From mboxrd@z Thu Jan 1 00:00:00 1970 From: Jagan Teki Subject: [PATCH 76/92] ram: rk3399: Update lpddr4 mode_sel based on io settings Date: Tue, 11 Jun 2019 20:21:19 +0530 Message-ID: <20190611145135.21399-77-jagan@amarulasolutions.com> References: <20190611145135.21399-1-jagan@amarulasolutions.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <20190611145135.21399-1-jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+glpar-linux-rockchip=m.gmane.org-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org To: Simon Glass , Philipp Tomsich , Kever Yang , YouMin Chen , u-boot-0aAXYlwwYIKGBzrmiIFOJg@public.gmane.org Cc: linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org, linux-amarula-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org, Jagan Teki , gajjar04akash-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org List-Id: linux-rockchip.vger.kernel.org The mode_sel on lpddr4 value is depending on IO settings of rd_vref. Add support for it. Signed-off-by: Jagan Teki Signed-off-by: YouMin Chen --- drivers/ram/rockchip/sdram_rk3399.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c index 413469f4cc..618327983a 100644 --- a/drivers/ram/rockchip/sdram_rk3399.c +++ b/drivers/ram/rockchip/sdram_rk3399.c @@ -349,7 +349,7 @@ static int phy_io_config(const struct chan_info *chan, u32 drv_value, odt_value; u32 speed; - /* vref setting */ + /* vref setting & mode setting */ if (sdram_params->base.dramtype == LPDDR4) { struct io_setting *io = lpddr4_get_io_settings(sdram_params, mr5); @@ -358,15 +358,18 @@ static int phy_io_config(const struct chan_info *chan, if (rd_vref < 36700) { /* MODE_LV[2:0] = LPDDR4 (Range 2)*/ vref_mode_dq = 0x7; + /* MODE[2:0]= LPDDR4 Range 2(0.4*VDDQ) */ + mode_sel = 0x5; vref_value_dq = (rd_vref - 3300) / 521; } else { /* MODE_LV[2:0] = LPDDR4 (Range 1)*/ vref_mode_dq = 0x6; + /* MODE[2:0]= LPDDR4 Range 1(0.33*VDDQ) */ + mode_sel = 0x4; vref_value_dq = (rd_vref - 15300) / 521; } vref_mode_ac = 0x6; vref_value_ac = 0x1f; - mode_sel = 0x6; } else if (sdram_params->base.dramtype == LPDDR3) { if (sdram_params->base.odt == 1) { vref_mode_dq = 0x5; /* LPDDR3 ODT */ -- 2.18.0.321.gffc6fa0e3 From mboxrd@z Thu Jan 1 00:00:00 1970 From: Jagan Teki Date: Tue, 11 Jun 2019 20:21:19 +0530 Subject: [U-Boot] [PATCH 76/92] ram: rk3399: Update lpddr4 mode_sel based on io settings In-Reply-To: <20190611145135.21399-1-jagan@amarulasolutions.com> References: <20190611145135.21399-1-jagan@amarulasolutions.com> Message-ID: <20190611145135.21399-77-jagan@amarulasolutions.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de The mode_sel on lpddr4 value is depending on IO settings of rd_vref. Add support for it. Signed-off-by: Jagan Teki Signed-off-by: YouMin Chen --- drivers/ram/rockchip/sdram_rk3399.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c index 413469f4cc..618327983a 100644 --- a/drivers/ram/rockchip/sdram_rk3399.c +++ b/drivers/ram/rockchip/sdram_rk3399.c @@ -349,7 +349,7 @@ static int phy_io_config(const struct chan_info *chan, u32 drv_value, odt_value; u32 speed; - /* vref setting */ + /* vref setting & mode setting */ if (sdram_params->base.dramtype == LPDDR4) { struct io_setting *io = lpddr4_get_io_settings(sdram_params, mr5); @@ -358,15 +358,18 @@ static int phy_io_config(const struct chan_info *chan, if (rd_vref < 36700) { /* MODE_LV[2:0] = LPDDR4 (Range 2)*/ vref_mode_dq = 0x7; + /* MODE[2:0]= LPDDR4 Range 2(0.4*VDDQ) */ + mode_sel = 0x5; vref_value_dq = (rd_vref - 3300) / 521; } else { /* MODE_LV[2:0] = LPDDR4 (Range 1)*/ vref_mode_dq = 0x6; + /* MODE[2:0]= LPDDR4 Range 1(0.33*VDDQ) */ + mode_sel = 0x4; vref_value_dq = (rd_vref - 15300) / 521; } vref_mode_ac = 0x6; vref_value_ac = 0x1f; - mode_sel = 0x6; } else if (sdram_params->base.dramtype == LPDDR3) { if (sdram_params->base.odt == 1) { vref_mode_dq = 0x5; /* LPDDR3 ODT */ -- 2.18.0.321.gffc6fa0e3