From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.2 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS, USER_AGENT_MUTT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 97CA1C46477 for ; Wed, 12 Jun 2019 13:54:08 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 7CAD321019 for ; Wed, 12 Jun 2019 13:54:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2409178AbfFLNyI (ORCPT ); Wed, 12 Jun 2019 09:54:08 -0400 Received: from foss.arm.com ([217.140.110.172]:53604 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2409112AbfFLNyF (ORCPT ); Wed, 12 Jun 2019 09:54:05 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 9224228; Wed, 12 Jun 2019 06:54:04 -0700 (PDT) Received: from redmoon (unknown [10.1.196.255]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 8EDE13F557; Wed, 12 Jun 2019 06:54:02 -0700 (PDT) Date: Wed, 12 Jun 2019 14:54:00 +0100 From: Lorenzo Pieralisi To: "Z.q. Hou" Cc: "linux-pci@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , "devicetree@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "bhelgaas@google.com" , "robh+dt@kernel.org" , "mark.rutland@arm.com" , "l.subrahmanya@mobiveil.co.in" , "shawnguo@kernel.org" , Leo Li , "catalin.marinas@arm.com" , "will.deacon@arm.com" , Mingkai Hu , "M.h. Lian" , Xiaowei Bao Subject: Re: [PATCHv5 19/20] PCI: mobiveil: Add 8-bit and 16-bit register accessors Message-ID: <20190612135400.GB15747@redmoon> References: <20190412083635.33626-1-Zhiqiang.Hou@nxp.com> <20190412083635.33626-20-Zhiqiang.Hou@nxp.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20190412083635.33626-20-Zhiqiang.Hou@nxp.com> User-Agent: Mutt/1.9.4 (2018-02-28) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri, Apr 12, 2019 at 08:37:05AM +0000, Z.q. Hou wrote: > From: Hou Zhiqiang > > There are some 8-bit and 16-bit registers in PCIe > configuration space, so add accessors for them. > > Signed-off-by: Hou Zhiqiang > Reviewed-by: Minghuan Lian > Reviewed-by: Subrahmanya Lingappa > --- > V5: > - Corrected and retouched the subject and changelog. > - No functionality change. > > drivers/pci/controller/pcie-mobiveil.c | 20 ++++++++++++++++++++ > 1 file changed, 20 insertions(+) > > diff --git a/drivers/pci/controller/pcie-mobiveil.c b/drivers/pci/controller/pcie-mobiveil.c > index 411e9779da12..456adfee393c 100644 > --- a/drivers/pci/controller/pcie-mobiveil.c > +++ b/drivers/pci/controller/pcie-mobiveil.c > @@ -268,11 +268,31 @@ static u32 csr_readl(struct mobiveil_pcie *pcie, u32 off) > return csr_read(pcie, off, 0x4); > } > > +static u32 csr_readw(struct mobiveil_pcie *pcie, u32 off) > +{ > + return csr_read(pcie, off, 0x2); > +} > + > +static u32 csr_readb(struct mobiveil_pcie *pcie, u32 off) > +{ > + return csr_read(pcie, off, 0x1); > +} > + > static void csr_writel(struct mobiveil_pcie *pcie, u32 val, u32 off) > { > csr_write(pcie, val, off, 0x4); > } > > +static void csr_writew(struct mobiveil_pcie *pcie, u32 val, u32 off) > +{ > + csr_write(pcie, val, off, 0x2); > +} > + > +static void csr_writeb(struct mobiveil_pcie *pcie, u32 val, u32 off) > +{ > + csr_write(pcie, val, off, 0x1); > +} > + They are not used so you should drop this patch. Lorenzo > static bool mobiveil_pcie_link_up(struct mobiveil_pcie *pcie) > { > return (csr_readl(pcie, LTSSM_STATUS) & > -- > 2.17.1 > From mboxrd@z Thu Jan 1 00:00:00 1970 From: Lorenzo Pieralisi Subject: Re: [PATCHv5 19/20] PCI: mobiveil: Add 8-bit and 16-bit register accessors Date: Wed, 12 Jun 2019 14:54:00 +0100 Message-ID: <20190612135400.GB15747@redmoon> References: <20190412083635.33626-1-Zhiqiang.Hou@nxp.com> <20190412083635.33626-20-Zhiqiang.Hou@nxp.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Content-Disposition: inline In-Reply-To: <20190412083635.33626-20-Zhiqiang.Hou@nxp.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=m.gmane.org@lists.infradead.org To: "Z.q. Hou" Cc: "mark.rutland@arm.com" , "devicetree@vger.kernel.org" , Xiaowei Bao , "linux-pci@vger.kernel.org" , "l.subrahmanya@mobiveil.co.in" , "will.deacon@arm.com" , "linux-kernel@vger.kernel.org" , Leo Li , "M.h. Lian" , "robh+dt@kernel.org" , Mingkai Hu , "catalin.marinas@arm.com" , "bhelgaas@google.com" , "shawnguo@kernel.org" , "linux-arm-kernel@lists.infradead.org" List-Id: devicetree@vger.kernel.org On Fri, Apr 12, 2019 at 08:37:05AM +0000, Z.q. Hou wrote: > From: Hou Zhiqiang > > There are some 8-bit and 16-bit registers in PCIe > configuration space, so add accessors for them. > > Signed-off-by: Hou Zhiqiang > Reviewed-by: Minghuan Lian > Reviewed-by: Subrahmanya Lingappa > --- > V5: > - Corrected and retouched the subject and changelog. > - No functionality change. > > drivers/pci/controller/pcie-mobiveil.c | 20 ++++++++++++++++++++ > 1 file changed, 20 insertions(+) > > diff --git a/drivers/pci/controller/pcie-mobiveil.c b/drivers/pci/controller/pcie-mobiveil.c > index 411e9779da12..456adfee393c 100644 > --- a/drivers/pci/controller/pcie-mobiveil.c > +++ b/drivers/pci/controller/pcie-mobiveil.c > @@ -268,11 +268,31 @@ static u32 csr_readl(struct mobiveil_pcie *pcie, u32 off) > return csr_read(pcie, off, 0x4); > } > > +static u32 csr_readw(struct mobiveil_pcie *pcie, u32 off) > +{ > + return csr_read(pcie, off, 0x2); > +} > + > +static u32 csr_readb(struct mobiveil_pcie *pcie, u32 off) > +{ > + return csr_read(pcie, off, 0x1); > +} > + > static void csr_writel(struct mobiveil_pcie *pcie, u32 val, u32 off) > { > csr_write(pcie, val, off, 0x4); > } > > +static void csr_writew(struct mobiveil_pcie *pcie, u32 val, u32 off) > +{ > + csr_write(pcie, val, off, 0x2); > +} > + > +static void csr_writeb(struct mobiveil_pcie *pcie, u32 val, u32 off) > +{ > + csr_write(pcie, val, off, 0x1); > +} > + They are not used so you should drop this patch. Lorenzo > static bool mobiveil_pcie_link_up(struct mobiveil_pcie *pcie) > { > return (csr_readl(pcie, LTSSM_STATUS) & > -- > 2.17.1 > From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.2 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,USER_AGENT_MUTT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id EFF3CC31E46 for ; Wed, 12 Jun 2019 13:54:15 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id C35D320874 for ; Wed, 12 Jun 2019 13:54:15 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="gT6kDWjO" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org C35D320874 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=56J4lyDAsFD7bb954P+V0b7knX+RmM0CoCevR4i2MTk=; b=gT6kDWjO+h/LhD Xk6HiQbZ8ATRPvcfAsjxVLqWrhU8bPHQ8Ca0O8PyRTHPVD7tNxaatJj2BxVVDNQlGNgKMWhjNQSrQ Orbj4Ee6OBc55KZOr7IGajvjohLO9LN68Y0aOcc2NHQ3THLvFHfM2heArtKagr4Q8JKYVbCB+zZCV 1xl8iSFIoJcK+Nd2DKBxx2eAiPE6+Cu61M01aT4TKBCzaE21XTBXscYfsTLb0bm15cyhVPFFFjy2y +6f22ROGAb0OdWN2WbYW/EBzWywFBZcC4rHFzifn10p1jBSos3LgkR+vuyAXqnoJuO+KTrUwKSGHt JQmGtp9roGy8pz9Dc/ew==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.92 #3 (Red Hat Linux)) id 1hb3hX-00076r-UZ; Wed, 12 Jun 2019 13:54:07 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.92 #3 (Red Hat Linux)) id 1hb3hV-00076B-Cf for linux-arm-kernel@lists.infradead.org; Wed, 12 Jun 2019 13:54:06 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 9224228; Wed, 12 Jun 2019 06:54:04 -0700 (PDT) Received: from redmoon (unknown [10.1.196.255]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 8EDE13F557; Wed, 12 Jun 2019 06:54:02 -0700 (PDT) Date: Wed, 12 Jun 2019 14:54:00 +0100 From: Lorenzo Pieralisi To: "Z.q. Hou" Subject: Re: [PATCHv5 19/20] PCI: mobiveil: Add 8-bit and 16-bit register accessors Message-ID: <20190612135400.GB15747@redmoon> References: <20190412083635.33626-1-Zhiqiang.Hou@nxp.com> <20190412083635.33626-20-Zhiqiang.Hou@nxp.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20190412083635.33626-20-Zhiqiang.Hou@nxp.com> User-Agent: Mutt/1.9.4 (2018-02-28) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190612_065405_472411_620C344A X-CRM114-Status: GOOD ( 14.50 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "mark.rutland@arm.com" , "devicetree@vger.kernel.org" , Xiaowei Bao , "linux-pci@vger.kernel.org" , "l.subrahmanya@mobiveil.co.in" , "will.deacon@arm.com" , "linux-kernel@vger.kernel.org" , Leo Li , "M.h. Lian" , "robh+dt@kernel.org" , Mingkai Hu , "catalin.marinas@arm.com" , "bhelgaas@google.com" , "shawnguo@kernel.org" , "linux-arm-kernel@lists.infradead.org" Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Fri, Apr 12, 2019 at 08:37:05AM +0000, Z.q. Hou wrote: > From: Hou Zhiqiang > > There are some 8-bit and 16-bit registers in PCIe > configuration space, so add accessors for them. > > Signed-off-by: Hou Zhiqiang > Reviewed-by: Minghuan Lian > Reviewed-by: Subrahmanya Lingappa > --- > V5: > - Corrected and retouched the subject and changelog. > - No functionality change. > > drivers/pci/controller/pcie-mobiveil.c | 20 ++++++++++++++++++++ > 1 file changed, 20 insertions(+) > > diff --git a/drivers/pci/controller/pcie-mobiveil.c b/drivers/pci/controller/pcie-mobiveil.c > index 411e9779da12..456adfee393c 100644 > --- a/drivers/pci/controller/pcie-mobiveil.c > +++ b/drivers/pci/controller/pcie-mobiveil.c > @@ -268,11 +268,31 @@ static u32 csr_readl(struct mobiveil_pcie *pcie, u32 off) > return csr_read(pcie, off, 0x4); > } > > +static u32 csr_readw(struct mobiveil_pcie *pcie, u32 off) > +{ > + return csr_read(pcie, off, 0x2); > +} > + > +static u32 csr_readb(struct mobiveil_pcie *pcie, u32 off) > +{ > + return csr_read(pcie, off, 0x1); > +} > + > static void csr_writel(struct mobiveil_pcie *pcie, u32 val, u32 off) > { > csr_write(pcie, val, off, 0x4); > } > > +static void csr_writew(struct mobiveil_pcie *pcie, u32 val, u32 off) > +{ > + csr_write(pcie, val, off, 0x2); > +} > + > +static void csr_writeb(struct mobiveil_pcie *pcie, u32 val, u32 off) > +{ > + csr_write(pcie, val, off, 0x1); > +} > + They are not used so you should drop this patch. Lorenzo > static bool mobiveil_pcie_link_up(struct mobiveil_pcie *pcie) > { > return (csr_readl(pcie, LTSSM_STATUS) & > -- > 2.17.1 > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel