From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.6 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 76B64C31E4B for ; Fri, 14 Jun 2019 13:13:08 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 3328420850 for ; Fri, 14 Jun 2019 13:13:08 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="fiB5wkBV" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728044AbfFNNNG (ORCPT ); Fri, 14 Jun 2019 09:13:06 -0400 Received: from mail-qk1-f195.google.com ([209.85.222.195]:46900 "EHLO mail-qk1-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726874AbfFNNNG (ORCPT ); Fri, 14 Jun 2019 09:13:06 -0400 Received: by mail-qk1-f195.google.com with SMTP id x18so1570828qkn.13 for ; Fri, 14 Jun 2019 06:13:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id; bh=+tFDksFffEpGXWf74d3vaKdXMAyKwc+2Rp4MyFwCKVQ=; b=fiB5wkBVxsKeL5k+KkAGrFlUmSk1byl/GiN2Xo9gy/7cEid5eY0hXmwLwDRizYspa4 oopJRiJUoBO3mRPxNIL+uwsH37O7Fa8SQLVmSYYd/uE18+Nret8ONqT3S4xaq/6sVxAN uhn9N23jWd41HX1joxngZLUZ6P27FDH/hpovd4G11oOn9gkdRuMNDhIa7/4opnT8GGn8 fF9y9/AW4idvXftY6zMTtrI9fDg8TTQSo6pCrDFHW+Z30Ggi6MuRNvZVwguGP2u4sMnS 3lD8R+PSQNxpbYIdTWbLpGf0Bzs78+O/M/FTdJJi1FKjsP/7oE9MRWhcf8EN1EdonIn8 Zn3g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=+tFDksFffEpGXWf74d3vaKdXMAyKwc+2Rp4MyFwCKVQ=; b=razBzapivphs7iiSzwrHy69UKtSrRdWm/WgYA96eH/uu3vIoHpuuK5KsJg3hF0uDt/ BThepQ5Rais8l8dyvQ+tsyRuj0o1d55drQEvup6+QDsrAE0mBAo/HIg6Ak3CA+9i68KA llTUGkQNdfgbD8j9fvbXVwQFrZkCjN7a7pGfbkHUIREhvEc8Jxzc074Xe6IhEtdwN7N7 /NIMBhv8Vt5bmxxD1yuxXpWGZT7+P1x4Jw/3owqL0FFHS+BIcPSgYoB4p5gCgpIs5NEl kpeu9MDurBGIof6v1u83e7xo2DVFJctOy5AEcnpvK5HZg/OylWNPhMIzDQMj23MNyJZf AfGw== X-Gm-Message-State: APjAAAX63WAcra+ukK1OFevdaMqO0CA+QaQV43dt2UjnktNOT1W7mi3I r/r/kJavRqkJr0h079eEZw== X-Google-Smtp-Source: APXvYqwCZcVCKo1fyJFmDmeZVjNujYgLtaS2EAtung+hF1kdgQvDNS6dXhUFlZJN2BWHrufFLDkWgg== X-Received: by 2002:a37:5407:: with SMTP id i7mr3763273qkb.149.1560517985220; Fri, 14 Jun 2019 06:13:05 -0700 (PDT) Received: from gabell.bos.redhat.com (nat-pool-bos-t.redhat.com. [66.187.233.206]) by smtp.gmail.com with ESMTPSA id i30sm1563893qtb.18.2019.06.14.06.13.04 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Fri, 14 Jun 2019 06:13:04 -0700 (PDT) From: Masayoshi Mizuma To: Catalin Marinas , Robin Murphy , Will Deacon , linux-arm-kernel@lists.infradead.org Cc: Masayoshi Mizuma , Masayoshi Mizuma , linux-kernel@vger.kernel.org, Hidetoshi Seto , Zhang Lei Subject: [PATCH v2] arm64/mm: Correct the cache line size warning with non coherent device Date: Fri, 14 Jun 2019 09:11:41 -0400 Message-Id: <20190614131141.4428-1-msys.mizuma@gmail.com> X-Mailer: git-send-email 2.17.1 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Masayoshi Mizuma If the cache line size is greater than ARCH_DMA_MINALIGN (128), the warning shows and it's tainted as TAINT_CPU_OUT_OF_SPEC. However, it's not good because as discussed in the thread [1], the cpu cache line size will be problem only on non-coherent devices. Since the coherent flag is already introduced to struct device, show the warning only if the device is non-coherent device and ARCH_DMA_MINALIGN is smaller than the cpu cache size. [1] https://lore.kernel.org/linux-arm-kernel/20180514145703.celnlobzn3uh5tc2@localhost/ Signed-off-by: Masayoshi Mizuma Reviewed-by: Hidetoshi Seto Tested-by: Zhang Lei --- arch/arm64/include/asm/cache.h | 7 +++++++ arch/arm64/kernel/cacheinfo.c | 4 +--- arch/arm64/mm/dma-mapping.c | 14 ++++++++++---- 3 files changed, 18 insertions(+), 7 deletions(-) diff --git a/arch/arm64/include/asm/cache.h b/arch/arm64/include/asm/cache.h index 758af6340314..d24b7c1ecd9b 100644 --- a/arch/arm64/include/asm/cache.h +++ b/arch/arm64/include/asm/cache.h @@ -91,6 +91,13 @@ static inline u32 cache_type_cwg(void) #define __read_mostly __attribute__((__section__(".data..read_mostly"))) +static inline int cache_line_size_of_cpu(void) +{ + u32 cwg = cache_type_cwg(); + + return cwg ? 4 << cwg : ARCH_DMA_MINALIGN; +} + int cache_line_size(void); /* diff --git a/arch/arm64/kernel/cacheinfo.c b/arch/arm64/kernel/cacheinfo.c index 6eaf1c07aa4e..7fa6828bb488 100644 --- a/arch/arm64/kernel/cacheinfo.c +++ b/arch/arm64/kernel/cacheinfo.c @@ -19,12 +19,10 @@ int cache_line_size(void) { - u32 cwg = cache_type_cwg(); - if (coherency_max_size != 0) return coherency_max_size; - return cwg ? 4 << cwg : ARCH_DMA_MINALIGN; + return cache_line_size_of_cpu(); } EXPORT_SYMBOL_GPL(cache_line_size); diff --git a/arch/arm64/mm/dma-mapping.c b/arch/arm64/mm/dma-mapping.c index 1669618db08a..379589dc7113 100644 --- a/arch/arm64/mm/dma-mapping.c +++ b/arch/arm64/mm/dma-mapping.c @@ -38,10 +38,6 @@ void arch_dma_prep_coherent(struct page *page, size_t size) static int __init arm64_dma_init(void) { - WARN_TAINT(ARCH_DMA_MINALIGN < cache_line_size(), - TAINT_CPU_OUT_OF_SPEC, - "ARCH_DMA_MINALIGN smaller than CTR_EL0.CWG (%d < %d)", - ARCH_DMA_MINALIGN, cache_line_size()); return dma_atomic_pool_init(GFP_DMA32, __pgprot(PROT_NORMAL_NC)); } arch_initcall(arm64_dma_init); @@ -56,7 +52,17 @@ void arch_teardown_dma_ops(struct device *dev) void arch_setup_dma_ops(struct device *dev, u64 dma_base, u64 size, const struct iommu_ops *iommu, bool coherent) { + int cls = cache_line_size_of_cpu(); + dev->dma_coherent = coherent; + + if (!coherent) + WARN_TAINT(cls > ARCH_DMA_MINALIGN, + TAINT_CPU_OUT_OF_SPEC, + "%s %s: ARCH_DMA_MINALIGN smaller than CTR_EL0.CWG (%d < %d)", + dev_driver_string(dev), dev_name(dev), + ARCH_DMA_MINALIGN, cls); + if (iommu) iommu_setup_dma_ops(dev, dma_base, size); -- 2.20.1 From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.5 required=3.0 tests=DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED,DKIM_VALID,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 594D6C31E4B for ; Fri, 14 Jun 2019 13:13:18 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 1687D20850 for ; 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[66.187.233.206]) by smtp.gmail.com with ESMTPSA id i30sm1563893qtb.18.2019.06.14.06.13.04 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Fri, 14 Jun 2019 06:13:04 -0700 (PDT) From: Masayoshi Mizuma To: Catalin Marinas , Robin Murphy , Will Deacon , linux-arm-kernel@lists.infradead.org Subject: [PATCH v2] arm64/mm: Correct the cache line size warning with non coherent device Date: Fri, 14 Jun 2019 09:11:41 -0400 Message-Id: <20190614131141.4428-1-msys.mizuma@gmail.com> X-Mailer: git-send-email 2.17.1 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190614_061307_014023_D01ADBF3 X-CRM114-Status: GOOD ( 13.73 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Masayoshi Mizuma , Hidetoshi Seto , Masayoshi Mizuma , linux-kernel@vger.kernel.org, Zhang Lei MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Masayoshi Mizuma If the cache line size is greater than ARCH_DMA_MINALIGN (128), the warning shows and it's tainted as TAINT_CPU_OUT_OF_SPEC. However, it's not good because as discussed in the thread [1], the cpu cache line size will be problem only on non-coherent devices. Since the coherent flag is already introduced to struct device, show the warning only if the device is non-coherent device and ARCH_DMA_MINALIGN is smaller than the cpu cache size. [1] https://lore.kernel.org/linux-arm-kernel/20180514145703.celnlobzn3uh5tc2@localhost/ Signed-off-by: Masayoshi Mizuma Reviewed-by: Hidetoshi Seto Tested-by: Zhang Lei --- arch/arm64/include/asm/cache.h | 7 +++++++ arch/arm64/kernel/cacheinfo.c | 4 +--- arch/arm64/mm/dma-mapping.c | 14 ++++++++++---- 3 files changed, 18 insertions(+), 7 deletions(-) diff --git a/arch/arm64/include/asm/cache.h b/arch/arm64/include/asm/cache.h index 758af6340314..d24b7c1ecd9b 100644 --- a/arch/arm64/include/asm/cache.h +++ b/arch/arm64/include/asm/cache.h @@ -91,6 +91,13 @@ static inline u32 cache_type_cwg(void) #define __read_mostly __attribute__((__section__(".data..read_mostly"))) +static inline int cache_line_size_of_cpu(void) +{ + u32 cwg = cache_type_cwg(); + + return cwg ? 4 << cwg : ARCH_DMA_MINALIGN; +} + int cache_line_size(void); /* diff --git a/arch/arm64/kernel/cacheinfo.c b/arch/arm64/kernel/cacheinfo.c index 6eaf1c07aa4e..7fa6828bb488 100644 --- a/arch/arm64/kernel/cacheinfo.c +++ b/arch/arm64/kernel/cacheinfo.c @@ -19,12 +19,10 @@ int cache_line_size(void) { - u32 cwg = cache_type_cwg(); - if (coherency_max_size != 0) return coherency_max_size; - return cwg ? 4 << cwg : ARCH_DMA_MINALIGN; + return cache_line_size_of_cpu(); } EXPORT_SYMBOL_GPL(cache_line_size); diff --git a/arch/arm64/mm/dma-mapping.c b/arch/arm64/mm/dma-mapping.c index 1669618db08a..379589dc7113 100644 --- a/arch/arm64/mm/dma-mapping.c +++ b/arch/arm64/mm/dma-mapping.c @@ -38,10 +38,6 @@ void arch_dma_prep_coherent(struct page *page, size_t size) static int __init arm64_dma_init(void) { - WARN_TAINT(ARCH_DMA_MINALIGN < cache_line_size(), - TAINT_CPU_OUT_OF_SPEC, - "ARCH_DMA_MINALIGN smaller than CTR_EL0.CWG (%d < %d)", - ARCH_DMA_MINALIGN, cache_line_size()); return dma_atomic_pool_init(GFP_DMA32, __pgprot(PROT_NORMAL_NC)); } arch_initcall(arm64_dma_init); @@ -56,7 +52,17 @@ void arch_teardown_dma_ops(struct device *dev) void arch_setup_dma_ops(struct device *dev, u64 dma_base, u64 size, const struct iommu_ops *iommu, bool coherent) { + int cls = cache_line_size_of_cpu(); + dev->dma_coherent = coherent; + + if (!coherent) + WARN_TAINT(cls > ARCH_DMA_MINALIGN, + TAINT_CPU_OUT_OF_SPEC, + "%s %s: ARCH_DMA_MINALIGN smaller than CTR_EL0.CWG (%d < %d)", + dev_driver_string(dev), dev_name(dev), + ARCH_DMA_MINALIGN, cls); + if (iommu) iommu_setup_dma_ops(dev, dma_base, size); -- 2.20.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel