* [Qemu-devel] [PATCH 0/5] Various i.MX7 fixes
@ 2019-04-16 1:38 ` Andrey Smirnov
0 siblings, 0 replies; 21+ messages in thread
From: Andrey Smirnov @ 2019-04-16 1:38 UTC (permalink / raw)
To: qemu-arm; +Cc: Andrey Smirnov, Peter Maydell, Michael S . Tsirkin, qemu-devel
Everyone:
I recently revisited my i.MX7 work and this series contains all of the
fixes I had to make to get it to work with latest (5.1-rc1) Linux
kernel again as well as fixes for genuine bugs that I somehow missed
during original submission ("pci: designware" patches). Hopefully each
patch is self-explanatory.
Feedback is welcome!
Thanks,
Andrey Smirnov
Andrey Smirnov (5):
i.mx7d: Add no-op/unimplemented APBH DMA module
i.mx7d: Add no-op/unimplemented PCIE PHY IP block
pci: designware: Update MSI mapping unconditionally
pci: designware: Update MSI mapping when MSI address changes
i.mx7d: pci: Update PCI IRQ mapping to match HW
include/hw/arm/fsl-imx7.h | 14 ++++++++++----
hw/arm/fsl-imx7.c | 11 +++++++++++
hw/pci-host/designware.c | 18 ++++++++----------
3 files changed, 29 insertions(+), 14 deletions(-)
--
2.20.1
^ permalink raw reply [flat|nested] 21+ messages in thread
* [Qemu-devel] [PATCH 0/5] Various i.MX7 fixes
@ 2019-04-16 1:38 ` Andrey Smirnov
0 siblings, 0 replies; 21+ messages in thread
From: Andrey Smirnov @ 2019-04-16 1:38 UTC (permalink / raw)
To: qemu-arm; +Cc: Andrey Smirnov, Peter Maydell, qemu-devel, Michael S . Tsirkin
Everyone:
I recently revisited my i.MX7 work and this series contains all of the
fixes I had to make to get it to work with latest (5.1-rc1) Linux
kernel again as well as fixes for genuine bugs that I somehow missed
during original submission ("pci: designware" patches). Hopefully each
patch is self-explanatory.
Feedback is welcome!
Thanks,
Andrey Smirnov
Andrey Smirnov (5):
i.mx7d: Add no-op/unimplemented APBH DMA module
i.mx7d: Add no-op/unimplemented PCIE PHY IP block
pci: designware: Update MSI mapping unconditionally
pci: designware: Update MSI mapping when MSI address changes
i.mx7d: pci: Update PCI IRQ mapping to match HW
include/hw/arm/fsl-imx7.h | 14 ++++++++++----
hw/arm/fsl-imx7.c | 11 +++++++++++
hw/pci-host/designware.c | 18 ++++++++----------
3 files changed, 29 insertions(+), 14 deletions(-)
--
2.20.1
^ permalink raw reply [flat|nested] 21+ messages in thread
* [Qemu-devel] [PATCH 1/5] i.mx7d: Add no-op/unimplemented APBH DMA module
@ 2019-04-16 1:38 ` Andrey Smirnov
0 siblings, 0 replies; 21+ messages in thread
From: Andrey Smirnov @ 2019-04-16 1:38 UTC (permalink / raw)
To: qemu-arm; +Cc: Andrey Smirnov, Peter Maydell, Michael S . Tsirkin, qemu-devel
Instantiate no-op APBH DMA module. Needed to boot latest Linux kernel.
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Cc: Peter Maydell <peter.maydell@linaro.org>
Cc: Michael S. Tsirkin <mst@redhat.com>
Cc: qemu-devel@nongnu.org
Cc: qemu-arm@nongnu.org
---
include/hw/arm/fsl-imx7.h | 3 +++
hw/arm/fsl-imx7.c | 6 ++++++
2 files changed, 9 insertions(+)
diff --git a/include/hw/arm/fsl-imx7.h b/include/hw/arm/fsl-imx7.h
index d848262bfd..aae4f860fc 100644
--- a/include/hw/arm/fsl-imx7.h
+++ b/include/hw/arm/fsl-imx7.h
@@ -179,6 +179,9 @@ enum FslIMX7MemoryMap {
FSL_IMX7_PCIE_REG_SIZE = 16 * 1024,
FSL_IMX7_GPR_ADDR = 0x30340000,
+
+ FSL_IMX7_DMA_APBH_ADDR = 0x33000000,
+ FSL_IMX7_DMA_APBH_SIZE = 0x2000,
};
enum FslIMX7IRQs {
diff --git a/hw/arm/fsl-imx7.c b/hw/arm/fsl-imx7.c
index 7663ad6861..1abfa5910c 100644
--- a/hw/arm/fsl-imx7.c
+++ b/hw/arm/fsl-imx7.c
@@ -526,6 +526,12 @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
*/
create_unimplemented_device("lcdif", FSL_IMX7_LCDIF_ADDR,
FSL_IMX7_LCDIF_SIZE);
+
+ /*
+ * DMA APBH
+ */
+ create_unimplemented_device("dma-apbh", FSL_IMX7_DMA_APBH_ADDR,
+ FSL_IMX7_DMA_APBH_SIZE);
}
static void fsl_imx7_class_init(ObjectClass *oc, void *data)
--
2.20.1
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [Qemu-devel] [PATCH 1/5] i.mx7d: Add no-op/unimplemented APBH DMA module
@ 2019-04-16 1:38 ` Andrey Smirnov
0 siblings, 0 replies; 21+ messages in thread
From: Andrey Smirnov @ 2019-04-16 1:38 UTC (permalink / raw)
To: qemu-arm; +Cc: Andrey Smirnov, Peter Maydell, qemu-devel, Michael S . Tsirkin
Instantiate no-op APBH DMA module. Needed to boot latest Linux kernel.
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Cc: Peter Maydell <peter.maydell@linaro.org>
Cc: Michael S. Tsirkin <mst@redhat.com>
Cc: qemu-devel@nongnu.org
Cc: qemu-arm@nongnu.org
---
include/hw/arm/fsl-imx7.h | 3 +++
hw/arm/fsl-imx7.c | 6 ++++++
2 files changed, 9 insertions(+)
diff --git a/include/hw/arm/fsl-imx7.h b/include/hw/arm/fsl-imx7.h
index d848262bfd..aae4f860fc 100644
--- a/include/hw/arm/fsl-imx7.h
+++ b/include/hw/arm/fsl-imx7.h
@@ -179,6 +179,9 @@ enum FslIMX7MemoryMap {
FSL_IMX7_PCIE_REG_SIZE = 16 * 1024,
FSL_IMX7_GPR_ADDR = 0x30340000,
+
+ FSL_IMX7_DMA_APBH_ADDR = 0x33000000,
+ FSL_IMX7_DMA_APBH_SIZE = 0x2000,
};
enum FslIMX7IRQs {
diff --git a/hw/arm/fsl-imx7.c b/hw/arm/fsl-imx7.c
index 7663ad6861..1abfa5910c 100644
--- a/hw/arm/fsl-imx7.c
+++ b/hw/arm/fsl-imx7.c
@@ -526,6 +526,12 @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
*/
create_unimplemented_device("lcdif", FSL_IMX7_LCDIF_ADDR,
FSL_IMX7_LCDIF_SIZE);
+
+ /*
+ * DMA APBH
+ */
+ create_unimplemented_device("dma-apbh", FSL_IMX7_DMA_APBH_ADDR,
+ FSL_IMX7_DMA_APBH_SIZE);
}
static void fsl_imx7_class_init(ObjectClass *oc, void *data)
--
2.20.1
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [Qemu-devel] [PATCH 2/5] i.mx7d: Add no-op/unimplemented PCIE PHY IP block
@ 2019-04-16 1:38 ` Andrey Smirnov
0 siblings, 0 replies; 21+ messages in thread
From: Andrey Smirnov @ 2019-04-16 1:38 UTC (permalink / raw)
To: qemu-arm; +Cc: Andrey Smirnov, Peter Maydell, Michael S . Tsirkin, qemu-devel
Add no-op/unimplemented PCIE PHY IP block. Needed by new kernels to
use PCIE.
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Cc: Peter Maydell <peter.maydell@linaro.org>
Cc: Michael S. Tsirkin <mst@redhat.com>
Cc: qemu-devel@nongnu.org
Cc: qemu-arm@nongnu.org
---
include/hw/arm/fsl-imx7.h | 3 +++
hw/arm/fsl-imx7.c | 5 +++++
2 files changed, 8 insertions(+)
diff --git a/include/hw/arm/fsl-imx7.h b/include/hw/arm/fsl-imx7.h
index aae4f860fc..3efa697adc 100644
--- a/include/hw/arm/fsl-imx7.h
+++ b/include/hw/arm/fsl-imx7.h
@@ -125,6 +125,9 @@ enum FslIMX7MemoryMap {
FSL_IMX7_ADC2_ADDR = 0x30620000,
FSL_IMX7_ADCn_SIZE = 0x1000,
+ FSL_IMX7_PCIE_PHY_ADDR = 0x306D0000,
+ FSL_IMX7_PCIE_PHY_SIZE = 0x10000,
+
FSL_IMX7_GPC_ADDR = 0x303A0000,
FSL_IMX7_I2C1_ADDR = 0x30A20000,
diff --git a/hw/arm/fsl-imx7.c b/hw/arm/fsl-imx7.c
index 1abfa5910c..813fb55ca9 100644
--- a/hw/arm/fsl-imx7.c
+++ b/hw/arm/fsl-imx7.c
@@ -532,6 +532,11 @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
*/
create_unimplemented_device("dma-apbh", FSL_IMX7_DMA_APBH_ADDR,
FSL_IMX7_DMA_APBH_SIZE);
+ /*
+ * PCIe PHY
+ */
+ create_unimplemented_device("pcie-phy", FSL_IMX7_PCIE_PHY_ADDR,
+ FSL_IMX7_PCIE_PHY_SIZE);
}
static void fsl_imx7_class_init(ObjectClass *oc, void *data)
--
2.20.1
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [Qemu-devel] [PATCH 2/5] i.mx7d: Add no-op/unimplemented PCIE PHY IP block
@ 2019-04-16 1:38 ` Andrey Smirnov
0 siblings, 0 replies; 21+ messages in thread
From: Andrey Smirnov @ 2019-04-16 1:38 UTC (permalink / raw)
To: qemu-arm; +Cc: Andrey Smirnov, Peter Maydell, qemu-devel, Michael S . Tsirkin
Add no-op/unimplemented PCIE PHY IP block. Needed by new kernels to
use PCIE.
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Cc: Peter Maydell <peter.maydell@linaro.org>
Cc: Michael S. Tsirkin <mst@redhat.com>
Cc: qemu-devel@nongnu.org
Cc: qemu-arm@nongnu.org
---
include/hw/arm/fsl-imx7.h | 3 +++
hw/arm/fsl-imx7.c | 5 +++++
2 files changed, 8 insertions(+)
diff --git a/include/hw/arm/fsl-imx7.h b/include/hw/arm/fsl-imx7.h
index aae4f860fc..3efa697adc 100644
--- a/include/hw/arm/fsl-imx7.h
+++ b/include/hw/arm/fsl-imx7.h
@@ -125,6 +125,9 @@ enum FslIMX7MemoryMap {
FSL_IMX7_ADC2_ADDR = 0x30620000,
FSL_IMX7_ADCn_SIZE = 0x1000,
+ FSL_IMX7_PCIE_PHY_ADDR = 0x306D0000,
+ FSL_IMX7_PCIE_PHY_SIZE = 0x10000,
+
FSL_IMX7_GPC_ADDR = 0x303A0000,
FSL_IMX7_I2C1_ADDR = 0x30A20000,
diff --git a/hw/arm/fsl-imx7.c b/hw/arm/fsl-imx7.c
index 1abfa5910c..813fb55ca9 100644
--- a/hw/arm/fsl-imx7.c
+++ b/hw/arm/fsl-imx7.c
@@ -532,6 +532,11 @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
*/
create_unimplemented_device("dma-apbh", FSL_IMX7_DMA_APBH_ADDR,
FSL_IMX7_DMA_APBH_SIZE);
+ /*
+ * PCIe PHY
+ */
+ create_unimplemented_device("pcie-phy", FSL_IMX7_PCIE_PHY_ADDR,
+ FSL_IMX7_PCIE_PHY_SIZE);
}
static void fsl_imx7_class_init(ObjectClass *oc, void *data)
--
2.20.1
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [Qemu-devel] [PATCH 3/5] pci: designware: Update MSI mapping unconditionally
@ 2019-04-16 1:39 ` Andrey Smirnov
0 siblings, 0 replies; 21+ messages in thread
From: Andrey Smirnov @ 2019-04-16 1:39 UTC (permalink / raw)
To: qemu-arm; +Cc: Andrey Smirnov, Peter Maydell, Michael S . Tsirkin, qemu-devel
Expression to calculate update_msi_mapping in code handling writes to
DESIGNWARE_PCIE_MSI_INTR0_ENABLE is missing an ! operator and should
be:
!!root->msi.intr[0].enable ^ !!val;
so that MSI mapping is updated when enabled transitions from either
"none" -> "any" or "any" -> "none". Since that register shouldn't be
written to very often, change the code to update MSI mapping
unconditionally instead of trying to fix the update_msi_mapping logic.
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Cc: Peter Maydell <peter.maydell@linaro.org>
Cc: Michael S. Tsirkin <mst@redhat.com>
Cc: qemu-devel@nongnu.org
Cc: qemu-arm@nongnu.org
---
hw/pci-host/designware.c | 10 ++--------
1 file changed, 2 insertions(+), 8 deletions(-)
diff --git a/hw/pci-host/designware.c b/hw/pci-host/designware.c
index 29ea313798..6affe823c0 100644
--- a/hw/pci-host/designware.c
+++ b/hw/pci-host/designware.c
@@ -296,16 +296,10 @@ static void designware_pcie_root_config_write(PCIDevice *d, uint32_t address,
root->msi.base |= (uint64_t)val << 32;
break;
- case DESIGNWARE_PCIE_MSI_INTR0_ENABLE: {
- const bool update_msi_mapping = !root->msi.intr[0].enable ^ !!val;
-
+ case DESIGNWARE_PCIE_MSI_INTR0_ENABLE:
root->msi.intr[0].enable = val;
-
- if (update_msi_mapping) {
- designware_pcie_root_update_msi_mapping(root);
- }
+ designware_pcie_root_update_msi_mapping(root);
break;
- }
case DESIGNWARE_PCIE_MSI_INTR0_MASK:
root->msi.intr[0].mask = val;
--
2.20.1
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [Qemu-devel] [PATCH 3/5] pci: designware: Update MSI mapping unconditionally
@ 2019-04-16 1:39 ` Andrey Smirnov
0 siblings, 0 replies; 21+ messages in thread
From: Andrey Smirnov @ 2019-04-16 1:39 UTC (permalink / raw)
To: qemu-arm; +Cc: Andrey Smirnov, Peter Maydell, qemu-devel, Michael S . Tsirkin
Expression to calculate update_msi_mapping in code handling writes to
DESIGNWARE_PCIE_MSI_INTR0_ENABLE is missing an ! operator and should
be:
!!root->msi.intr[0].enable ^ !!val;
so that MSI mapping is updated when enabled transitions from either
"none" -> "any" or "any" -> "none". Since that register shouldn't be
written to very often, change the code to update MSI mapping
unconditionally instead of trying to fix the update_msi_mapping logic.
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Cc: Peter Maydell <peter.maydell@linaro.org>
Cc: Michael S. Tsirkin <mst@redhat.com>
Cc: qemu-devel@nongnu.org
Cc: qemu-arm@nongnu.org
---
hw/pci-host/designware.c | 10 ++--------
1 file changed, 2 insertions(+), 8 deletions(-)
diff --git a/hw/pci-host/designware.c b/hw/pci-host/designware.c
index 29ea313798..6affe823c0 100644
--- a/hw/pci-host/designware.c
+++ b/hw/pci-host/designware.c
@@ -296,16 +296,10 @@ static void designware_pcie_root_config_write(PCIDevice *d, uint32_t address,
root->msi.base |= (uint64_t)val << 32;
break;
- case DESIGNWARE_PCIE_MSI_INTR0_ENABLE: {
- const bool update_msi_mapping = !root->msi.intr[0].enable ^ !!val;
-
+ case DESIGNWARE_PCIE_MSI_INTR0_ENABLE:
root->msi.intr[0].enable = val;
-
- if (update_msi_mapping) {
- designware_pcie_root_update_msi_mapping(root);
- }
+ designware_pcie_root_update_msi_mapping(root);
break;
- }
case DESIGNWARE_PCIE_MSI_INTR0_MASK:
root->msi.intr[0].mask = val;
--
2.20.1
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [Qemu-devel] [PATCH 4/5] pci: designware: Update MSI mapping when MSI address changes
@ 2019-04-16 1:39 ` Andrey Smirnov
0 siblings, 0 replies; 21+ messages in thread
From: Andrey Smirnov @ 2019-04-16 1:39 UTC (permalink / raw)
To: qemu-arm; +Cc: Andrey Smirnov, Peter Maydell, Michael S . Tsirkin, qemu-devel
MSI mapping needs to be update when MSI address changes, so add the
code to do so.
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Cc: Peter Maydell <peter.maydell@linaro.org>
Cc: Michael S. Tsirkin <mst@redhat.com>
Cc: qemu-devel@nongnu.org
Cc: qemu-arm@nongnu.org
---
hw/pci-host/designware.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/hw/pci-host/designware.c b/hw/pci-host/designware.c
index 6affe823c0..e80facc4a0 100644
--- a/hw/pci-host/designware.c
+++ b/hw/pci-host/designware.c
@@ -289,11 +289,13 @@ static void designware_pcie_root_config_write(PCIDevice *d, uint32_t address,
case DESIGNWARE_PCIE_MSI_ADDR_LO:
root->msi.base &= 0xFFFFFFFF00000000ULL;
root->msi.base |= val;
+ designware_pcie_root_update_msi_mapping(root);
break;
case DESIGNWARE_PCIE_MSI_ADDR_HI:
root->msi.base &= 0x00000000FFFFFFFFULL;
root->msi.base |= (uint64_t)val << 32;
+ designware_pcie_root_update_msi_mapping(root);
break;
case DESIGNWARE_PCIE_MSI_INTR0_ENABLE:
--
2.20.1
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [Qemu-devel] [PATCH 4/5] pci: designware: Update MSI mapping when MSI address changes
@ 2019-04-16 1:39 ` Andrey Smirnov
0 siblings, 0 replies; 21+ messages in thread
From: Andrey Smirnov @ 2019-04-16 1:39 UTC (permalink / raw)
To: qemu-arm; +Cc: Andrey Smirnov, Peter Maydell, qemu-devel, Michael S . Tsirkin
MSI mapping needs to be update when MSI address changes, so add the
code to do so.
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Cc: Peter Maydell <peter.maydell@linaro.org>
Cc: Michael S. Tsirkin <mst@redhat.com>
Cc: qemu-devel@nongnu.org
Cc: qemu-arm@nongnu.org
---
hw/pci-host/designware.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/hw/pci-host/designware.c b/hw/pci-host/designware.c
index 6affe823c0..e80facc4a0 100644
--- a/hw/pci-host/designware.c
+++ b/hw/pci-host/designware.c
@@ -289,11 +289,13 @@ static void designware_pcie_root_config_write(PCIDevice *d, uint32_t address,
case DESIGNWARE_PCIE_MSI_ADDR_LO:
root->msi.base &= 0xFFFFFFFF00000000ULL;
root->msi.base |= val;
+ designware_pcie_root_update_msi_mapping(root);
break;
case DESIGNWARE_PCIE_MSI_ADDR_HI:
root->msi.base &= 0x00000000FFFFFFFFULL;
root->msi.base |= (uint64_t)val << 32;
+ designware_pcie_root_update_msi_mapping(root);
break;
case DESIGNWARE_PCIE_MSI_INTR0_ENABLE:
--
2.20.1
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [Qemu-devel] [PATCH 5/5] i.mx7d: pci: Update PCI IRQ mapping to match HW
@ 2019-04-16 1:39 ` Andrey Smirnov
0 siblings, 0 replies; 21+ messages in thread
From: Andrey Smirnov @ 2019-04-16 1:39 UTC (permalink / raw)
To: qemu-arm; +Cc: Andrey Smirnov, Peter Maydell, Michael S . Tsirkin, qemu-devel
Datasheet for i.MX7 is incorrect and i.MX7's PCI IRQ mapping matches
that of i.MX6:
* INTD/MSI 122
* INTC 123
* INTB 124
* INTA 125
Fix all of the relevant code to reflect that fact. Needed by latest
Linux kernels.
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Cc: Peter Maydell <peter.maydell@linaro.org>
Cc: Michael S. Tsirkin <mst@redhat.com>
Cc: qemu-devel@nongnu.org
Cc: qemu-arm@nongnu.org
---
include/hw/arm/fsl-imx7.h | 8 ++++----
hw/pci-host/designware.c | 6 ++++--
2 files changed, 8 insertions(+), 6 deletions(-)
diff --git a/include/hw/arm/fsl-imx7.h b/include/hw/arm/fsl-imx7.h
index 3efa697adc..9750003a4f 100644
--- a/include/hw/arm/fsl-imx7.h
+++ b/include/hw/arm/fsl-imx7.h
@@ -213,10 +213,10 @@ enum FslIMX7IRQs {
FSL_IMX7_USB2_IRQ = 42,
FSL_IMX7_USB3_IRQ = 40,
- FSL_IMX7_PCI_INTA_IRQ = 122,
- FSL_IMX7_PCI_INTB_IRQ = 123,
- FSL_IMX7_PCI_INTC_IRQ = 124,
- FSL_IMX7_PCI_INTD_IRQ = 125,
+ FSL_IMX7_PCI_INTA_IRQ = 125,
+ FSL_IMX7_PCI_INTB_IRQ = 124,
+ FSL_IMX7_PCI_INTC_IRQ = 123,
+ FSL_IMX7_PCI_INTD_IRQ = 122,
FSL_IMX7_UART7_IRQ = 126,
diff --git a/hw/pci-host/designware.c b/hw/pci-host/designware.c
index e80facc4a0..f4c58b25c1 100644
--- a/hw/pci-host/designware.c
+++ b/hw/pci-host/designware.c
@@ -50,6 +50,8 @@
#define DESIGNWARE_PCIE_ATU_DEVFN(x) (((x) >> 16) & 0xff)
#define DESIGNWARE_PCIE_ATU_UPPER_TARGET 0x91C
+#define DESIGNWARE_PCIE_IRQ_MSI 3
+
static DesignwarePCIEHost *
designware_pcie_root_to_host(DesignwarePCIERoot *root)
{
@@ -66,7 +68,7 @@ static void designware_pcie_root_msi_write(void *opaque, hwaddr addr,
root->msi.intr[0].status |= BIT(val) & root->msi.intr[0].enable;
if (root->msi.intr[0].status & ~root->msi.intr[0].mask) {
- qemu_set_irq(host->pci.irqs[0], 1);
+ qemu_set_irq(host->pci.irqs[DESIGNWARE_PCIE_IRQ_MSI], 1);
}
}
@@ -310,7 +312,7 @@ static void designware_pcie_root_config_write(PCIDevice *d, uint32_t address,
case DESIGNWARE_PCIE_MSI_INTR0_STATUS:
root->msi.intr[0].status ^= val;
if (!root->msi.intr[0].status) {
- qemu_set_irq(host->pci.irqs[0], 0);
+ qemu_set_irq(host->pci.irqs[DESIGNWARE_PCIE_IRQ_MSI], 0);
}
break;
--
2.20.1
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [Qemu-devel] [PATCH 5/5] i.mx7d: pci: Update PCI IRQ mapping to match HW
@ 2019-04-16 1:39 ` Andrey Smirnov
0 siblings, 0 replies; 21+ messages in thread
From: Andrey Smirnov @ 2019-04-16 1:39 UTC (permalink / raw)
To: qemu-arm; +Cc: Andrey Smirnov, Peter Maydell, qemu-devel, Michael S . Tsirkin
Datasheet for i.MX7 is incorrect and i.MX7's PCI IRQ mapping matches
that of i.MX6:
* INTD/MSI 122
* INTC 123
* INTB 124
* INTA 125
Fix all of the relevant code to reflect that fact. Needed by latest
Linux kernels.
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Cc: Peter Maydell <peter.maydell@linaro.org>
Cc: Michael S. Tsirkin <mst@redhat.com>
Cc: qemu-devel@nongnu.org
Cc: qemu-arm@nongnu.org
---
include/hw/arm/fsl-imx7.h | 8 ++++----
hw/pci-host/designware.c | 6 ++++--
2 files changed, 8 insertions(+), 6 deletions(-)
diff --git a/include/hw/arm/fsl-imx7.h b/include/hw/arm/fsl-imx7.h
index 3efa697adc..9750003a4f 100644
--- a/include/hw/arm/fsl-imx7.h
+++ b/include/hw/arm/fsl-imx7.h
@@ -213,10 +213,10 @@ enum FslIMX7IRQs {
FSL_IMX7_USB2_IRQ = 42,
FSL_IMX7_USB3_IRQ = 40,
- FSL_IMX7_PCI_INTA_IRQ = 122,
- FSL_IMX7_PCI_INTB_IRQ = 123,
- FSL_IMX7_PCI_INTC_IRQ = 124,
- FSL_IMX7_PCI_INTD_IRQ = 125,
+ FSL_IMX7_PCI_INTA_IRQ = 125,
+ FSL_IMX7_PCI_INTB_IRQ = 124,
+ FSL_IMX7_PCI_INTC_IRQ = 123,
+ FSL_IMX7_PCI_INTD_IRQ = 122,
FSL_IMX7_UART7_IRQ = 126,
diff --git a/hw/pci-host/designware.c b/hw/pci-host/designware.c
index e80facc4a0..f4c58b25c1 100644
--- a/hw/pci-host/designware.c
+++ b/hw/pci-host/designware.c
@@ -50,6 +50,8 @@
#define DESIGNWARE_PCIE_ATU_DEVFN(x) (((x) >> 16) & 0xff)
#define DESIGNWARE_PCIE_ATU_UPPER_TARGET 0x91C
+#define DESIGNWARE_PCIE_IRQ_MSI 3
+
static DesignwarePCIEHost *
designware_pcie_root_to_host(DesignwarePCIERoot *root)
{
@@ -66,7 +68,7 @@ static void designware_pcie_root_msi_write(void *opaque, hwaddr addr,
root->msi.intr[0].status |= BIT(val) & root->msi.intr[0].enable;
if (root->msi.intr[0].status & ~root->msi.intr[0].mask) {
- qemu_set_irq(host->pci.irqs[0], 1);
+ qemu_set_irq(host->pci.irqs[DESIGNWARE_PCIE_IRQ_MSI], 1);
}
}
@@ -310,7 +312,7 @@ static void designware_pcie_root_config_write(PCIDevice *d, uint32_t address,
case DESIGNWARE_PCIE_MSI_INTR0_STATUS:
root->msi.intr[0].status ^= val;
if (!root->msi.intr[0].status) {
- qemu_set_irq(host->pci.irqs[0], 0);
+ qemu_set_irq(host->pci.irqs[DESIGNWARE_PCIE_IRQ_MSI], 0);
}
break;
--
2.20.1
^ permalink raw reply related [flat|nested] 21+ messages in thread
* Re: [Qemu-devel] [PATCH 0/5] Various i.MX7 fixes
2019-04-16 1:38 ` Andrey Smirnov
` (5 preceding siblings ...)
(?)
@ 2019-06-18 0:27 ` Andrey Smirnov
2019-07-01 12:12 ` Peter Maydell
-1 siblings, 1 reply; 21+ messages in thread
From: Andrey Smirnov @ 2019-06-18 0:27 UTC (permalink / raw)
To: Peter Maydell, Michael S . Tsirkin; +Cc: open list:ARM, QEMU Developers
On Mon, Apr 15, 2019 at 6:39 PM Andrey Smirnov <andrew.smirnov@gmail.com> wrote:
>
> Everyone:
>
> I recently revisited my i.MX7 work and this series contains all of the
> fixes I had to make to get it to work with latest (5.1-rc1) Linux
> kernel again as well as fixes for genuine bugs that I somehow missed
> during original submission ("pci: designware" patches). Hopefully each
> patch is self-explanatory.
>
> Feedback is welcome!
>
Is there any changes necessary for this to go in?
Thanks,
Andrey Smirnov
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [Qemu-devel] [PATCH 3/5] pci: designware: Update MSI mapping unconditionally
2019-04-16 1:39 ` Andrey Smirnov
(?)
@ 2019-06-18 1:26 ` Michael S. Tsirkin
-1 siblings, 0 replies; 21+ messages in thread
From: Michael S. Tsirkin @ 2019-06-18 1:26 UTC (permalink / raw)
To: Andrey Smirnov; +Cc: Peter Maydell, qemu-arm, qemu-devel
On Mon, Apr 15, 2019 at 06:39:00PM -0700, Andrey Smirnov wrote:
> Expression to calculate update_msi_mapping in code handling writes to
> DESIGNWARE_PCIE_MSI_INTR0_ENABLE is missing an ! operator and should
> be:
>
> !!root->msi.intr[0].enable ^ !!val;
>
> so that MSI mapping is updated when enabled transitions from either
> "none" -> "any" or "any" -> "none". Since that register shouldn't be
> written to very often, change the code to update MSI mapping
> unconditionally instead of trying to fix the update_msi_mapping logic.
>
> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
> Cc: Peter Maydell <peter.maydell@linaro.org>
> Cc: Michael S. Tsirkin <mst@redhat.com>
> Cc: qemu-devel@nongnu.org
> Cc: qemu-arm@nongnu.org
Acked-by: Michael S. Tsirkin <mst@redhat.com>
> ---
> hw/pci-host/designware.c | 10 ++--------
> 1 file changed, 2 insertions(+), 8 deletions(-)
>
> diff --git a/hw/pci-host/designware.c b/hw/pci-host/designware.c
> index 29ea313798..6affe823c0 100644
> --- a/hw/pci-host/designware.c
> +++ b/hw/pci-host/designware.c
> @@ -296,16 +296,10 @@ static void designware_pcie_root_config_write(PCIDevice *d, uint32_t address,
> root->msi.base |= (uint64_t)val << 32;
> break;
>
> - case DESIGNWARE_PCIE_MSI_INTR0_ENABLE: {
> - const bool update_msi_mapping = !root->msi.intr[0].enable ^ !!val;
> -
> + case DESIGNWARE_PCIE_MSI_INTR0_ENABLE:
> root->msi.intr[0].enable = val;
> -
> - if (update_msi_mapping) {
> - designware_pcie_root_update_msi_mapping(root);
> - }
> + designware_pcie_root_update_msi_mapping(root);
> break;
> - }
>
> case DESIGNWARE_PCIE_MSI_INTR0_MASK:
> root->msi.intr[0].mask = val;
> --
> 2.20.1
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [Qemu-devel] [PATCH 4/5] pci: designware: Update MSI mapping when MSI address changes
2019-04-16 1:39 ` Andrey Smirnov
(?)
@ 2019-06-18 1:26 ` Michael S. Tsirkin
-1 siblings, 0 replies; 21+ messages in thread
From: Michael S. Tsirkin @ 2019-06-18 1:26 UTC (permalink / raw)
To: Andrey Smirnov; +Cc: Peter Maydell, qemu-arm, qemu-devel
On Mon, Apr 15, 2019 at 06:39:01PM -0700, Andrey Smirnov wrote:
> MSI mapping needs to be update when MSI address changes, so add the
> code to do so.
>
> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
> Cc: Peter Maydell <peter.maydell@linaro.org>
> Cc: Michael S. Tsirkin <mst@redhat.com>
> Cc: qemu-devel@nongnu.org
> Cc: qemu-arm@nongnu.org
Acked-by: Michael S. Tsirkin <mst@redhat.com>
> ---
> hw/pci-host/designware.c | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/hw/pci-host/designware.c b/hw/pci-host/designware.c
> index 6affe823c0..e80facc4a0 100644
> --- a/hw/pci-host/designware.c
> +++ b/hw/pci-host/designware.c
> @@ -289,11 +289,13 @@ static void designware_pcie_root_config_write(PCIDevice *d, uint32_t address,
> case DESIGNWARE_PCIE_MSI_ADDR_LO:
> root->msi.base &= 0xFFFFFFFF00000000ULL;
> root->msi.base |= val;
> + designware_pcie_root_update_msi_mapping(root);
> break;
>
> case DESIGNWARE_PCIE_MSI_ADDR_HI:
> root->msi.base &= 0x00000000FFFFFFFFULL;
> root->msi.base |= (uint64_t)val << 32;
> + designware_pcie_root_update_msi_mapping(root);
> break;
>
> case DESIGNWARE_PCIE_MSI_INTR0_ENABLE:
> --
> 2.20.1
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [Qemu-devel] [PATCH 1/5] i.mx7d: Add no-op/unimplemented APBH DMA module
2019-04-16 1:38 ` Andrey Smirnov
(?)
@ 2019-06-18 5:15 ` Philippe Mathieu-Daudé
-1 siblings, 0 replies; 21+ messages in thread
From: Philippe Mathieu-Daudé @ 2019-06-18 5:15 UTC (permalink / raw)
To: Andrey Smirnov, qemu-arm; +Cc: Peter Maydell, qemu-devel, Michael S . Tsirkin
On 4/16/19 3:38 AM, Andrey Smirnov wrote:
> Instantiate no-op APBH DMA module. Needed to boot latest Linux kernel.
>
> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
> Cc: Peter Maydell <peter.maydell@linaro.org>
> Cc: Michael S. Tsirkin <mst@redhat.com>
> Cc: qemu-devel@nongnu.org
> Cc: qemu-arm@nongnu.org
> ---
> include/hw/arm/fsl-imx7.h | 3 +++
> hw/arm/fsl-imx7.c | 6 ++++++
> 2 files changed, 9 insertions(+)
>
> diff --git a/include/hw/arm/fsl-imx7.h b/include/hw/arm/fsl-imx7.h
> index d848262bfd..aae4f860fc 100644
> --- a/include/hw/arm/fsl-imx7.h
> +++ b/include/hw/arm/fsl-imx7.h
> @@ -179,6 +179,9 @@ enum FslIMX7MemoryMap {
> FSL_IMX7_PCIE_REG_SIZE = 16 * 1024,
>
> FSL_IMX7_GPR_ADDR = 0x30340000,
> +
> + FSL_IMX7_DMA_APBH_ADDR = 0x33000000,
> + FSL_IMX7_DMA_APBH_SIZE = 0x2000,
0x8000?
> };
>
> enum FslIMX7IRQs {
> diff --git a/hw/arm/fsl-imx7.c b/hw/arm/fsl-imx7.c
> index 7663ad6861..1abfa5910c 100644
> --- a/hw/arm/fsl-imx7.c
> +++ b/hw/arm/fsl-imx7.c
> @@ -526,6 +526,12 @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
> */
> create_unimplemented_device("lcdif", FSL_IMX7_LCDIF_ADDR,
> FSL_IMX7_LCDIF_SIZE);
> +
> + /*
> + * DMA APBH
> + */
> + create_unimplemented_device("dma-apbh", FSL_IMX7_DMA_APBH_ADDR,
> + FSL_IMX7_DMA_APBH_SIZE);
> }
>
> static void fsl_imx7_class_init(ObjectClass *oc, void *data)
>
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [Qemu-devel] [PATCH 2/5] i.mx7d: Add no-op/unimplemented PCIE PHY IP block
2019-04-16 1:38 ` Andrey Smirnov
(?)
@ 2019-06-18 5:20 ` Philippe Mathieu-Daudé
-1 siblings, 0 replies; 21+ messages in thread
From: Philippe Mathieu-Daudé @ 2019-06-18 5:20 UTC (permalink / raw)
To: Andrey Smirnov, qemu-arm; +Cc: Peter Maydell, qemu-devel, Michael S . Tsirkin
On 4/16/19 3:38 AM, Andrey Smirnov wrote:
> Add no-op/unimplemented PCIE PHY IP block. Needed by new kernels to
> use PCIE.
>
> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
> Cc: Peter Maydell <peter.maydell@linaro.org>
> Cc: Michael S. Tsirkin <mst@redhat.com>
> Cc: qemu-devel@nongnu.org
> Cc: qemu-arm@nongnu.org
> ---
> include/hw/arm/fsl-imx7.h | 3 +++
> hw/arm/fsl-imx7.c | 5 +++++
> 2 files changed, 8 insertions(+)
>
> diff --git a/include/hw/arm/fsl-imx7.h b/include/hw/arm/fsl-imx7.h
> index aae4f860fc..3efa697adc 100644
> --- a/include/hw/arm/fsl-imx7.h
> +++ b/include/hw/arm/fsl-imx7.h
> @@ -125,6 +125,9 @@ enum FslIMX7MemoryMap {
> FSL_IMX7_ADC2_ADDR = 0x30620000,
> FSL_IMX7_ADCn_SIZE = 0x1000,
>
> + FSL_IMX7_PCIE_PHY_ADDR = 0x306D0000,
> + FSL_IMX7_PCIE_PHY_SIZE = 0x10000,
> +
> FSL_IMX7_GPC_ADDR = 0x303A0000,
>
> FSL_IMX7_I2C1_ADDR = 0x30A20000,
> diff --git a/hw/arm/fsl-imx7.c b/hw/arm/fsl-imx7.c
> index 1abfa5910c..813fb55ca9 100644
> --- a/hw/arm/fsl-imx7.c
> +++ b/hw/arm/fsl-imx7.c
> @@ -532,6 +532,11 @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
> */
> create_unimplemented_device("dma-apbh", FSL_IMX7_DMA_APBH_ADDR,
> FSL_IMX7_DMA_APBH_SIZE);
> + /*
> + * PCIe PHY
> + */
> + create_unimplemented_device("pcie-phy", FSL_IMX7_PCIE_PHY_ADDR,
> + FSL_IMX7_PCIE_PHY_SIZE);
> }
>
> static void fsl_imx7_class_init(ObjectClass *oc, void *data)
>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [Qemu-devel] [PATCH 3/5] pci: designware: Update MSI mapping unconditionally
2019-04-16 1:39 ` Andrey Smirnov
(?)
(?)
@ 2019-07-01 11:56 ` Peter Maydell
-1 siblings, 0 replies; 21+ messages in thread
From: Peter Maydell @ 2019-07-01 11:56 UTC (permalink / raw)
To: Andrey Smirnov; +Cc: qemu-arm, QEMU Developers, Michael S . Tsirkin
On Tue, 16 Apr 2019 at 02:39, Andrey Smirnov <andrew.smirnov@gmail.com> wrote:
>
> Expression to calculate update_msi_mapping in code handling writes to
> DESIGNWARE_PCIE_MSI_INTR0_ENABLE is missing an ! operator and should
> be:
>
> !!root->msi.intr[0].enable ^ !!val;
>
> so that MSI mapping is updated when enabled transitions from either
> "none" -> "any" or "any" -> "none". Since that register shouldn't be
> written to very often, change the code to update MSI mapping
> unconditionally instead of trying to fix the update_msi_mapping logic.
>
> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
> Cc: Peter Maydell <peter.maydell@linaro.org>
> Cc: Michael S. Tsirkin <mst@redhat.com>
> Cc: qemu-devel@nongnu.org
> Cc: qemu-arm@nongnu.org
> ---
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
thanks
-- PMM
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [Qemu-devel] [PATCH 4/5] pci: designware: Update MSI mapping when MSI address changes
2019-04-16 1:39 ` Andrey Smirnov
(?)
(?)
@ 2019-07-01 11:56 ` Peter Maydell
-1 siblings, 0 replies; 21+ messages in thread
From: Peter Maydell @ 2019-07-01 11:56 UTC (permalink / raw)
To: Andrey Smirnov; +Cc: qemu-arm, QEMU Developers, Michael S . Tsirkin
On Tue, 16 Apr 2019 at 02:39, Andrey Smirnov <andrew.smirnov@gmail.com> wrote:
>
> MSI mapping needs to be update when MSI address changes, so add the
> code to do so.
>
> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
> Cc: Peter Maydell <peter.maydell@linaro.org>
> Cc: Michael S. Tsirkin <mst@redhat.com>
> Cc: qemu-devel@nongnu.org
> Cc: qemu-arm@nongnu.org
> ---
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
thanks
-- PMM
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [Qemu-devel] [PATCH 5/5] i.mx7d: pci: Update PCI IRQ mapping to match HW
2019-04-16 1:39 ` Andrey Smirnov
(?)
@ 2019-07-01 12:01 ` Peter Maydell
-1 siblings, 0 replies; 21+ messages in thread
From: Peter Maydell @ 2019-07-01 12:01 UTC (permalink / raw)
To: Andrey Smirnov; +Cc: qemu-arm, QEMU Developers, Michael S . Tsirkin
On Tue, 16 Apr 2019 at 02:39, Andrey Smirnov <andrew.smirnov@gmail.com> wrote:
>
> Datasheet for i.MX7 is incorrect and i.MX7's PCI IRQ mapping matches
> that of i.MX6:
>
> * INTD/MSI 122
> * INTC 123
> * INTB 124
> * INTA 125
>
> Fix all of the relevant code to reflect that fact. Needed by latest
> Linux kernels.
>
> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
> Cc: Peter Maydell <peter.maydell@linaro.org>
> Cc: Michael S. Tsirkin <mst@redhat.com>
> Cc: qemu-devel@nongnu.org
> Cc: qemu-arm@nongnu.org
> ---
> include/hw/arm/fsl-imx7.h | 8 ++++----
> hw/pci-host/designware.c | 6 ++++--
> 2 files changed, 8 insertions(+), 6 deletions(-)
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Compare Linux kernel commit 538d6e9d597584e805146 from an
NXP employee confirming that the datasheet is incorrect
and with a report of a test against real h/w.
thanks
-- PMM
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [Qemu-devel] [PATCH 0/5] Various i.MX7 fixes
2019-06-18 0:27 ` [Qemu-devel] [PATCH 0/5] Various i.MX7 fixes Andrey Smirnov
@ 2019-07-01 12:12 ` Peter Maydell
0 siblings, 0 replies; 21+ messages in thread
From: Peter Maydell @ 2019-07-01 12:12 UTC (permalink / raw)
To: Andrey Smirnov; +Cc: open list:ARM, QEMU Developers, Michael S . Tsirkin
On Tue, 18 Jun 2019 at 01:27, Andrey Smirnov <andrew.smirnov@gmail.com> wrote:
>
> On Mon, Apr 15, 2019 at 6:39 PM Andrey Smirnov <andrew.smirnov@gmail.com> wrote:
> >
> > Everyone:
> >
> > I recently revisited my i.MX7 work and this series contains all of the
> > fixes I had to make to get it to work with latest (5.1-rc1) Linux
> > kernel again as well as fixes for genuine bugs that I somehow missed
> > during original submission ("pci: designware" patches). Hopefully each
> > patch is self-explanatory.
> >
> > Feedback is welcome!
> >
>
> Is there any changes necessary for this to go in?
Oops, sorry we missed this (for future patches you can feel free
to ping them after a couple of weeks of no response).
If you could reply to Philippe's query on patch 1 about the
correct value for FSL_IMX7_DMA_APBH_SIZE that would be great,
but since that's a very minor issue and we have softfreeze
for the next release tomorrow, I'm going to take these patches
into target-arm.next as they stand. We can fix the size value
with a followup patch if necessary.
thanks
-- PMM
^ permalink raw reply [flat|nested] 21+ messages in thread
end of thread, other threads:[~2019-07-01 12:14 UTC | newest]
Thread overview: 21+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-04-16 1:38 [Qemu-devel] [PATCH 0/5] Various i.MX7 fixes Andrey Smirnov
2019-04-16 1:38 ` Andrey Smirnov
2019-04-16 1:38 ` [Qemu-devel] [PATCH 1/5] i.mx7d: Add no-op/unimplemented APBH DMA module Andrey Smirnov
2019-04-16 1:38 ` Andrey Smirnov
2019-06-18 5:15 ` Philippe Mathieu-Daudé
2019-04-16 1:38 ` [Qemu-devel] [PATCH 2/5] i.mx7d: Add no-op/unimplemented PCIE PHY IP block Andrey Smirnov
2019-04-16 1:38 ` Andrey Smirnov
2019-06-18 5:20 ` Philippe Mathieu-Daudé
2019-04-16 1:39 ` [Qemu-devel] [PATCH 3/5] pci: designware: Update MSI mapping unconditionally Andrey Smirnov
2019-04-16 1:39 ` Andrey Smirnov
2019-06-18 1:26 ` Michael S. Tsirkin
2019-07-01 11:56 ` Peter Maydell
2019-04-16 1:39 ` [Qemu-devel] [PATCH 4/5] pci: designware: Update MSI mapping when MSI address changes Andrey Smirnov
2019-04-16 1:39 ` Andrey Smirnov
2019-06-18 1:26 ` Michael S. Tsirkin
2019-07-01 11:56 ` Peter Maydell
2019-04-16 1:39 ` [Qemu-devel] [PATCH 5/5] i.mx7d: pci: Update PCI IRQ mapping to match HW Andrey Smirnov
2019-04-16 1:39 ` Andrey Smirnov
2019-07-01 12:01 ` Peter Maydell
2019-06-18 0:27 ` [Qemu-devel] [PATCH 0/5] Various i.MX7 fixes Andrey Smirnov
2019-07-01 12:12 ` Peter Maydell
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