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From: John.C.Harrison@Intel.com
To: Intel-GFX@Lists.FreeDesktop.Org
Subject: [PATCH 3/4] drm/i915: Add whitelist workarounds for ICL
Date: Mon, 17 Jun 2019 18:01:07 -0700	[thread overview]
Message-ID: <20190618010108.27499-4-John.C.Harrison@Intel.com> (raw)
In-Reply-To: <20190618010108.27499-1-John.C.Harrison@Intel.com>

From: John Harrison <John.C.Harrison@Intel.com>

Updated whitelist table for ICL.

v2: Reduce changes to just those required for media driver until
the selftest can be updated to support the new features of the
other entries.

Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
Signed-off-by: Robert M. Fosha <robert.m.fosha@intel.com>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
---
 drivers/gpu/drm/i915/gt/intel_workarounds.c | 38 +++++++++++++++------
 1 file changed, 27 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 5308a0864e78..d37ebcddb963 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -1113,17 +1113,33 @@ static void icl_whitelist_build(struct intel_engine_cs *engine)
 {
 	struct i915_wa_list *w = &engine->whitelist;
 
-	if (engine->class != RENDER_CLASS)
-		return;
-
-	/* WaAllowUMDToModifyHalfSliceChicken7:icl */
-	whitelist_reg(w, GEN9_HALF_SLICE_CHICKEN7);
-
-	/* WaAllowUMDToModifySamplerMode:icl */
-	whitelist_reg(w, GEN10_SAMPLER_MODE);
-
-	/* WaEnableStateCacheRedirectToCS:icl */
-	whitelist_reg(w, GEN9_SLICE_COMMON_ECO_CHICKEN1);
+	switch (engine->class) {
+	case RENDER_CLASS:
+		/* WaAllowUMDToModifyHalfSliceChicken7:icl */
+		whitelist_reg(w, GEN9_HALF_SLICE_CHICKEN7);
+
+		/* WaAllowUMDToModifySamplerMode:icl */
+		whitelist_reg(w, GEN10_SAMPLER_MODE);
+
+		/* WaEnableStateCacheRedirectToCS:icl */
+		whitelist_reg(w, GEN9_SLICE_COMMON_ECO_CHICKEN1);
+		break;
+
+	case VIDEO_DECODE_CLASS:
+		/* hucStatusRegOffset */
+		whitelist_reg_ext(w, _MMIO(0x2000 + engine->mmio_base),
+				  RING_FORCE_TO_NONPRIV_RD);
+		/* hucUKernelHdrInfoRegOffset */
+		whitelist_reg_ext(w, _MMIO(0x2014 + engine->mmio_base),
+				  RING_FORCE_TO_NONPRIV_RD);
+		/* hucStatus2RegOffset */
+		whitelist_reg_ext(w, _MMIO(0x23B0 + engine->mmio_base),
+				  RING_FORCE_TO_NONPRIV_RD);
+		break;
+
+	default:
+		break;
+	}
 }
 
 void intel_engine_init_whitelist(struct intel_engine_cs *engine)
-- 
2.21.0.5.gaeb582a983

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  parent reply	other threads:[~2019-06-18  1:01 UTC|newest]

Thread overview: 25+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-06-18  1:01 [PATCH 0/4] Update whitelist support for new hardware John.C.Harrison
2019-06-18  1:01 ` [PATCH 1/4] drm/i915: Support flags in whitlist WAs John.C.Harrison
2019-06-18  6:27   ` Tvrtko Ursulin
2019-06-18  6:35   ` Tvrtko Ursulin
2019-06-18 13:48     ` John Harrison
2019-06-18 16:10   ` Tvrtko Ursulin
2019-06-18  1:01 ` [PATCH 2/4] drm/i915: Support whitelist workarounds on all engines John.C.Harrison
2019-06-18  6:29   ` Tvrtko Ursulin
2019-06-18  1:01 ` John.C.Harrison [this message]
2019-06-18  6:30   ` [PATCH 3/4] drm/i915: Add whitelist workarounds for ICL Tvrtko Ursulin
2019-06-18  1:01 ` [PATCH 4/4] drm/i915: Update workarounds selftest for read only regs John.C.Harrison
2019-06-18  6:42   ` Tvrtko Ursulin
2019-06-18 13:43     ` John Harrison
2019-06-18 16:14       ` Tvrtko Ursulin
2019-06-18  1:50 ` ✓ Fi.CI.BAT: success for Update whitelist support for new hardware (rev2) Patchwork
2019-06-18 16:33   ` Tvrtko Ursulin
2019-06-18 19:54     ` [PATCH] drm/i915: Implement read-only support in whitelist selftest John.C.Harrison
2019-06-18 20:08       ` John Harrison
2019-06-19  6:41         ` Tvrtko Ursulin
2019-06-19  6:49       ` Tvrtko Ursulin
2019-06-20 15:43       ` Tvrtko Ursulin
2019-06-25  8:33         ` Tvrtko Ursulin
2019-07-03  2:20           ` John Harrison
2019-06-18 20:51     ` ✗ Fi.CI.BAT: failure for " Patchwork
2019-06-18 16:22 ` ✓ Fi.CI.IGT: success for Update whitelist support for new hardware (rev2) Patchwork

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