From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.7 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED,USER_AGENT_NEOMUTT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 90BDDC4646B for ; Mon, 24 Jun 2019 12:43:08 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 73DCB213F2 for ; Mon, 24 Jun 2019 12:43:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727315AbfFXMnI (ORCPT ); Mon, 24 Jun 2019 08:43:08 -0400 Received: from relay8-d.mail.gandi.net ([217.70.183.201]:37979 "EHLO relay8-d.mail.gandi.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726631AbfFXMnH (ORCPT ); Mon, 24 Jun 2019 08:43:07 -0400 X-Originating-IP: 90.88.16.156 Received: from localhost (aaubervilliers-681-1-41-156.w90-88.abo.wanadoo.fr [90.88.16.156]) (Authenticated sender: maxime.ripard@bootlin.com) by relay8-d.mail.gandi.net (Postfix) with ESMTPSA id 111EC1BF206; Mon, 24 Jun 2019 12:43:01 +0000 (UTC) Date: Mon, 24 Jun 2019 14:43:01 +0200 From: Maxime Ripard To: Icenowy Zheng Cc: Rob Herring , Chen-Yu Tsai , Linus Walleij , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, linux-sunxi@googlegroups.com Subject: Re: [PATCH v3 9/9] ARM: dts: sun8i: s3: add devicetree for Lichee zero plus w/ S3 Message-ID: <20190624124301.chwhfalk5o53fm5x@flea> References: <20190623043801.14040-1-icenowy@aosc.io> <20190623043801.14040-10-icenowy@aosc.io> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="py4hwz3wgnzkb3bv" Content-Disposition: inline In-Reply-To: <20190623043801.14040-10-icenowy@aosc.io> User-Agent: NeoMutt/20180716 Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org --py4hwz3wgnzkb3bv Content-Type: text/plain; charset=us-ascii Content-Disposition: inline On Sun, Jun 23, 2019 at 12:38:01PM +0800, Icenowy Zheng wrote: > Lichee zero plus is a core board made by Sipeed, which includes on-board > TF slot or SMT SD NAND, and optional SPI NOR or eMMC, a UART debug > header, a microUSB slot and a gold finger connector for expansion. It > can use either Sochip S3 or Allwinner S3L SoC. > > Add the basic device tree for the core board, w/o optional onboard > storage, and with S3 SoC. > > Signed-off-by: Icenowy Zheng > --- > Changes in v3: > - Drop common regulator DTSI usage and added vcc3v3 regulator. > > arch/arm/boot/dts/Makefile | 1 + > .../boot/dts/sun8i-s3-lichee-zero-plus.dts | 8 ++++ > .../dts/sun8i-s3-s3l-lichee-zero-plus.dtsi | 44 +++++++++++++++++++ > 3 files changed, 53 insertions(+) > create mode 100644 arch/arm/boot/dts/sun8i-s3-lichee-zero-plus.dts > create mode 100644 arch/arm/boot/dts/sun8i-s3-s3l-lichee-zero-plus.dtsi > > diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile > index c4742afe41a7..d24dec29245e 100644 > --- a/arch/arm/boot/dts/Makefile > +++ b/arch/arm/boot/dts/Makefile > @@ -1113,6 +1113,7 @@ dtb-$(CONFIG_MACH_SUN8I) += \ > sun8i-r16-nintendo-super-nes-classic.dtb \ > sun8i-r16-parrot.dtb \ > sun8i-r40-bananapi-m2-ultra.dtb \ > + sun8i-s3-lichee-zero-plus.dtb \ > sun8i-t3-cqa3t-bv3.dtb \ > sun8i-v3s-licheepi-zero.dtb \ > sun8i-v3s-licheepi-zero-dock.dtb \ > diff --git a/arch/arm/boot/dts/sun8i-s3-lichee-zero-plus.dts b/arch/arm/boot/dts/sun8i-s3-lichee-zero-plus.dts > new file mode 100644 > index 000000000000..7d2f6b145190 > --- /dev/null > +++ b/arch/arm/boot/dts/sun8i-s3-lichee-zero-plus.dts > @@ -0,0 +1,8 @@ > +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) > +/* > + * Copyright (C) 2019 Icenowy Zheng > + */ > + > +/dts-v1/; > +#include "sun8i-s3.dtsi" > +#include "sun8i-s3-s3l-lichee-zero-plus.dtsi" > diff --git a/arch/arm/boot/dts/sun8i-s3-s3l-lichee-zero-plus.dtsi b/arch/arm/boot/dts/sun8i-s3-s3l-lichee-zero-plus.dtsi > new file mode 100644 > index 000000000000..e68f738c3046 > --- /dev/null > +++ b/arch/arm/boot/dts/sun8i-s3-s3l-lichee-zero-plus.dtsi > @@ -0,0 +1,46 @@ > +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) > +/* > + * Copyright (C) 2019 Icenowy Zheng > + */ > + > +#include > + > +/ { > + aliases { > + serial0 = &uart0; > + }; > + > + chosen { > + stdout-path = "serial0:115200n8"; > + }; > + > + reg_vcc3v3: vcc3v3 { > + compatible = "regulator-fixed"; > + regulator-name = "vcc3v3"; > + regulator-min-microvolt = <3300000>; > + regulator-max-microvolt = <3300000>; > + }; > +}; > + > +&mmc0 { > + broken-cd; > + bus-width = <4>; > + vmmc-supply = <®_vcc3v3>; > + status = "okay"; > +}; > + > +&uart0 { > + pinctrl-0 = <&uart0_pb_pins>; > + pinctrl-names = "default"; > + status = "okay"; > +}; > + > +&usb_otg { > + dr_mode = "otg"; > + status = "okay"; > +}; > + > +&usbphy { > + usb0_id_det-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; > + status = "okay"; > +}; How can it do OTG if there's no controllable VBUS regulator? Maxime -- Maxime Ripard, Bootlin Embedded Linux and Kernel engineering https://bootlin.com --py4hwz3wgnzkb3bv Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iHUEABYIAB0WIQRcEzekXsqa64kGDp7j7w1vZxhRxQUCXRDFVQAKCRDj7w1vZxhR xVyPAQC4xoOkF/OU5Ri3MaNxHNBSJU4jKHG3k6wvxxc8ao76IAD/dTJSG1W8lufw RayEbaAS6Ujh3FgQv7u22QzXoCOe9w0= =ip3c -----END PGP SIGNATURE----- --py4hwz3wgnzkb3bv-- From mboxrd@z Thu Jan 1 00:00:00 1970 From: Maxime Ripard Subject: Re: [PATCH v3 9/9] ARM: dts: sun8i: s3: add devicetree for Lichee zero plus w/ S3 Date: Mon, 24 Jun 2019 14:43:01 +0200 Message-ID: <20190624124301.chwhfalk5o53fm5x@flea> References: <20190623043801.14040-1-icenowy@aosc.io> <20190623043801.14040-10-icenowy@aosc.io> Reply-To: maxime.ripard-LDxbnhwyfcJBDgjK7y7TUQ@public.gmane.org Mime-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="py4hwz3wgnzkb3bv" Return-path: Sender: linux-sunxi-/JYPxA39Uh5TLH3MbocFFw@public.gmane.org Content-Disposition: inline In-Reply-To: <20190623043801.14040-10-icenowy-h8G6r0blFSE@public.gmane.org> List-Post: , List-Help: , List-Archive: , List-Unsubscribe: , To: Icenowy Zheng Cc: Rob Herring , Chen-Yu Tsai , Linus Walleij , devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org, linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-clk-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-gpio-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-sunxi-/JYPxA39Uh5TLH3MbocFFw@public.gmane.org List-Id: devicetree@vger.kernel.org --py4hwz3wgnzkb3bv Content-Type: text/plain; charset="UTF-8" Content-Disposition: inline On Sun, Jun 23, 2019 at 12:38:01PM +0800, Icenowy Zheng wrote: > Lichee zero plus is a core board made by Sipeed, which includes on-board > TF slot or SMT SD NAND, and optional SPI NOR or eMMC, a UART debug > header, a microUSB slot and a gold finger connector for expansion. It > can use either Sochip S3 or Allwinner S3L SoC. > > Add the basic device tree for the core board, w/o optional onboard > storage, and with S3 SoC. > > Signed-off-by: Icenowy Zheng > --- > Changes in v3: > - Drop common regulator DTSI usage and added vcc3v3 regulator. > > arch/arm/boot/dts/Makefile | 1 + > .../boot/dts/sun8i-s3-lichee-zero-plus.dts | 8 ++++ > .../dts/sun8i-s3-s3l-lichee-zero-plus.dtsi | 44 +++++++++++++++++++ > 3 files changed, 53 insertions(+) > create mode 100644 arch/arm/boot/dts/sun8i-s3-lichee-zero-plus.dts > create mode 100644 arch/arm/boot/dts/sun8i-s3-s3l-lichee-zero-plus.dtsi > > diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile > index c4742afe41a7..d24dec29245e 100644 > --- a/arch/arm/boot/dts/Makefile > +++ b/arch/arm/boot/dts/Makefile > @@ -1113,6 +1113,7 @@ dtb-$(CONFIG_MACH_SUN8I) += \ > sun8i-r16-nintendo-super-nes-classic.dtb \ > sun8i-r16-parrot.dtb \ > sun8i-r40-bananapi-m2-ultra.dtb \ > + sun8i-s3-lichee-zero-plus.dtb \ > sun8i-t3-cqa3t-bv3.dtb \ > sun8i-v3s-licheepi-zero.dtb \ > sun8i-v3s-licheepi-zero-dock.dtb \ > diff --git a/arch/arm/boot/dts/sun8i-s3-lichee-zero-plus.dts b/arch/arm/boot/dts/sun8i-s3-lichee-zero-plus.dts > new file mode 100644 > index 000000000000..7d2f6b145190 > --- /dev/null > +++ b/arch/arm/boot/dts/sun8i-s3-lichee-zero-plus.dts > @@ -0,0 +1,8 @@ > +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) > +/* > + * Copyright (C) 2019 Icenowy Zheng > + */ > + > +/dts-v1/; > +#include "sun8i-s3.dtsi" > +#include "sun8i-s3-s3l-lichee-zero-plus.dtsi" > diff --git a/arch/arm/boot/dts/sun8i-s3-s3l-lichee-zero-plus.dtsi b/arch/arm/boot/dts/sun8i-s3-s3l-lichee-zero-plus.dtsi > new file mode 100644 > index 000000000000..e68f738c3046 > --- /dev/null > +++ b/arch/arm/boot/dts/sun8i-s3-s3l-lichee-zero-plus.dtsi > @@ -0,0 +1,46 @@ > +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) > +/* > + * Copyright (C) 2019 Icenowy Zheng > + */ > + > +#include > + > +/ { > + aliases { > + serial0 = &uart0; > + }; > + > + chosen { > + stdout-path = "serial0:115200n8"; > + }; > + > + reg_vcc3v3: vcc3v3 { > + compatible = "regulator-fixed"; > + regulator-name = "vcc3v3"; > + regulator-min-microvolt = <3300000>; > + regulator-max-microvolt = <3300000>; > + }; > +}; > + > +&mmc0 { > + broken-cd; > + bus-width = <4>; > + vmmc-supply = <®_vcc3v3>; > + status = "okay"; > +}; > + > +&uart0 { > + pinctrl-0 = <&uart0_pb_pins>; > + pinctrl-names = "default"; > + status = "okay"; > +}; > + > +&usb_otg { > + dr_mode = "otg"; > + status = "okay"; > +}; > + > +&usbphy { > + usb0_id_det-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; > + status = "okay"; > +}; How can it do OTG if there's no controllable VBUS regulator? Maxime -- Maxime Ripard, Bootlin Embedded Linux and Kernel engineering https://bootlin.com --py4hwz3wgnzkb3bv-- From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.8 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_NEOMUTT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D3314C43613 for ; Mon, 24 Jun 2019 12:43:16 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 9C134213F2 for ; Mon, 24 Jun 2019 12:43:16 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="oixUHmQo" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 9C134213F2 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=bootlin.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender:Content-Type:Cc: List-Subscribe:List-Help:List-Post:List-Archive:List-Unsubscribe:List-Id: In-Reply-To:MIME-Version:References:Message-ID:Subject:To:From:Date:Reply-To: Content-Transfer-Encoding:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=9YJaRajCUOJiN42kNNxV4JLNvPmJF45W33Ei0mq0l8k=; b=oixUHmQoQNZBGV84+ygAZ9nol bZgs1+E2uvjNvduZUW6rcqREbnxnA7a3gRRDKJeXHg3ewAWYOf17KdFtEWCx8PZVIVqpIMafx2vkn 9i3un4l7yD0JySlfsOgYrOt5Dib/yEoyXIDToaUYx5FDUf5O+3H1rusleYjIyjtfeIjdmNBUm+XWw HBV//KdGkKtYRv0ijVD4EugzcPM8IB+fa4pBEzOyy/Soq7xNGj+y3C/BAuwEdl0pgILBp2os6woAK mA+K7Y/ahhDvcwIQso2fh4JQmEbYok6PP8xZkUPmotKsa0cg3SGc93fOb08qB5DWit0R+zrYpOl8X zMgeEDZPQ==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.92 #3 (Red Hat Linux)) id 1hfOJT-00020F-Pu; Mon, 24 Jun 2019 12:43:11 +0000 Received: from relay8-d.mail.gandi.net ([217.70.183.201]) by bombadil.infradead.org with esmtps (Exim 4.92 #3 (Red Hat Linux)) id 1hfOJP-0001yD-C6 for linux-arm-kernel@lists.infradead.org; Mon, 24 Jun 2019 12:43:09 +0000 X-Originating-IP: 90.88.16.156 Received: from localhost (aaubervilliers-681-1-41-156.w90-88.abo.wanadoo.fr [90.88.16.156]) (Authenticated sender: maxime.ripard@bootlin.com) by relay8-d.mail.gandi.net (Postfix) with ESMTPSA id 111EC1BF206; Mon, 24 Jun 2019 12:43:01 +0000 (UTC) Date: Mon, 24 Jun 2019 14:43:01 +0200 From: Maxime Ripard To: Icenowy Zheng Subject: Re: [PATCH v3 9/9] ARM: dts: sun8i: s3: add devicetree for Lichee zero plus w/ S3 Message-ID: <20190624124301.chwhfalk5o53fm5x@flea> References: <20190623043801.14040-1-icenowy@aosc.io> <20190623043801.14040-10-icenowy@aosc.io> MIME-Version: 1.0 In-Reply-To: <20190623043801.14040-10-icenowy@aosc.io> User-Agent: NeoMutt/20180716 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190624_054307_733434_5750162D X-CRM114-Status: GOOD ( 19.48 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Linus Walleij , linux-sunxi@googlegroups.com, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, Chen-Yu Tsai , Rob Herring , linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org Content-Type: multipart/mixed; boundary="===============4851598385938794382==" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org --===============4851598385938794382== Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="py4hwz3wgnzkb3bv" Content-Disposition: inline --py4hwz3wgnzkb3bv Content-Type: text/plain; charset=us-ascii Content-Disposition: inline On Sun, Jun 23, 2019 at 12:38:01PM +0800, Icenowy Zheng wrote: > Lichee zero plus is a core board made by Sipeed, which includes on-board > TF slot or SMT SD NAND, and optional SPI NOR or eMMC, a UART debug > header, a microUSB slot and a gold finger connector for expansion. It > can use either Sochip S3 or Allwinner S3L SoC. > > Add the basic device tree for the core board, w/o optional onboard > storage, and with S3 SoC. > > Signed-off-by: Icenowy Zheng > --- > Changes in v3: > - Drop common regulator DTSI usage and added vcc3v3 regulator. > > arch/arm/boot/dts/Makefile | 1 + > .../boot/dts/sun8i-s3-lichee-zero-plus.dts | 8 ++++ > .../dts/sun8i-s3-s3l-lichee-zero-plus.dtsi | 44 +++++++++++++++++++ > 3 files changed, 53 insertions(+) > create mode 100644 arch/arm/boot/dts/sun8i-s3-lichee-zero-plus.dts > create mode 100644 arch/arm/boot/dts/sun8i-s3-s3l-lichee-zero-plus.dtsi > > diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile > index c4742afe41a7..d24dec29245e 100644 > --- a/arch/arm/boot/dts/Makefile > +++ b/arch/arm/boot/dts/Makefile > @@ -1113,6 +1113,7 @@ dtb-$(CONFIG_MACH_SUN8I) += \ > sun8i-r16-nintendo-super-nes-classic.dtb \ > sun8i-r16-parrot.dtb \ > sun8i-r40-bananapi-m2-ultra.dtb \ > + sun8i-s3-lichee-zero-plus.dtb \ > sun8i-t3-cqa3t-bv3.dtb \ > sun8i-v3s-licheepi-zero.dtb \ > sun8i-v3s-licheepi-zero-dock.dtb \ > diff --git a/arch/arm/boot/dts/sun8i-s3-lichee-zero-plus.dts b/arch/arm/boot/dts/sun8i-s3-lichee-zero-plus.dts > new file mode 100644 > index 000000000000..7d2f6b145190 > --- /dev/null > +++ b/arch/arm/boot/dts/sun8i-s3-lichee-zero-plus.dts > @@ -0,0 +1,8 @@ > +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) > +/* > + * Copyright (C) 2019 Icenowy Zheng > + */ > + > +/dts-v1/; > +#include "sun8i-s3.dtsi" > +#include "sun8i-s3-s3l-lichee-zero-plus.dtsi" > diff --git a/arch/arm/boot/dts/sun8i-s3-s3l-lichee-zero-plus.dtsi b/arch/arm/boot/dts/sun8i-s3-s3l-lichee-zero-plus.dtsi > new file mode 100644 > index 000000000000..e68f738c3046 > --- /dev/null > +++ b/arch/arm/boot/dts/sun8i-s3-s3l-lichee-zero-plus.dtsi > @@ -0,0 +1,46 @@ > +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) > +/* > + * Copyright (C) 2019 Icenowy Zheng > + */ > + > +#include > + > +/ { > + aliases { > + serial0 = &uart0; > + }; > + > + chosen { > + stdout-path = "serial0:115200n8"; > + }; > + > + reg_vcc3v3: vcc3v3 { > + compatible = "regulator-fixed"; > + regulator-name = "vcc3v3"; > + regulator-min-microvolt = <3300000>; > + regulator-max-microvolt = <3300000>; > + }; > +}; > + > +&mmc0 { > + broken-cd; > + bus-width = <4>; > + vmmc-supply = <®_vcc3v3>; > + status = "okay"; > +}; > + > +&uart0 { > + pinctrl-0 = <&uart0_pb_pins>; > + pinctrl-names = "default"; > + status = "okay"; > +}; > + > +&usb_otg { > + dr_mode = "otg"; > + status = "okay"; > +}; > + > +&usbphy { > + usb0_id_det-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; > + status = "okay"; > +}; How can it do OTG if there's no controllable VBUS regulator? Maxime -- Maxime Ripard, Bootlin Embedded Linux and Kernel engineering https://bootlin.com --py4hwz3wgnzkb3bv Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iHUEABYIAB0WIQRcEzekXsqa64kGDp7j7w1vZxhRxQUCXRDFVQAKCRDj7w1vZxhR xVyPAQC4xoOkF/OU5Ri3MaNxHNBSJU4jKHG3k6wvxxc8ao76IAD/dTJSG1W8lufw RayEbaAS6Ujh3FgQv7u22QzXoCOe9w0= =ip3c -----END PGP SIGNATURE----- --py4hwz3wgnzkb3bv-- --===============4851598385938794382== Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Disposition: inline _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel --===============4851598385938794382==--