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From:   Jitao Shi <jitao.shi@mediatek.com>
To:     Rob Herring <robh+dt@kernel.org>, Pawel Moll <pawel.moll@arm.com>,
        Mark Rutland <mark.rutland@arm.com>,
        Ian Campbell <ijc+devicetree@hellion.org.uk>,
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        Thierry Reding <treding@nvidia.com>,
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        Inki Dae <inki.dae@samsung.com>,
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Subject: [v3 2/4] drm/panel: support for BOE tv101wum-nl6 wuxga dsi video mode panel
Date:   Wed, 26 Jun 2019 10:53:58 +0800
Message-ID: <20190626025400.109567-3-jitao.shi@mediatek.com>
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Add driver for BOE tv101wum-nl6 panel is a 10.1" 1200x1920 panel.

Signed-off-by: Jitao Shi <jitao.shi@mediatek.com>
---
 drivers/gpu/drm/panel/Kconfig                 |   9 +
 drivers/gpu/drm/panel/Makefile                |   1 +
 .../gpu/drm/panel/panel-boe-tv101wum-nl6.c    | 714 ++++++++++++++++++
 3 files changed, 724 insertions(+)
 create mode 100644 drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c

diff --git a/drivers/gpu/drm/panel/Kconfig b/drivers/gpu/drm/panel/Kconfig
index e36dbb4df867..706f6ff2b4fa 100644
--- a/drivers/gpu/drm/panel/Kconfig
+++ b/drivers/gpu/drm/panel/Kconfig
@@ -17,6 +17,15 @@ config DRM_PANEL_ARM_VERSATILE
 	  reference designs. The panel is detected using special registers
 	  in the Versatile family syscon registers.
 
+config DRM_PANEL_BOE_TV101WUM_NL6
+	tristate "BOE TV101WUM 1200x1920 panel"
+	depends on OF
+	depends on DRM_MIPI_DSI
+	depends on BACKLIGHT_CLASS_DEVICE
+	help
+	  Say Y here if you want to support for BOE TV101WUM WUXGA PANEL
+	  DSI Video Mode panel
+
 config DRM_PANEL_LVDS
 	tristate "Generic LVDS panel driver"
 	depends on OF
diff --git a/drivers/gpu/drm/panel/Makefile b/drivers/gpu/drm/panel/Makefile
index 78e3dc376bdd..8d009223c44e 100644
--- a/drivers/gpu/drm/panel/Makefile
+++ b/drivers/gpu/drm/panel/Makefile
@@ -1,5 +1,6 @@
 # SPDX-License-Identifier: GPL-2.0
 obj-$(CONFIG_DRM_PANEL_ARM_VERSATILE) += panel-arm-versatile.o
+obj-$(CONFIG_DRM_PANEL_BOE_TV101WUM_NL6) += panel-boe-tv101wum-nl6.o
 obj-$(CONFIG_DRM_PANEL_LVDS) += panel-lvds.o
 obj-$(CONFIG_DRM_PANEL_SIMPLE) += panel-simple.o
 obj-$(CONFIG_DRM_PANEL_FEIYANG_FY07024DI26A30D) += panel-feiyang-fy07024di26a30d.o
diff --git a/drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c b/drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c
new file mode 100644
index 000000000000..30d1f53dcbaf
--- /dev/null
+++ b/drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c
@@ -0,0 +1,714 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2018 MediaTek Inc.
+ * Author: Jitao Shi <jitao.shi@mediatek.com>
+ */
+
+#include <linux/backlight.h>
+#include <linux/delay.h>
+#include <linux/gpio/consumer.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/regulator/consumer.h>
+
+#include <drm/drm_crtc.h>
+#include <drm/drm_mipi_dsi.h>
+#include <drm/drm_panel.h>
+
+#include <video/mipi_display.h>
+
+struct panel_desc {
+	const struct drm_display_mode *modes;
+	unsigned int bpc;
+
+	/**
+	 * @width: width (in millimeters) of the panel's active display area
+	 * @height: height (in millimeters) of the panel's active display area
+	 */
+	struct {
+		unsigned int width;
+		unsigned int height;
+	} size;
+
+	unsigned long mode_flags;
+	enum mipi_dsi_pixel_format format;
+	const struct panel_init_cmd *init_cmds;
+	unsigned int lanes;
+};
+
+struct boe_panel {
+	struct drm_panel base;
+	struct mipi_dsi_device *dsi;
+
+	const struct panel_desc *desc;
+
+	struct backlight_device *backlight;
+	struct regulator *pp1800;
+	struct regulator *avee;
+	struct regulator *avdd;
+	struct gpio_desc *enable_gpio;
+
+	bool prepared;
+	bool enabled;
+
+	const struct drm_display_mode *mode;
+};
+
+enum dsi_cmd_type {
+	INIT_DCS_CMD,
+	DELAY_CMD,
+};
+
+struct panel_init_cmd {
+	enum dsi_cmd_type type;
+	size_t len;
+	const char *data;
+};
+
+#define _INIT_DCS_CMD(...) { \
+	.type = INIT_DCS_CMD, \
+	.len = sizeof((char[]){__VA_ARGS__}), \
+	.data = (char[]){__VA_ARGS__} }
+
+#define _INIT_DELAY_CMD(...) { \
+	.type = DELAY_CMD,\
+	.len = sizeof((char[]){__VA_ARGS__}), \
+	.data = (char[]){__VA_ARGS__} }
+
+static const struct panel_init_cmd boe_init_cmd[] = {
+	_INIT_DELAY_CMD(24),
+	_INIT_DCS_CMD(0xB0, 0x05),
+	_INIT_DCS_CMD(0xB1, 0xE5),
+	_INIT_DCS_CMD(0xB3, 0x52),
+	_INIT_DCS_CMD(0xB0, 0x00),
+	_INIT_DCS_CMD(0xB3, 0x88),
+	_INIT_DCS_CMD(0xB0, 0x04),
+	_INIT_DCS_CMD(0xB8, 0x00),
+	_INIT_DCS_CMD(0xB0, 0x00),
+	_INIT_DCS_CMD(0xB6, 0x03),
+	_INIT_DCS_CMD(0xBA, 0x8B),
+	_INIT_DCS_CMD(0xBF, 0x1A),
+	_INIT_DCS_CMD(0xC0, 0x0F),
+	_INIT_DCS_CMD(0xC2, 0x0C),
+	_INIT_DCS_CMD(0xC3, 0x02),
+	_INIT_DCS_CMD(0xC4, 0x0C),
+	_INIT_DCS_CMD(0xC5, 0x02),
+	_INIT_DCS_CMD(0xB0, 0x01),
+	_INIT_DCS_CMD(0xE0, 0x26),
+	_INIT_DCS_CMD(0xE1, 0x26),
+	_INIT_DCS_CMD(0xDC, 0x00),
+	_INIT_DCS_CMD(0xDD, 0x00),
+	_INIT_DCS_CMD(0xCC, 0x26),
+	_INIT_DCS_CMD(0xCD, 0x26),
+	_INIT_DCS_CMD(0xC8, 0x00),
+	_INIT_DCS_CMD(0xC9, 0x00),
+	_INIT_DCS_CMD(0xD2, 0x03),
+	_INIT_DCS_CMD(0xD3, 0x03),
+	_INIT_DCS_CMD(0xE6, 0x04),
+	_INIT_DCS_CMD(0xE7, 0x04),
+	_INIT_DCS_CMD(0xC4, 0x09),
+	_INIT_DCS_CMD(0xC5, 0x09),
+	_INIT_DCS_CMD(0xD8, 0x0A),
+	_INIT_DCS_CMD(0xD9, 0x0A),
+	_INIT_DCS_CMD(0xC2, 0x0B),
+	_INIT_DCS_CMD(0xC3, 0x0B),
+	_INIT_DCS_CMD(0xD6, 0x0C),
+	_INIT_DCS_CMD(0xD7, 0x0C),
+	_INIT_DCS_CMD(0xC0, 0x05),
+	_INIT_DCS_CMD(0xC1, 0x05),
+	_INIT_DCS_CMD(0xD4, 0x06),
+	_INIT_DCS_CMD(0xD5, 0x06),
+	_INIT_DCS_CMD(0xCA, 0x07),
+	_INIT_DCS_CMD(0xCB, 0x07),
+	_INIT_DCS_CMD(0xDE, 0x08),
+	_INIT_DCS_CMD(0xDF, 0x08),
+	_INIT_DCS_CMD(0xB0, 0x02),
+	_INIT_DCS_CMD(0xC0, 0x00),
+	_INIT_DCS_CMD(0xC1, 0x0D),
+	_INIT_DCS_CMD(0xC2, 0x17),
+	_INIT_DCS_CMD(0xC3, 0x26),
+	_INIT_DCS_CMD(0xC4, 0x31),
+	_INIT_DCS_CMD(0xC5, 0x1C),
+	_INIT_DCS_CMD(0xC6, 0x2C),
+	_INIT_DCS_CMD(0xC7, 0x33),
+	_INIT_DCS_CMD(0xC8, 0x31),
+	_INIT_DCS_CMD(0xC9, 0x37),
+	_INIT_DCS_CMD(0xCA, 0x37),
+	_INIT_DCS_CMD(0xCB, 0x37),
+	_INIT_DCS_CMD(0xCC, 0x39),
+	_INIT_DCS_CMD(0xCD, 0x2E),
+	_INIT_DCS_CMD(0xCE, 0x2F),
+	_INIT_DCS_CMD(0xCF, 0x2F),
+	_INIT_DCS_CMD(0xD0, 0x07),
+	_INIT_DCS_CMD(0xD2, 0x00),
+	_INIT_DCS_CMD(0xD3, 0x0D),
+	_INIT_DCS_CMD(0xD4, 0x17),
+	_INIT_DCS_CMD(0xD5, 0x26),
+	_INIT_DCS_CMD(0xD6, 0x31),
+	_INIT_DCS_CMD(0xD7, 0x3F),
+	_INIT_DCS_CMD(0xD8, 0x3F),
+	_INIT_DCS_CMD(0xD9, 0x3F),
+	_INIT_DCS_CMD(0xDA, 0x3F),
+	_INIT_DCS_CMD(0xDB, 0x37),
+	_INIT_DCS_CMD(0xDC, 0x37),
+	_INIT_DCS_CMD(0xDD, 0x37),
+	_INIT_DCS_CMD(0xDE, 0x39),
+	_INIT_DCS_CMD(0xDF, 0x2E),
+	_INIT_DCS_CMD(0xE0, 0x2F),
+	_INIT_DCS_CMD(0xE1, 0x2F),
+	_INIT_DCS_CMD(0xE2, 0x07),
+	_INIT_DCS_CMD(0xB0, 0x03),
+	_INIT_DCS_CMD(0xC8, 0x0B),
+	_INIT_DCS_CMD(0xC9, 0x07),
+	_INIT_DCS_CMD(0xC3, 0x00),
+	_INIT_DCS_CMD(0xE7, 0x00),
+	_INIT_DCS_CMD(0xC5, 0x2A),
+	_INIT_DCS_CMD(0xDE, 0x2A),
+	_INIT_DCS_CMD(0xCA, 0x43),
+	_INIT_DCS_CMD(0xC9, 0x07),
+	_INIT_DCS_CMD(0xE4, 0xC0),
+	_INIT_DCS_CMD(0xE5, 0x0D),
+	_INIT_DCS_CMD(0xCB, 0x00),
+	_INIT_DCS_CMD(0xB0, 0x06),
+	_INIT_DCS_CMD(0xB8, 0xA5),
+	_INIT_DCS_CMD(0xC0, 0xA5),
+	_INIT_DCS_CMD(0xC7, 0x0F),
+	_INIT_DCS_CMD(0xD5, 0x32),
+	_INIT_DCS_CMD(0xB8, 0x00),
+	_INIT_DCS_CMD(0xC0, 0x00),
+	_INIT_DCS_CMD(0xBC, 0x00),
+	_INIT_DCS_CMD(0xB0, 0x07),
+	_INIT_DCS_CMD(0xB1, 0x00),
+	_INIT_DCS_CMD(0xB2, 0x02),
+	_INIT_DCS_CMD(0xB3, 0x0F),
+	_INIT_DCS_CMD(0xB4, 0x25),
+	_INIT_DCS_CMD(0xB5, 0x39),
+	_INIT_DCS_CMD(0xB6, 0x4E),
+	_INIT_DCS_CMD(0xB7, 0x72),
+	_INIT_DCS_CMD(0xB8, 0x97),
+	_INIT_DCS_CMD(0xB9, 0xDC),
+	_INIT_DCS_CMD(0xBA, 0x22),
+	_INIT_DCS_CMD(0xBB, 0xA4),
+	_INIT_DCS_CMD(0xBC, 0x2B),
+	_INIT_DCS_CMD(0xBD, 0x2F),
+	_INIT_DCS_CMD(0xBE, 0xA9),
+	_INIT_DCS_CMD(0xBF, 0x25),
+	_INIT_DCS_CMD(0xC0, 0x61),
+	_INIT_DCS_CMD(0xC1, 0x97),
+	_INIT_DCS_CMD(0xC2, 0xB2),
+	_INIT_DCS_CMD(0xC3, 0xCD),
+	_INIT_DCS_CMD(0xC4, 0xD9),
+	_INIT_DCS_CMD(0xC5, 0xE7),
+	_INIT_DCS_CMD(0xC6, 0xF4),
+	_INIT_DCS_CMD(0xC7, 0xFA),
+	_INIT_DCS_CMD(0xC8, 0xFC),
+	_INIT_DCS_CMD(0xC9, 0x00),
+	_INIT_DCS_CMD(0xCA, 0x00),
+	_INIT_DCS_CMD(0xCB, 0x16),
+	_INIT_DCS_CMD(0xCC, 0xAF),
+	_INIT_DCS_CMD(0xCD, 0xFF),
+	_INIT_DCS_CMD(0xCE, 0xFF),
+	_INIT_DCS_CMD(0xB0, 0x08),
+	_INIT_DCS_CMD(0xB1, 0x04),
+	_INIT_DCS_CMD(0xB2, 0x05),
+	_INIT_DCS_CMD(0xB3, 0x11),
+	_INIT_DCS_CMD(0xB4, 0x24),
+	_INIT_DCS_CMD(0xB5, 0x39),
+	_INIT_DCS_CMD(0xB6, 0x4F),
+	_INIT_DCS_CMD(0xB7, 0x72),
+	_INIT_DCS_CMD(0xB8, 0x98),
+	_INIT_DCS_CMD(0xB9, 0xDC),
+	_INIT_DCS_CMD(0xBA, 0x23),
+	_INIT_DCS_CMD(0xBB, 0xA6),
+	_INIT_DCS_CMD(0xBC, 0x2C),
+	_INIT_DCS_CMD(0xBD, 0x30),
+	_INIT_DCS_CMD(0xBE, 0xAA),
+	_INIT_DCS_CMD(0xBF, 0x26),
+	_INIT_DCS_CMD(0xC0, 0x62),
+	_INIT_DCS_CMD(0xC1, 0x9B),
+	_INIT_DCS_CMD(0xC2, 0xB5),
+	_INIT_DCS_CMD(0xC3, 0xCF),
+	_INIT_DCS_CMD(0xC4, 0xDB),
+	_INIT_DCS_CMD(0xC5, 0xE8),
+	_INIT_DCS_CMD(0xC6, 0xF5),
+	_INIT_DCS_CMD(0xC7, 0xFA),
+	_INIT_DCS_CMD(0xC8, 0xFC),
+	_INIT_DCS_CMD(0xC9, 0x00),
+	_INIT_DCS_CMD(0xCA, 0x00),
+	_INIT_DCS_CMD(0xCB, 0x16),
+	_INIT_DCS_CMD(0xCC, 0xAF),
+	_INIT_DCS_CMD(0xCD, 0xFF),
+	_INIT_DCS_CMD(0xCE, 0xFF),
+	_INIT_DCS_CMD(0xB0, 0x09),
+	_INIT_DCS_CMD(0xB1, 0x04),
+	_INIT_DCS_CMD(0xB2, 0x02),
+	_INIT_DCS_CMD(0xB3, 0x16),
+	_INIT_DCS_CMD(0xB4, 0x24),
+	_INIT_DCS_CMD(0xB5, 0x3B),
+	_INIT_DCS_CMD(0xB6, 0x4F),
+	_INIT_DCS_CMD(0xB7, 0x73),
+	_INIT_DCS_CMD(0xB8, 0x99),
+	_INIT_DCS_CMD(0xB9, 0xE0),
+	_INIT_DCS_CMD(0xBA, 0x26),
+	_INIT_DCS_CMD(0xBB, 0xAD),
+	_INIT_DCS_CMD(0xBC, 0x36),
+	_INIT_DCS_CMD(0xBD, 0x3A),
+	_INIT_DCS_CMD(0xBE, 0xAE),
+	_INIT_DCS_CMD(0xBF, 0x2A),
+	_INIT_DCS_CMD(0xC0, 0x66),
+	_INIT_DCS_CMD(0xC1, 0x9E),
+	_INIT_DCS_CMD(0xC2, 0xB8),
+	_INIT_DCS_CMD(0xC3, 0xD1),
+	_INIT_DCS_CMD(0xC4, 0xDD),
+	_INIT_DCS_CMD(0xC5, 0xE9),
+	_INIT_DCS_CMD(0xC6, 0xF6),
+	_INIT_DCS_CMD(0xC7, 0xFA),
+	_INIT_DCS_CMD(0xC8, 0xFC),
+	_INIT_DCS_CMD(0xC9, 0x00),
+	_INIT_DCS_CMD(0xCA, 0x00),
+	_INIT_DCS_CMD(0xCB, 0x16),
+	_INIT_DCS_CMD(0xCC, 0xAF),
+	_INIT_DCS_CMD(0xCD, 0xFF),
+	_INIT_DCS_CMD(0xCE, 0xFF),
+	_INIT_DCS_CMD(0xB0, 0x0A),
+	_INIT_DCS_CMD(0xB1, 0x00),
+	_INIT_DCS_CMD(0xB2, 0x02),
+	_INIT_DCS_CMD(0xB3, 0x0F),
+	_INIT_DCS_CMD(0xB4, 0x25),
+	_INIT_DCS_CMD(0xB5, 0x39),
+	_INIT_DCS_CMD(0xB6, 0x4E),
+	_INIT_DCS_CMD(0xB7, 0x72),
+	_INIT_DCS_CMD(0xB8, 0x97),
+	_INIT_DCS_CMD(0xB9, 0xDC),
+	_INIT_DCS_CMD(0xBA, 0x22),
+	_INIT_DCS_CMD(0xBB, 0xA4),
+	_INIT_DCS_CMD(0xBC, 0x2B),
+	_INIT_DCS_CMD(0xBD, 0x2F),
+	_INIT_DCS_CMD(0xBE, 0xA9),
+	_INIT_DCS_CMD(0xBF, 0x25),
+	_INIT_DCS_CMD(0xC0, 0x61),
+	_INIT_DCS_CMD(0xC1, 0x97),
+	_INIT_DCS_CMD(0xC2, 0xB2),
+	_INIT_DCS_CMD(0xC3, 0xCD),
+	_INIT_DCS_CMD(0xC4, 0xD9),
+	_INIT_DCS_CMD(0xC5, 0xE7),
+	_INIT_DCS_CMD(0xC6, 0xF4),
+	_INIT_DCS_CMD(0xC7, 0xFA),
+	_INIT_DCS_CMD(0xC8, 0xFC),
+	_INIT_DCS_CMD(0xC9, 0x00),
+	_INIT_DCS_CMD(0xCA, 0x00),
+	_INIT_DCS_CMD(0xCB, 0x16),
+	_INIT_DCS_CMD(0xCC, 0xAF),
+	_INIT_DCS_CMD(0xCD, 0xFF),
+	_INIT_DCS_CMD(0xCE, 0xFF),
+	_INIT_DCS_CMD(0xB0, 0x0B),
+	_INIT_DCS_CMD(0xB1, 0x04),
+	_INIT_DCS_CMD(0xB2, 0x05),
+	_INIT_DCS_CMD(0xB3, 0x11),
+	_INIT_DCS_CMD(0xB4, 0x24),
+	_INIT_DCS_CMD(0xB5, 0x39),
+	_INIT_DCS_CMD(0xB6, 0x4F),
+	_INIT_DCS_CMD(0xB7, 0x72),
+	_INIT_DCS_CMD(0xB8, 0x98),
+	_INIT_DCS_CMD(0xB9, 0xDC),
+	_INIT_DCS_CMD(0xBA, 0x23),
+	_INIT_DCS_CMD(0xBB, 0xA6),
+	_INIT_DCS_CMD(0xBC, 0x2C),
+	_INIT_DCS_CMD(0xBD, 0x30),
+	_INIT_DCS_CMD(0xBE, 0xAA),
+	_INIT_DCS_CMD(0xBF, 0x26),
+	_INIT_DCS_CMD(0xC0, 0x62),
+	_INIT_DCS_CMD(0xC1, 0x9B),
+	_INIT_DCS_CMD(0xC2, 0xB5),
+	_INIT_DCS_CMD(0xC3, 0xCF),
+	_INIT_DCS_CMD(0xC4, 0xDB),
+	_INIT_DCS_CMD(0xC5, 0xE8),
+	_INIT_DCS_CMD(0xC6, 0xF5),
+	_INIT_DCS_CMD(0xC7, 0xFA),
+	_INIT_DCS_CMD(0xC8, 0xFC),
+	_INIT_DCS_CMD(0xC9, 0x00),
+	_INIT_DCS_CMD(0xCA, 0x00),
+	_INIT_DCS_CMD(0xCB, 0x16),
+	_INIT_DCS_CMD(0xCC, 0xAF),
+	_INIT_DCS_CMD(0xCD, 0xFF),
+	_INIT_DCS_CMD(0xCE, 0xFF),
+	_INIT_DCS_CMD(0xB0, 0x0C),
+	_INIT_DCS_CMD(0xB1, 0x04),
+	_INIT_DCS_CMD(0xB2, 0x02),
+	_INIT_DCS_CMD(0xB3, 0x16),
+	_INIT_DCS_CMD(0xB4, 0x24),
+	_INIT_DCS_CMD(0xB5, 0x3B),
+	_INIT_DCS_CMD(0xB6, 0x4F),
+	_INIT_DCS_CMD(0xB7, 0x73),
+	_INIT_DCS_CMD(0xB8, 0x99),
+	_INIT_DCS_CMD(0xB9, 0xE0),
+	_INIT_DCS_CMD(0xBA, 0x26),
+	_INIT_DCS_CMD(0xBB, 0xAD),
+	_INIT_DCS_CMD(0xBC, 0x36),
+	_INIT_DCS_CMD(0xBD, 0x3A),
+	_INIT_DCS_CMD(0xBE, 0xAE),
+	_INIT_DCS_CMD(0xBF, 0x2A),
+	_INIT_DCS_CMD(0xC0, 0x66),
+	_INIT_DCS_CMD(0xC1, 0x9E),
+	_INIT_DCS_CMD(0xC2, 0xB8),
+	_INIT_DCS_CMD(0xC3, 0xD1),
+	_INIT_DCS_CMD(0xC4, 0xDD),
+	_INIT_DCS_CMD(0xC5, 0xE9),
+	_INIT_DCS_CMD(0xC6, 0xF6),
+	_INIT_DCS_CMD(0xC7, 0xFA),
+	_INIT_DCS_CMD(0xC8, 0xFC),
+	_INIT_DCS_CMD(0xC9, 0x00),
+	_INIT_DCS_CMD(0xCA, 0x00),
+	_INIT_DCS_CMD(0xCB, 0x16),
+	_INIT_DCS_CMD(0xCC, 0xAF),
+	_INIT_DCS_CMD(0xCD, 0xFF),
+	_INIT_DCS_CMD(0xCE, 0xFF),
+	_INIT_DCS_CMD(0xB0, 0x00),
+	_INIT_DCS_CMD(0xB3, 0x08),
+	_INIT_DCS_CMD(0xB0, 0x04),
+	_INIT_DCS_CMD(0xB8, 0x68),
+	_INIT_DELAY_CMD(150),
+	{},
+};
+
+static inline struct boe_panel *to_boe_panel(struct drm_panel *panel)
+{
+	return container_of(panel, struct boe_panel, base);
+}
+
+static int boe_panel_init(struct boe_panel *boe)
+{
+	struct mipi_dsi_device *dsi = boe->dsi;
+	struct drm_panel *panel = &boe->base;
+	int err, i;
+
+	if (boe->desc->init_cmds) {
+		const struct panel_init_cmd *init_cmds = boe->desc->init_cmds;
+
+		for (i = 0; init_cmds[i].len != 0; i++) {
+			const struct panel_init_cmd *cmd = &init_cmds[i];
+
+			switch (cmd->type) {
+			case DELAY_CMD:
+				msleep(cmd->data[0]);
+				err = 0;
+				break;
+
+			case INIT_DCS_CMD:
+				err = mipi_dsi_dcs_write(dsi, cmd->data[0],
+							 cmd->len <= 1 ? NULL :
+							 &cmd->data[1],
+							 cmd->len - 1);
+				break;
+			}
+
+			if (err < 0) {
+				dev_err(panel->dev,
+					"failed to write command %u\n", i);
+				return err;
+			}
+		}
+	}
+	return 0;
+}
+
+static int boe_panel_off(struct boe_panel *boe)
+{
+	struct mipi_dsi_device *dsi = boe->dsi;
+	int ret;
+
+	dsi->mode_flags &= ~MIPI_DSI_MODE_LPM;
+
+	ret = mipi_dsi_dcs_enter_sleep_mode(dsi);
+	if (ret < 0)
+		return ret;
+
+	return 0;
+}
+
+static int boe_panel_disable(struct drm_panel *panel)
+{
+	struct boe_panel *boe = to_boe_panel(panel);
+
+	if (!boe->enabled)
+		return 0;
+
+	backlight_disable(boe->backlight);
+
+	boe->enabled = false;
+
+	return 0;
+}
+
+static int boe_panel_unprepare(struct drm_panel *panel)
+{
+	struct boe_panel *boe = to_boe_panel(panel);
+	int ret;
+
+	if (!boe->prepared)
+		return 0;
+
+	ret = boe_panel_off(boe);
+	if (ret < 0) {
+		dev_err(panel->dev, "failed to set panel off: %d\n", ret);
+		return ret;
+	}
+
+	msleep(150);
+	if (boe->enable_gpio)
+		gpiod_set_value(boe->enable_gpio, 0);
+	usleep_range(500, 1000);
+	regulator_disable(boe->avee);
+	regulator_disable(boe->avdd);
+	usleep_range(5000, 7000);
+	regulator_disable(boe->pp1800);
+
+	boe->prepared = false;
+
+	return 0;
+}
+
+static int boe_panel_prepare(struct drm_panel *panel)
+{
+	struct boe_panel *boe = to_boe_panel(panel);
+	int ret;
+
+	if (boe->prepared)
+		return 0;
+
+	if (boe->enable_gpio) {
+		gpiod_set_value(boe->enable_gpio, 0);
+		usleep_range(1000, 1500);
+	}
+
+	ret = regulator_enable(boe->pp1800);
+	if (ret < 0)
+		return ret;
+
+	usleep_range(3000, 5000);
+
+	ret = regulator_enable(boe->avdd);
+	if (ret < 0)
+		goto poweroff1v8;
+	ret = regulator_enable(boe->avee);
+	if (ret < 0)
+		goto poweroffavdd;
+
+	msleep(100);
+
+	if (boe->enable_gpio) {
+		gpiod_set_value(boe->enable_gpio, 1);
+		usleep_range(10000, 12000);
+	}
+
+	ret = boe_panel_init(boe);
+	if (ret < 0) {
+		dev_err(panel->dev, "failed to init panel: %d\n", ret);
+		goto poweroff;
+	}
+
+	boe->prepared = true;
+
+	return 0;
+
+poweroff:
+	regulator_disable(boe->avee);
+poweroffavdd:
+	regulator_disable(boe->avdd);
+poweroff1v8:
+	usleep_range(5000, 7000);
+	regulator_disable(boe->pp1800);
+	if (boe->enable_gpio)
+		gpiod_set_value(boe->enable_gpio, 0);
+	return ret;
+}
+
+static int boe_panel_enable(struct drm_panel *panel)
+{
+	struct boe_panel *boe = to_boe_panel(panel);
+	int ret;
+
+	if (boe->enabled)
+		return 0;
+
+	ret = backlight_enable(boe->backlight);
+	if (ret) {
+		dev_err(panel->dev, "Failed to enable backlight %d\n",
+			ret);
+		return ret;
+	}
+
+	boe->enabled = true;
+
+	return 0;
+}
+
+static const struct drm_display_mode boe_default_mode = {
+	.clock = 159425,
+	.hdisplay = 1200,
+	.hsync_start = 1200 + 100,
+	.hsync_end = 1200 + 100 + 40,
+	.htotal = 1200 + 100 + 40 + 24,
+	.vdisplay = 1920,
+	.vsync_start = 1920 + 10,
+	.vsync_end = 1920 + 10 + 14,
+	.vtotal = 1920 + 10 + 14 + 4,
+	.vrefresh = 60,
+};
+
+static const struct panel_desc boe_tv101wum_nl6_desc = {
+	.modes = &boe_default_mode,
+	.bpc = 8,
+	.size = {
+		.width = 135,
+		.height = 216,
+	},
+	.lanes = 4,
+	.format = MIPI_DSI_FMT_RGB888,
+	.mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
+		      MIPI_DSI_MODE_LPM,
+	.init_cmds = boe_init_cmd,
+};
+
+static int boe_panel_get_modes(struct drm_panel *panel)
+{
+	struct boe_panel *boe = to_boe_panel(panel);
+	const struct drm_display_mode *m = boe->desc->modes;
+	struct drm_display_mode *mode;
+
+	mode = drm_mode_duplicate(panel->drm, m);
+	if (!mode) {
+		dev_err(panel->dev, "failed to add mode %ux%u@%u\n",
+			m->hdisplay, m->vdisplay, m->vrefresh);
+		return -ENOMEM;
+	}
+
+	mode->type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED;
+	drm_mode_set_name(mode);
+	drm_mode_probed_add(panel->connector, mode);
+
+	panel->connector->display_info.width_mm = boe->desc->size.width;
+	panel->connector->display_info.height_mm = boe->desc->size.height;
+	panel->connector->display_info.bpc = boe->desc->bpc;
+
+	return 1;
+}
+
+static const struct drm_panel_funcs boe_panel_funcs = {
+	.disable = boe_panel_disable,
+	.unprepare = boe_panel_unprepare,
+	.prepare = boe_panel_prepare,
+	.enable = boe_panel_enable,
+	.get_modes = boe_panel_get_modes,
+};
+
+static int boe_panel_add(struct boe_panel *boe)
+{
+	struct device *dev = &boe->dsi->dev;
+
+	boe->avdd = devm_regulator_get(dev, "avdd");
+	if (IS_ERR(boe->avdd))
+		return PTR_ERR(boe->avdd);
+
+	boe->avee = devm_regulator_get(dev, "avee");
+	if (IS_ERR(boe->avee))
+		return PTR_ERR(boe->avee);
+
+	boe->pp1800 = devm_regulator_get(dev, "pp1800");
+	if (IS_ERR(boe->pp1800))
+		return PTR_ERR(boe->pp1800);
+
+	boe->enable_gpio = devm_gpiod_get(dev, "enable", GPIOD_OUT_LOW);
+	if (IS_ERR(boe->enable_gpio)) {
+		dev_err(dev, "cannot get reset-gpios %ld\n",
+			PTR_ERR(boe->enable_gpio));
+		return PTR_ERR(boe->enable_gpio);
+	}
+
+	gpiod_set_value(boe->enable_gpio, 0);
+
+	boe->backlight = devm_of_find_backlight(dev);
+	if (IS_ERR(boe->backlight))
+		return PTR_ERR(boe->backlight);
+
+	drm_panel_init(&boe->base);
+	boe->base.funcs = &boe_panel_funcs;
+	boe->base.dev = &boe->dsi->dev;
+
+	return drm_panel_add(&boe->base);
+}
+
+static int boe_panel_probe(struct mipi_dsi_device *dsi)
+{
+	struct boe_panel *boe;
+	int ret;
+	const struct panel_desc *desc;
+
+	boe = devm_kzalloc(&dsi->dev, sizeof(*boe), GFP_KERNEL);
+	if (!boe)
+		return -ENOMEM;
+
+	desc = of_device_get_match_data(&dsi->dev);
+	dsi->lanes = desc->lanes;
+	dsi->format = desc->format;
+	dsi->mode_flags = desc->mode_flags;
+	boe->desc = desc;
+	boe->dsi = dsi;
+	ret = boe_panel_add(boe);
+	if (ret < 0)
+		return ret;
+
+	mipi_dsi_set_drvdata(dsi, boe);
+
+	return mipi_dsi_attach(dsi);
+}
+
+static int boe_panel_remove(struct mipi_dsi_device *dsi)
+{
+	struct boe_panel *boe = mipi_dsi_get_drvdata(dsi);
+	int ret;
+
+	ret = boe_panel_disable(&boe->base);
+	if (ret < 0)
+		dev_err(&dsi->dev, "failed to disable panel: %d\n", ret);
+
+	ret = mipi_dsi_detach(dsi);
+	if (ret < 0)
+		dev_err(&dsi->dev, "failed to detach from DSI host: %d\n", ret);
+
+	if (boe->base.dev)
+		drm_panel_remove(&boe->base);
+
+	return 0;
+}
+
+static void boe_panel_shutdown(struct mipi_dsi_device *dsi)
+{
+	struct boe_panel *boe = mipi_dsi_get_drvdata(dsi);
+
+	boe_panel_disable(&boe->base);
+}
+
+static const struct of_device_id boe_of_match[] = {
+	{ .compatible = "boe,tv101wum-nl6",
+	  .data = &boe_tv101wum_nl6_desc
+	},
+	{ /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, boe_of_match);
+
+static struct mipi_dsi_driver boe_panel_driver = {
+	.driver = {
+		.name = "panel-boe-tv101wum-nl6",
+		.of_match_table = boe_of_match,
+	},
+	.probe = boe_panel_probe,
+	.remove = boe_panel_remove,
+	.shutdown = boe_panel_shutdown,
+};
+module_mipi_dsi_driver(boe_panel_driver);
+
+MODULE_AUTHOR("Jitao Shi <jitao.shi@mediatek.com>");
+MODULE_DESCRIPTION("BOE tv101wum-nl6 1200x1920 video mode panel driver");
+MODULE_LICENSE("GPL v2");
-- 
2.21.0


From mboxrd@z Thu Jan  1 00:00:00 1970
From: Jitao Shi <jitao.shi@mediatek.com>
Subject: [v3 2/4] drm/panel: support for BOE tv101wum-nl6 wuxga dsi video mode
 panel
Date: Wed, 26 Jun 2019 10:53:58 +0800
Message-ID: <20190626025400.109567-3-jitao.shi@mediatek.com>
References: <20190626025400.109567-1-jitao.shi@mediatek.com>
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To: Rob Herring <robh+dt@kernel.org>, Pawel Moll <pawel.moll@arm.com>, Mark Rutland <mark.rutland@arm.com>, Ian Campbell <ijc+devicetree@hellion.org.uk>, linux-pwm@vger.kernel.org, David Airlie <airlied@linux.ie>, Matthias Brugger <matthias.bgg@gmail.com>
Cc: stonea168@163.com, dri-devel@lists.freedesktop.org, Andy Yan <andy.yan@rock-chips.com>, Ajay Kumar <ajaykumar.rs@samsung.com>, Vincent Palatin <vpalatin@chromium.org>, cawa.cheng@mediatek.com, Russell King <rmk+kernel@arm.linux.org.uk>, Thierry Reding <treding@nvidia.com>, devicetree@vger.kernel.org, Jitao Shi <jitao.shi@mediatek.com>, linux-mediatek@lists.infradead.org, yingjoe.chen@mediatek.com, eddie.huang@mediatek.com, linux-arm-kernel@lists.infradead.org, Rahul Sharma <rahul.sharma@samsung.com>, srv_heupstream@mediatek.com, linux-kernel@vger.kernel.org, Sascha Hauer <kernel@pengutronix.de>, Sean Paul <seanpaul@chromium.org>
List-Id: devicetree@vger.kernel.org

QWRkIGRyaXZlciBmb3IgQk9FIHR2MTAxd3VtLW5sNiBwYW5lbCBpcyBhIDEwLjEiIDEyMDB4MTky
MCBwYW5lbC4KClNpZ25lZC1vZmYtYnk6IEppdGFvIFNoaSA8aml0YW8uc2hpQG1lZGlhdGVrLmNv
bT4KLS0tCiBkcml2ZXJzL2dwdS9kcm0vcGFuZWwvS2NvbmZpZyAgICAgICAgICAgICAgICAgfCAg
IDkgKwogZHJpdmVycy9ncHUvZHJtL3BhbmVsL01ha2VmaWxlICAgICAgICAgICAgICAgIHwgICAx
ICsKIC4uLi9ncHUvZHJtL3BhbmVsL3BhbmVsLWJvZS10djEwMXd1bS1ubDYuYyAgICB8IDcxNCAr
KysrKysrKysrKysrKysrKysKIDMgZmlsZXMgY2hhbmdlZCwgNzI0IGluc2VydGlvbnMoKykKIGNy
ZWF0ZSBtb2RlIDEwMDY0NCBkcml2ZXJzL2dwdS9kcm0vcGFuZWwvcGFuZWwtYm9lLXR2MTAxd3Vt
LW5sNi5jCgpkaWZmIC0tZ2l0IGEvZHJpdmVycy9ncHUvZHJtL3BhbmVsL0tjb25maWcgYi9kcml2
ZXJzL2dwdS9kcm0vcGFuZWwvS2NvbmZpZwppbmRleCBlMzZkYmI0ZGY4NjcuLjcwNmY2ZmYyYjRm
YSAxMDA2NDQKLS0tIGEvZHJpdmVycy9ncHUvZHJtL3BhbmVsL0tjb25maWcKKysrIGIvZHJpdmVy
cy9ncHUvZHJtL3BhbmVsL0tjb25maWcKQEAgLTE3LDYgKzE3LDE1IEBAIGNvbmZpZyBEUk1fUEFO
RUxfQVJNX1ZFUlNBVElMRQogCSAgcmVmZXJlbmNlIGRlc2lnbnMuIFRoZSBwYW5lbCBpcyBkZXRl
Y3RlZCB1c2luZyBzcGVjaWFsIHJlZ2lzdGVycwogCSAgaW4gdGhlIFZlcnNhdGlsZSBmYW1pbHkg
c3lzY29uIHJlZ2lzdGVycy4KIAorY29uZmlnIERSTV9QQU5FTF9CT0VfVFYxMDFXVU1fTkw2CisJ
dHJpc3RhdGUgIkJPRSBUVjEwMVdVTSAxMjAweDE5MjAgcGFuZWwiCisJZGVwZW5kcyBvbiBPRgor
CWRlcGVuZHMgb24gRFJNX01JUElfRFNJCisJZGVwZW5kcyBvbiBCQUNLTElHSFRfQ0xBU1NfREVW
SUNFCisJaGVscAorCSAgU2F5IFkgaGVyZSBpZiB5b3Ugd2FudCB0byBzdXBwb3J0IGZvciBCT0Ug
VFYxMDFXVU0gV1VYR0EgUEFORUwKKwkgIERTSSBWaWRlbyBNb2RlIHBhbmVsCisKIGNvbmZpZyBE
Uk1fUEFORUxfTFZEUwogCXRyaXN0YXRlICJHZW5lcmljIExWRFMgcGFuZWwgZHJpdmVyIgogCWRl
cGVuZHMgb24gT0YKZGlmZiAtLWdpdCBhL2RyaXZlcnMvZ3B1L2RybS9wYW5lbC9NYWtlZmlsZSBi
L2RyaXZlcnMvZ3B1L2RybS9wYW5lbC9NYWtlZmlsZQppbmRleCA3OGUzZGMzNzZiZGQuLjhkMDA5
MjIzYzQ0ZSAxMDA2NDQKLS0tIGEvZHJpdmVycy9ncHUvZHJtL3BhbmVsL01ha2VmaWxlCisrKyBi
L2RyaXZlcnMvZ3B1L2RybS9wYW5lbC9NYWtlZmlsZQpAQCAtMSw1ICsxLDYgQEAKICMgU1BEWC1M
aWNlbnNlLUlkZW50aWZpZXI6IEdQTC0yLjAKIG9iai0kKENPTkZJR19EUk1fUEFORUxfQVJNX1ZF
UlNBVElMRSkgKz0gcGFuZWwtYXJtLXZlcnNhdGlsZS5vCitvYmotJChDT05GSUdfRFJNX1BBTkVM
X0JPRV9UVjEwMVdVTV9OTDYpICs9IHBhbmVsLWJvZS10djEwMXd1bS1ubDYubwogb2JqLSQoQ09O
RklHX0RSTV9QQU5FTF9MVkRTKSArPSBwYW5lbC1sdmRzLm8KIG9iai0kKENPTkZJR19EUk1fUEFO
RUxfU0lNUExFKSArPSBwYW5lbC1zaW1wbGUubwogb2JqLSQoQ09ORklHX0RSTV9QQU5FTF9GRUlZ
QU5HX0ZZMDcwMjRESTI2QTMwRCkgKz0gcGFuZWwtZmVpeWFuZy1meTA3MDI0ZGkyNmEzMGQubwpk
aWZmIC0tZ2l0IGEvZHJpdmVycy9ncHUvZHJtL3BhbmVsL3BhbmVsLWJvZS10djEwMXd1bS1ubDYu
YyBiL2RyaXZlcnMvZ3B1L2RybS9wYW5lbC9wYW5lbC1ib2UtdHYxMDF3dW0tbmw2LmMKbmV3IGZp
bGUgbW9kZSAxMDA2NDQKaW5kZXggMDAwMDAwMDAwMDAwLi4zMGQxZjUzZGNiYWYKLS0tIC9kZXYv
bnVsbAorKysgYi9kcml2ZXJzL2dwdS9kcm0vcGFuZWwvcGFuZWwtYm9lLXR2MTAxd3VtLW5sNi5j
CkBAIC0wLDAgKzEsNzE0IEBACisvLyBTUERYLUxpY2Vuc2UtSWRlbnRpZmllcjogR1BMLTIuMAor
LyoKKyAqIENvcHlyaWdodCAoYykgMjAxOCBNZWRpYVRlayBJbmMuCisgKiBBdXRob3I6IEppdGFv
IFNoaSA8aml0YW8uc2hpQG1lZGlhdGVrLmNvbT4KKyAqLworCisjaW5jbHVkZSA8bGludXgvYmFj
a2xpZ2h0Lmg+CisjaW5jbHVkZSA8bGludXgvZGVsYXkuaD4KKyNpbmNsdWRlIDxsaW51eC9ncGlv
L2NvbnN1bWVyLmg+CisjaW5jbHVkZSA8bGludXgvbW9kdWxlLmg+CisjaW5jbHVkZSA8bGludXgv
b2YuaD4KKyNpbmNsdWRlIDxsaW51eC9vZl9kZXZpY2UuaD4KKyNpbmNsdWRlIDxsaW51eC9yZWd1
bGF0b3IvY29uc3VtZXIuaD4KKworI2luY2x1ZGUgPGRybS9kcm1fY3J0Yy5oPgorI2luY2x1ZGUg
PGRybS9kcm1fbWlwaV9kc2kuaD4KKyNpbmNsdWRlIDxkcm0vZHJtX3BhbmVsLmg+CisKKyNpbmNs
dWRlIDx2aWRlby9taXBpX2Rpc3BsYXkuaD4KKworc3RydWN0IHBhbmVsX2Rlc2MgeworCWNvbnN0
IHN0cnVjdCBkcm1fZGlzcGxheV9tb2RlICptb2RlczsKKwl1bnNpZ25lZCBpbnQgYnBjOworCisJ
LyoqCisJICogQHdpZHRoOiB3aWR0aCAoaW4gbWlsbGltZXRlcnMpIG9mIHRoZSBwYW5lbCdzIGFj
dGl2ZSBkaXNwbGF5IGFyZWEKKwkgKiBAaGVpZ2h0OiBoZWlnaHQgKGluIG1pbGxpbWV0ZXJzKSBv
ZiB0aGUgcGFuZWwncyBhY3RpdmUgZGlzcGxheSBhcmVhCisJICovCisJc3RydWN0IHsKKwkJdW5z
aWduZWQgaW50IHdpZHRoOworCQl1bnNpZ25lZCBpbnQgaGVpZ2h0OworCX0gc2l6ZTsKKworCXVu
c2lnbmVkIGxvbmcgbW9kZV9mbGFnczsKKwllbnVtIG1pcGlfZHNpX3BpeGVsX2Zvcm1hdCBmb3Jt
YXQ7CisJY29uc3Qgc3RydWN0IHBhbmVsX2luaXRfY21kICppbml0X2NtZHM7CisJdW5zaWduZWQg
aW50IGxhbmVzOworfTsKKworc3RydWN0IGJvZV9wYW5lbCB7CisJc3RydWN0IGRybV9wYW5lbCBi
YXNlOworCXN0cnVjdCBtaXBpX2RzaV9kZXZpY2UgKmRzaTsKKworCWNvbnN0IHN0cnVjdCBwYW5l
bF9kZXNjICpkZXNjOworCisJc3RydWN0IGJhY2tsaWdodF9kZXZpY2UgKmJhY2tsaWdodDsKKwlz
dHJ1Y3QgcmVndWxhdG9yICpwcDE4MDA7CisJc3RydWN0IHJlZ3VsYXRvciAqYXZlZTsKKwlzdHJ1
Y3QgcmVndWxhdG9yICphdmRkOworCXN0cnVjdCBncGlvX2Rlc2MgKmVuYWJsZV9ncGlvOworCisJ
Ym9vbCBwcmVwYXJlZDsKKwlib29sIGVuYWJsZWQ7CisKKwljb25zdCBzdHJ1Y3QgZHJtX2Rpc3Bs
YXlfbW9kZSAqbW9kZTsKK307CisKK2VudW0gZHNpX2NtZF90eXBlIHsKKwlJTklUX0RDU19DTUQs
CisJREVMQVlfQ01ELAorfTsKKworc3RydWN0IHBhbmVsX2luaXRfY21kIHsKKwllbnVtIGRzaV9j
bWRfdHlwZSB0eXBlOworCXNpemVfdCBsZW47CisJY29uc3QgY2hhciAqZGF0YTsKK307CisKKyNk
ZWZpbmUgX0lOSVRfRENTX0NNRCguLi4pIHsgXAorCS50eXBlID0gSU5JVF9EQ1NfQ01ELCBcCisJ
LmxlbiA9IHNpemVvZigoY2hhcltdKXtfX1ZBX0FSR1NfX30pLCBcCisJLmRhdGEgPSAoY2hhcltd
KXtfX1ZBX0FSR1NfX30gfQorCisjZGVmaW5lIF9JTklUX0RFTEFZX0NNRCguLi4pIHsgXAorCS50
eXBlID0gREVMQVlfQ01ELFwKKwkubGVuID0gc2l6ZW9mKChjaGFyW10pe19fVkFfQVJHU19ffSks
IFwKKwkuZGF0YSA9IChjaGFyW10pe19fVkFfQVJHU19ffSB9CisKK3N0YXRpYyBjb25zdCBzdHJ1
Y3QgcGFuZWxfaW5pdF9jbWQgYm9lX2luaXRfY21kW10gPSB7CisJX0lOSVRfREVMQVlfQ01EKDI0
KSwKKwlfSU5JVF9EQ1NfQ01EKDB4QjAsIDB4MDUpLAorCV9JTklUX0RDU19DTUQoMHhCMSwgMHhF
NSksCisJX0lOSVRfRENTX0NNRCgweEIzLCAweDUyKSwKKwlfSU5JVF9EQ1NfQ01EKDB4QjAsIDB4
MDApLAorCV9JTklUX0RDU19DTUQoMHhCMywgMHg4OCksCisJX0lOSVRfRENTX0NNRCgweEIwLCAw
eDA0KSwKKwlfSU5JVF9EQ1NfQ01EKDB4QjgsIDB4MDApLAorCV9JTklUX0RDU19DTUQoMHhCMCwg
MHgwMCksCisJX0lOSVRfRENTX0NNRCgweEI2LCAweDAzKSwKKwlfSU5JVF9EQ1NfQ01EKDB4QkEs
IDB4OEIpLAorCV9JTklUX0RDU19DTUQoMHhCRiwgMHgxQSksCisJX0lOSVRfRENTX0NNRCgweEMw
LCAweDBGKSwKKwlfSU5JVF9EQ1NfQ01EKDB4QzIsIDB4MEMpLAorCV9JTklUX0RDU19DTUQoMHhD
MywgMHgwMiksCisJX0lOSVRfRENTX0NNRCgweEM0LCAweDBDKSwKKwlfSU5JVF9EQ1NfQ01EKDB4
QzUsIDB4MDIpLAorCV9JTklUX0RDU19DTUQoMHhCMCwgMHgwMSksCisJX0lOSVRfRENTX0NNRCgw
eEUwLCAweDI2KSwKKwlfSU5JVF9EQ1NfQ01EKDB4RTEsIDB4MjYpLAorCV9JTklUX0RDU19DTUQo
MHhEQywgMHgwMCksCisJX0lOSVRfRENTX0NNRCgweERELCAweDAwKSwKKwlfSU5JVF9EQ1NfQ01E
KDB4Q0MsIDB4MjYpLAorCV9JTklUX0RDU19DTUQoMHhDRCwgMHgyNiksCisJX0lOSVRfRENTX0NN
RCgweEM4LCAweDAwKSwKKwlfSU5JVF9EQ1NfQ01EKDB4QzksIDB4MDApLAorCV9JTklUX0RDU19D
TUQoMHhEMiwgMHgwMyksCisJX0lOSVRfRENTX0NNRCgweEQzLCAweDAzKSwKKwlfSU5JVF9EQ1Nf
Q01EKDB4RTYsIDB4MDQpLAorCV9JTklUX0RDU19DTUQoMHhFNywgMHgwNCksCisJX0lOSVRfRENT
X0NNRCgweEM0LCAweDA5KSwKKwlfSU5JVF9EQ1NfQ01EKDB4QzUsIDB4MDkpLAorCV9JTklUX0RD
U19DTUQoMHhEOCwgMHgwQSksCisJX0lOSVRfRENTX0NNRCgweEQ5LCAweDBBKSwKKwlfSU5JVF9E
Q1NfQ01EKDB4QzIsIDB4MEIpLAorCV9JTklUX0RDU19DTUQoMHhDMywgMHgwQiksCisJX0lOSVRf
RENTX0NNRCgweEQ2LCAweDBDKSwKKwlfSU5JVF9EQ1NfQ01EKDB4RDcsIDB4MEMpLAorCV9JTklU
X0RDU19DTUQoMHhDMCwgMHgwNSksCisJX0lOSVRfRENTX0NNRCgweEMxLCAweDA1KSwKKwlfSU5J
VF9EQ1NfQ01EKDB4RDQsIDB4MDYpLAorCV9JTklUX0RDU19DTUQoMHhENSwgMHgwNiksCisJX0lO
SVRfRENTX0NNRCgweENBLCAweDA3KSwKKwlfSU5JVF9EQ1NfQ01EKDB4Q0IsIDB4MDcpLAorCV9J
TklUX0RDU19DTUQoMHhERSwgMHgwOCksCisJX0lOSVRfRENTX0NNRCgweERGLCAweDA4KSwKKwlf
SU5JVF9EQ1NfQ01EKDB4QjAsIDB4MDIpLAorCV9JTklUX0RDU19DTUQoMHhDMCwgMHgwMCksCisJ
X0lOSVRfRENTX0NNRCgweEMxLCAweDBEKSwKKwlfSU5JVF9EQ1NfQ01EKDB4QzIsIDB4MTcpLAor
CV9JTklUX0RDU19DTUQoMHhDMywgMHgyNiksCisJX0lOSVRfRENTX0NNRCgweEM0LCAweDMxKSwK
KwlfSU5JVF9EQ1NfQ01EKDB4QzUsIDB4MUMpLAorCV9JTklUX0RDU19DTUQoMHhDNiwgMHgyQyks
CisJX0lOSVRfRENTX0NNRCgweEM3LCAweDMzKSwKKwlfSU5JVF9EQ1NfQ01EKDB4QzgsIDB4MzEp
LAorCV9JTklUX0RDU19DTUQoMHhDOSwgMHgzNyksCisJX0lOSVRfRENTX0NNRCgweENBLCAweDM3
KSwKKwlfSU5JVF9EQ1NfQ01EKDB4Q0IsIDB4MzcpLAorCV9JTklUX0RDU19DTUQoMHhDQywgMHgz
OSksCisJX0lOSVRfRENTX0NNRCgweENELCAweDJFKSwKKwlfSU5JVF9EQ1NfQ01EKDB4Q0UsIDB4
MkYpLAorCV9JTklUX0RDU19DTUQoMHhDRiwgMHgyRiksCisJX0lOSVRfRENTX0NNRCgweEQwLCAw
eDA3KSwKKwlfSU5JVF9EQ1NfQ01EKDB4RDIsIDB4MDApLAorCV9JTklUX0RDU19DTUQoMHhEMywg
MHgwRCksCisJX0lOSVRfRENTX0NNRCgweEQ0LCAweDE3KSwKKwlfSU5JVF9EQ1NfQ01EKDB4RDUs
IDB4MjYpLAorCV9JTklUX0RDU19DTUQoMHhENiwgMHgzMSksCisJX0lOSVRfRENTX0NNRCgweEQ3
LCAweDNGKSwKKwlfSU5JVF9EQ1NfQ01EKDB4RDgsIDB4M0YpLAorCV9JTklUX0RDU19DTUQoMHhE
OSwgMHgzRiksCisJX0lOSVRfRENTX0NNRCgweERBLCAweDNGKSwKKwlfSU5JVF9EQ1NfQ01EKDB4
REIsIDB4MzcpLAorCV9JTklUX0RDU19DTUQoMHhEQywgMHgzNyksCisJX0lOSVRfRENTX0NNRCgw
eERELCAweDM3KSwKKwlfSU5JVF9EQ1NfQ01EKDB4REUsIDB4MzkpLAorCV9JTklUX0RDU19DTUQo
MHhERiwgMHgyRSksCisJX0lOSVRfRENTX0NNRCgweEUwLCAweDJGKSwKKwlfSU5JVF9EQ1NfQ01E
KDB4RTEsIDB4MkYpLAorCV9JTklUX0RDU19DTUQoMHhFMiwgMHgwNyksCisJX0lOSVRfRENTX0NN
RCgweEIwLCAweDAzKSwKKwlfSU5JVF9EQ1NfQ01EKDB4QzgsIDB4MEIpLAorCV9JTklUX0RDU19D
TUQoMHhDOSwgMHgwNyksCisJX0lOSVRfRENTX0NNRCgweEMzLCAweDAwKSwKKwlfSU5JVF9EQ1Nf
Q01EKDB4RTcsIDB4MDApLAorCV9JTklUX0RDU19DTUQoMHhDNSwgMHgyQSksCisJX0lOSVRfRENT
X0NNRCgweERFLCAweDJBKSwKKwlfSU5JVF9EQ1NfQ01EKDB4Q0EsIDB4NDMpLAorCV9JTklUX0RD
U19DTUQoMHhDOSwgMHgwNyksCisJX0lOSVRfRENTX0NNRCgweEU0LCAweEMwKSwKKwlfSU5JVF9E
Q1NfQ01EKDB4RTUsIDB4MEQpLAorCV9JTklUX0RDU19DTUQoMHhDQiwgMHgwMCksCisJX0lOSVRf
RENTX0NNRCgweEIwLCAweDA2KSwKKwlfSU5JVF9EQ1NfQ01EKDB4QjgsIDB4QTUpLAorCV9JTklU
X0RDU19DTUQoMHhDMCwgMHhBNSksCisJX0lOSVRfRENTX0NNRCgweEM3LCAweDBGKSwKKwlfSU5J
VF9EQ1NfQ01EKDB4RDUsIDB4MzIpLAorCV9JTklUX0RDU19DTUQoMHhCOCwgMHgwMCksCisJX0lO
SVRfRENTX0NNRCgweEMwLCAweDAwKSwKKwlfSU5JVF9EQ1NfQ01EKDB4QkMsIDB4MDApLAorCV9J
TklUX0RDU19DTUQoMHhCMCwgMHgwNyksCisJX0lOSVRfRENTX0NNRCgweEIxLCAweDAwKSwKKwlf
SU5JVF9EQ1NfQ01EKDB4QjIsIDB4MDIpLAorCV9JTklUX0RDU19DTUQoMHhCMywgMHgwRiksCisJ
X0lOSVRfRENTX0NNRCgweEI0LCAweDI1KSwKKwlfSU5JVF9EQ1NfQ01EKDB4QjUsIDB4MzkpLAor
CV9JTklUX0RDU19DTUQoMHhCNiwgMHg0RSksCisJX0lOSVRfRENTX0NNRCgweEI3LCAweDcyKSwK
KwlfSU5JVF9EQ1NfQ01EKDB4QjgsIDB4OTcpLAorCV9JTklUX0RDU19DTUQoMHhCOSwgMHhEQyks
CisJX0lOSVRfRENTX0NNRCgweEJBLCAweDIyKSwKKwlfSU5JVF9EQ1NfQ01EKDB4QkIsIDB4QTQp
LAorCV9JTklUX0RDU19DTUQoMHhCQywgMHgyQiksCisJX0lOSVRfRENTX0NNRCgweEJELCAweDJG
KSwKKwlfSU5JVF9EQ1NfQ01EKDB4QkUsIDB4QTkpLAorCV9JTklUX0RDU19DTUQoMHhCRiwgMHgy
NSksCisJX0lOSVRfRENTX0NNRCgweEMwLCAweDYxKSwKKwlfSU5JVF9EQ1NfQ01EKDB4QzEsIDB4
OTcpLAorCV9JTklUX0RDU19DTUQoMHhDMiwgMHhCMiksCisJX0lOSVRfRENTX0NNRCgweEMzLCAw
eENEKSwKKwlfSU5JVF9EQ1NfQ01EKDB4QzQsIDB4RDkpLAorCV9JTklUX0RDU19DTUQoMHhDNSwg
MHhFNyksCisJX0lOSVRfRENTX0NNRCgweEM2LCAweEY0KSwKKwlfSU5JVF9EQ1NfQ01EKDB4Qzcs
IDB4RkEpLAorCV9JTklUX0RDU19DTUQoMHhDOCwgMHhGQyksCisJX0lOSVRfRENTX0NNRCgweEM5
LCAweDAwKSwKKwlfSU5JVF9EQ1NfQ01EKDB4Q0EsIDB4MDApLAorCV9JTklUX0RDU19DTUQoMHhD
QiwgMHgxNiksCisJX0lOSVRfRENTX0NNRCgweENDLCAweEFGKSwKKwlfSU5JVF9EQ1NfQ01EKDB4
Q0QsIDB4RkYpLAorCV9JTklUX0RDU19DTUQoMHhDRSwgMHhGRiksCisJX0lOSVRfRENTX0NNRCgw
eEIwLCAweDA4KSwKKwlfSU5JVF9EQ1NfQ01EKDB4QjEsIDB4MDQpLAorCV9JTklUX0RDU19DTUQo
MHhCMiwgMHgwNSksCisJX0lOSVRfRENTX0NNRCgweEIzLCAweDExKSwKKwlfSU5JVF9EQ1NfQ01E
KDB4QjQsIDB4MjQpLAorCV9JTklUX0RDU19DTUQoMHhCNSwgMHgzOSksCisJX0lOSVRfRENTX0NN
RCgweEI2LCAweDRGKSwKKwlfSU5JVF9EQ1NfQ01EKDB4QjcsIDB4NzIpLAorCV9JTklUX0RDU19D
TUQoMHhCOCwgMHg5OCksCisJX0lOSVRfRENTX0NNRCgweEI5LCAweERDKSwKKwlfSU5JVF9EQ1Nf
Q01EKDB4QkEsIDB4MjMpLAorCV9JTklUX0RDU19DTUQoMHhCQiwgMHhBNiksCisJX0lOSVRfRENT
X0NNRCgweEJDLCAweDJDKSwKKwlfSU5JVF9EQ1NfQ01EKDB4QkQsIDB4MzApLAorCV9JTklUX0RD
U19DTUQoMHhCRSwgMHhBQSksCisJX0lOSVRfRENTX0NNRCgweEJGLCAweDI2KSwKKwlfSU5JVF9E
Q1NfQ01EKDB4QzAsIDB4NjIpLAorCV9JTklUX0RDU19DTUQoMHhDMSwgMHg5QiksCisJX0lOSVRf
RENTX0NNRCgweEMyLCAweEI1KSwKKwlfSU5JVF9EQ1NfQ01EKDB4QzMsIDB4Q0YpLAorCV9JTklU
X0RDU19DTUQoMHhDNCwgMHhEQiksCisJX0lOSVRfRENTX0NNRCgweEM1LCAweEU4KSwKKwlfSU5J
VF9EQ1NfQ01EKDB4QzYsIDB4RjUpLAorCV9JTklUX0RDU19DTUQoMHhDNywgMHhGQSksCisJX0lO
SVRfRENTX0NNRCgweEM4LCAweEZDKSwKKwlfSU5JVF9EQ1NfQ01EKDB4QzksIDB4MDApLAorCV9J
TklUX0RDU19DTUQoMHhDQSwgMHgwMCksCisJX0lOSVRfRENTX0NNRCgweENCLCAweDE2KSwKKwlf
SU5JVF9EQ1NfQ01EKDB4Q0MsIDB4QUYpLAorCV9JTklUX0RDU19DTUQoMHhDRCwgMHhGRiksCisJ
X0lOSVRfRENTX0NNRCgweENFLCAweEZGKSwKKwlfSU5JVF9EQ1NfQ01EKDB4QjAsIDB4MDkpLAor
CV9JTklUX0RDU19DTUQoMHhCMSwgMHgwNCksCisJX0lOSVRfRENTX0NNRCgweEIyLCAweDAyKSwK
KwlfSU5JVF9EQ1NfQ01EKDB4QjMsIDB4MTYpLAorCV9JTklUX0RDU19DTUQoMHhCNCwgMHgyNCks
CisJX0lOSVRfRENTX0NNRCgweEI1LCAweDNCKSwKKwlfSU5JVF9EQ1NfQ01EKDB4QjYsIDB4NEYp
LAorCV9JTklUX0RDU19DTUQoMHhCNywgMHg3MyksCisJX0lOSVRfRENTX0NNRCgweEI4LCAweDk5
KSwKKwlfSU5JVF9EQ1NfQ01EKDB4QjksIDB4RTApLAorCV9JTklUX0RDU19DTUQoMHhCQSwgMHgy
NiksCisJX0lOSVRfRENTX0NNRCgweEJCLCAweEFEKSwKKwlfSU5JVF9EQ1NfQ01EKDB4QkMsIDB4
MzYpLAorCV9JTklUX0RDU19DTUQoMHhCRCwgMHgzQSksCisJX0lOSVRfRENTX0NNRCgweEJFLCAw
eEFFKSwKKwlfSU5JVF9EQ1NfQ01EKDB4QkYsIDB4MkEpLAorCV9JTklUX0RDU19DTUQoMHhDMCwg
MHg2NiksCisJX0lOSVRfRENTX0NNRCgweEMxLCAweDlFKSwKKwlfSU5JVF9EQ1NfQ01EKDB4QzIs
IDB4QjgpLAorCV9JTklUX0RDU19DTUQoMHhDMywgMHhEMSksCisJX0lOSVRfRENTX0NNRCgweEM0
LCAweEREKSwKKwlfSU5JVF9EQ1NfQ01EKDB4QzUsIDB4RTkpLAorCV9JTklUX0RDU19DTUQoMHhD
NiwgMHhGNiksCisJX0lOSVRfRENTX0NNRCgweEM3LCAweEZBKSwKKwlfSU5JVF9EQ1NfQ01EKDB4
QzgsIDB4RkMpLAorCV9JTklUX0RDU19DTUQoMHhDOSwgMHgwMCksCisJX0lOSVRfRENTX0NNRCgw
eENBLCAweDAwKSwKKwlfSU5JVF9EQ1NfQ01EKDB4Q0IsIDB4MTYpLAorCV9JTklUX0RDU19DTUQo
MHhDQywgMHhBRiksCisJX0lOSVRfRENTX0NNRCgweENELCAweEZGKSwKKwlfSU5JVF9EQ1NfQ01E
KDB4Q0UsIDB4RkYpLAorCV9JTklUX0RDU19DTUQoMHhCMCwgMHgwQSksCisJX0lOSVRfRENTX0NN
RCgweEIxLCAweDAwKSwKKwlfSU5JVF9EQ1NfQ01EKDB4QjIsIDB4MDIpLAorCV9JTklUX0RDU19D
TUQoMHhCMywgMHgwRiksCisJX0lOSVRfRENTX0NNRCgweEI0LCAweDI1KSwKKwlfSU5JVF9EQ1Nf
Q01EKDB4QjUsIDB4MzkpLAorCV9JTklUX0RDU19DTUQoMHhCNiwgMHg0RSksCisJX0lOSVRfRENT
X0NNRCgweEI3LCAweDcyKSwKKwlfSU5JVF9EQ1NfQ01EKDB4QjgsIDB4OTcpLAorCV9JTklUX0RD
U19DTUQoMHhCOSwgMHhEQyksCisJX0lOSVRfRENTX0NNRCgweEJBLCAweDIyKSwKKwlfSU5JVF9E
Q1NfQ01EKDB4QkIsIDB4QTQpLAorCV9JTklUX0RDU19DTUQoMHhCQywgMHgyQiksCisJX0lOSVRf
RENTX0NNRCgweEJELCAweDJGKSwKKwlfSU5JVF9EQ1NfQ01EKDB4QkUsIDB4QTkpLAorCV9JTklU
X0RDU19DTUQoMHhCRiwgMHgyNSksCisJX0lOSVRfRENTX0NNRCgweEMwLCAweDYxKSwKKwlfSU5J
VF9EQ1NfQ01EKDB4QzEsIDB4OTcpLAorCV9JTklUX0RDU19DTUQoMHhDMiwgMHhCMiksCisJX0lO
SVRfRENTX0NNRCgweEMzLCAweENEKSwKKwlfSU5JVF9EQ1NfQ01EKDB4QzQsIDB4RDkpLAorCV9J
TklUX0RDU19DTUQoMHhDNSwgMHhFNyksCisJX0lOSVRfRENTX0NNRCgweEM2LCAweEY0KSwKKwlf
SU5JVF9EQ1NfQ01EKDB4QzcsIDB4RkEpLAorCV9JTklUX0RDU19DTUQoMHhDOCwgMHhGQyksCisJ
X0lOSVRfRENTX0NNRCgweEM5LCAweDAwKSwKKwlfSU5JVF9EQ1NfQ01EKDB4Q0EsIDB4MDApLAor
CV9JTklUX0RDU19DTUQoMHhDQiwgMHgxNiksCisJX0lOSVRfRENTX0NNRCgweENDLCAweEFGKSwK
KwlfSU5JVF9EQ1NfQ01EKDB4Q0QsIDB4RkYpLAorCV9JTklUX0RDU19DTUQoMHhDRSwgMHhGRiks
CisJX0lOSVRfRENTX0NNRCgweEIwLCAweDBCKSwKKwlfSU5JVF9EQ1NfQ01EKDB4QjEsIDB4MDQp
LAorCV9JTklUX0RDU19DTUQoMHhCMiwgMHgwNSksCisJX0lOSVRfRENTX0NNRCgweEIzLCAweDEx
KSwKKwlfSU5JVF9EQ1NfQ01EKDB4QjQsIDB4MjQpLAorCV9JTklUX0RDU19DTUQoMHhCNSwgMHgz
OSksCisJX0lOSVRfRENTX0NNRCgweEI2LCAweDRGKSwKKwlfSU5JVF9EQ1NfQ01EKDB4QjcsIDB4
NzIpLAorCV9JTklUX0RDU19DTUQoMHhCOCwgMHg5OCksCisJX0lOSVRfRENTX0NNRCgweEI5LCAw
eERDKSwKKwlfSU5JVF9EQ1NfQ01EKDB4QkEsIDB4MjMpLAorCV9JTklUX0RDU19DTUQoMHhCQiwg
MHhBNiksCisJX0lOSVRfRENTX0NNRCgweEJDLCAweDJDKSwKKwlfSU5JVF9EQ1NfQ01EKDB4QkQs
IDB4MzApLAorCV9JTklUX0RDU19DTUQoMHhCRSwgMHhBQSksCisJX0lOSVRfRENTX0NNRCgweEJG
LCAweDI2KSwKKwlfSU5JVF9EQ1NfQ01EKDB4QzAsIDB4NjIpLAorCV9JTklUX0RDU19DTUQoMHhD
MSwgMHg5QiksCisJX0lOSVRfRENTX0NNRCgweEMyLCAweEI1KSwKKwlfSU5JVF9EQ1NfQ01EKDB4
QzMsIDB4Q0YpLAorCV9JTklUX0RDU19DTUQoMHhDNCwgMHhEQiksCisJX0lOSVRfRENTX0NNRCgw
eEM1LCAweEU4KSwKKwlfSU5JVF9EQ1NfQ01EKDB4QzYsIDB4RjUpLAorCV9JTklUX0RDU19DTUQo
MHhDNywgMHhGQSksCisJX0lOSVRfRENTX0NNRCgweEM4LCAweEZDKSwKKwlfSU5JVF9EQ1NfQ01E
KDB4QzksIDB4MDApLAorCV9JTklUX0RDU19DTUQoMHhDQSwgMHgwMCksCisJX0lOSVRfRENTX0NN
RCgweENCLCAweDE2KSwKKwlfSU5JVF9EQ1NfQ01EKDB4Q0MsIDB4QUYpLAorCV9JTklUX0RDU19D
TUQoMHhDRCwgMHhGRiksCisJX0lOSVRfRENTX0NNRCgweENFLCAweEZGKSwKKwlfSU5JVF9EQ1Nf
Q01EKDB4QjAsIDB4MEMpLAorCV9JTklUX0RDU19DTUQoMHhCMSwgMHgwNCksCisJX0lOSVRfRENT
X0NNRCgweEIyLCAweDAyKSwKKwlfSU5JVF9EQ1NfQ01EKDB4QjMsIDB4MTYpLAorCV9JTklUX0RD
U19DTUQoMHhCNCwgMHgyNCksCisJX0lOSVRfRENTX0NNRCgweEI1LCAweDNCKSwKKwlfSU5JVF9E
Q1NfQ01EKDB4QjYsIDB4NEYpLAorCV9JTklUX0RDU19DTUQoMHhCNywgMHg3MyksCisJX0lOSVRf
RENTX0NNRCgweEI4LCAweDk5KSwKKwlfSU5JVF9EQ1NfQ01EKDB4QjksIDB4RTApLAorCV9JTklU
X0RDU19DTUQoMHhCQSwgMHgyNiksCisJX0lOSVRfRENTX0NNRCgweEJCLCAweEFEKSwKKwlfSU5J
VF9EQ1NfQ01EKDB4QkMsIDB4MzYpLAorCV9JTklUX0RDU19DTUQoMHhCRCwgMHgzQSksCisJX0lO
SVRfRENTX0NNRCgweEJFLCAweEFFKSwKKwlfSU5JVF9EQ1NfQ01EKDB4QkYsIDB4MkEpLAorCV9J
TklUX0RDU19DTUQoMHhDMCwgMHg2NiksCisJX0lOSVRfRENTX0NNRCgweEMxLCAweDlFKSwKKwlf
SU5JVF9EQ1NfQ01EKDB4QzIsIDB4QjgpLAorCV9JTklUX0RDU19DTUQoMHhDMywgMHhEMSksCisJ
X0lOSVRfRENTX0NNRCgweEM0LCAweEREKSwKKwlfSU5JVF9EQ1NfQ01EKDB4QzUsIDB4RTkpLAor
CV9JTklUX0RDU19DTUQoMHhDNiwgMHhGNiksCisJX0lOSVRfRENTX0NNRCgweEM3LCAweEZBKSwK
KwlfSU5JVF9EQ1NfQ01EKDB4QzgsIDB4RkMpLAorCV9JTklUX0RDU19DTUQoMHhDOSwgMHgwMCks
CisJX0lOSVRfRENTX0NNRCgweENBLCAweDAwKSwKKwlfSU5JVF9EQ1NfQ01EKDB4Q0IsIDB4MTYp
LAorCV9JTklUX0RDU19DTUQoMHhDQywgMHhBRiksCisJX0lOSVRfRENTX0NNRCgweENELCAweEZG
KSwKKwlfSU5JVF9EQ1NfQ01EKDB4Q0UsIDB4RkYpLAorCV9JTklUX0RDU19DTUQoMHhCMCwgMHgw
MCksCisJX0lOSVRfRENTX0NNRCgweEIzLCAweDA4KSwKKwlfSU5JVF9EQ1NfQ01EKDB4QjAsIDB4
MDQpLAorCV9JTklUX0RDU19DTUQoMHhCOCwgMHg2OCksCisJX0lOSVRfREVMQVlfQ01EKDE1MCks
CisJe30sCit9OworCitzdGF0aWMgaW5saW5lIHN0cnVjdCBib2VfcGFuZWwgKnRvX2JvZV9wYW5l
bChzdHJ1Y3QgZHJtX3BhbmVsICpwYW5lbCkKK3sKKwlyZXR1cm4gY29udGFpbmVyX29mKHBhbmVs
LCBzdHJ1Y3QgYm9lX3BhbmVsLCBiYXNlKTsKK30KKworc3RhdGljIGludCBib2VfcGFuZWxfaW5p
dChzdHJ1Y3QgYm9lX3BhbmVsICpib2UpCit7CisJc3RydWN0IG1pcGlfZHNpX2RldmljZSAqZHNp
ID0gYm9lLT5kc2k7CisJc3RydWN0IGRybV9wYW5lbCAqcGFuZWwgPSAmYm9lLT5iYXNlOworCWlu
dCBlcnIsIGk7CisKKwlpZiAoYm9lLT5kZXNjLT5pbml0X2NtZHMpIHsKKwkJY29uc3Qgc3RydWN0
IHBhbmVsX2luaXRfY21kICppbml0X2NtZHMgPSBib2UtPmRlc2MtPmluaXRfY21kczsKKworCQlm
b3IgKGkgPSAwOyBpbml0X2NtZHNbaV0ubGVuICE9IDA7IGkrKykgeworCQkJY29uc3Qgc3RydWN0
IHBhbmVsX2luaXRfY21kICpjbWQgPSAmaW5pdF9jbWRzW2ldOworCisJCQlzd2l0Y2ggKGNtZC0+
dHlwZSkgeworCQkJY2FzZSBERUxBWV9DTUQ6CisJCQkJbXNsZWVwKGNtZC0+ZGF0YVswXSk7CisJ
CQkJZXJyID0gMDsKKwkJCQlicmVhazsKKworCQkJY2FzZSBJTklUX0RDU19DTUQ6CisJCQkJZXJy
ID0gbWlwaV9kc2lfZGNzX3dyaXRlKGRzaSwgY21kLT5kYXRhWzBdLAorCQkJCQkJCSBjbWQtPmxl
biA8PSAxID8gTlVMTCA6CisJCQkJCQkJICZjbWQtPmRhdGFbMV0sCisJCQkJCQkJIGNtZC0+bGVu
IC0gMSk7CisJCQkJYnJlYWs7CisJCQl9CisKKwkJCWlmIChlcnIgPCAwKSB7CisJCQkJZGV2X2Vy
cihwYW5lbC0+ZGV2LAorCQkJCQkiZmFpbGVkIHRvIHdyaXRlIGNvbW1hbmQgJXVcbiIsIGkpOwor
CQkJCXJldHVybiBlcnI7CisJCQl9CisJCX0KKwl9CisJcmV0dXJuIDA7Cit9CisKK3N0YXRpYyBp
bnQgYm9lX3BhbmVsX29mZihzdHJ1Y3QgYm9lX3BhbmVsICpib2UpCit7CisJc3RydWN0IG1pcGlf
ZHNpX2RldmljZSAqZHNpID0gYm9lLT5kc2k7CisJaW50IHJldDsKKworCWRzaS0+bW9kZV9mbGFn
cyAmPSB+TUlQSV9EU0lfTU9ERV9MUE07CisKKwlyZXQgPSBtaXBpX2RzaV9kY3NfZW50ZXJfc2xl
ZXBfbW9kZShkc2kpOworCWlmIChyZXQgPCAwKQorCQlyZXR1cm4gcmV0OworCisJcmV0dXJuIDA7
Cit9CisKK3N0YXRpYyBpbnQgYm9lX3BhbmVsX2Rpc2FibGUoc3RydWN0IGRybV9wYW5lbCAqcGFu
ZWwpCit7CisJc3RydWN0IGJvZV9wYW5lbCAqYm9lID0gdG9fYm9lX3BhbmVsKHBhbmVsKTsKKwor
CWlmICghYm9lLT5lbmFibGVkKQorCQlyZXR1cm4gMDsKKworCWJhY2tsaWdodF9kaXNhYmxlKGJv
ZS0+YmFja2xpZ2h0KTsKKworCWJvZS0+ZW5hYmxlZCA9IGZhbHNlOworCisJcmV0dXJuIDA7Cit9
CisKK3N0YXRpYyBpbnQgYm9lX3BhbmVsX3VucHJlcGFyZShzdHJ1Y3QgZHJtX3BhbmVsICpwYW5l
bCkKK3sKKwlzdHJ1Y3QgYm9lX3BhbmVsICpib2UgPSB0b19ib2VfcGFuZWwocGFuZWwpOworCWlu
dCByZXQ7CisKKwlpZiAoIWJvZS0+cHJlcGFyZWQpCisJCXJldHVybiAwOworCisJcmV0ID0gYm9l
X3BhbmVsX29mZihib2UpOworCWlmIChyZXQgPCAwKSB7CisJCWRldl9lcnIocGFuZWwtPmRldiwg
ImZhaWxlZCB0byBzZXQgcGFuZWwgb2ZmOiAlZFxuIiwgcmV0KTsKKwkJcmV0dXJuIHJldDsKKwl9
CisKKwltc2xlZXAoMTUwKTsKKwlpZiAoYm9lLT5lbmFibGVfZ3BpbykKKwkJZ3Bpb2Rfc2V0X3Zh
bHVlKGJvZS0+ZW5hYmxlX2dwaW8sIDApOworCXVzbGVlcF9yYW5nZSg1MDAsIDEwMDApOworCXJl
Z3VsYXRvcl9kaXNhYmxlKGJvZS0+YXZlZSk7CisJcmVndWxhdG9yX2Rpc2FibGUoYm9lLT5hdmRk
KTsKKwl1c2xlZXBfcmFuZ2UoNTAwMCwgNzAwMCk7CisJcmVndWxhdG9yX2Rpc2FibGUoYm9lLT5w
cDE4MDApOworCisJYm9lLT5wcmVwYXJlZCA9IGZhbHNlOworCisJcmV0dXJuIDA7Cit9CisKK3N0
YXRpYyBpbnQgYm9lX3BhbmVsX3ByZXBhcmUoc3RydWN0IGRybV9wYW5lbCAqcGFuZWwpCit7CisJ
c3RydWN0IGJvZV9wYW5lbCAqYm9lID0gdG9fYm9lX3BhbmVsKHBhbmVsKTsKKwlpbnQgcmV0Owor
CisJaWYgKGJvZS0+cHJlcGFyZWQpCisJCXJldHVybiAwOworCisJaWYgKGJvZS0+ZW5hYmxlX2dw
aW8pIHsKKwkJZ3Bpb2Rfc2V0X3ZhbHVlKGJvZS0+ZW5hYmxlX2dwaW8sIDApOworCQl1c2xlZXBf
cmFuZ2UoMTAwMCwgMTUwMCk7CisJfQorCisJcmV0ID0gcmVndWxhdG9yX2VuYWJsZShib2UtPnBw
MTgwMCk7CisJaWYgKHJldCA8IDApCisJCXJldHVybiByZXQ7CisKKwl1c2xlZXBfcmFuZ2UoMzAw
MCwgNTAwMCk7CisKKwlyZXQgPSByZWd1bGF0b3JfZW5hYmxlKGJvZS0+YXZkZCk7CisJaWYgKHJl
dCA8IDApCisJCWdvdG8gcG93ZXJvZmYxdjg7CisJcmV0ID0gcmVndWxhdG9yX2VuYWJsZShib2Ut
PmF2ZWUpOworCWlmIChyZXQgPCAwKQorCQlnb3RvIHBvd2Vyb2ZmYXZkZDsKKworCW1zbGVlcCgx
MDApOworCisJaWYgKGJvZS0+ZW5hYmxlX2dwaW8pIHsKKwkJZ3Bpb2Rfc2V0X3ZhbHVlKGJvZS0+
ZW5hYmxlX2dwaW8sIDEpOworCQl1c2xlZXBfcmFuZ2UoMTAwMDAsIDEyMDAwKTsKKwl9CisKKwly
ZXQgPSBib2VfcGFuZWxfaW5pdChib2UpOworCWlmIChyZXQgPCAwKSB7CisJCWRldl9lcnIocGFu
ZWwtPmRldiwgImZhaWxlZCB0byBpbml0IHBhbmVsOiAlZFxuIiwgcmV0KTsKKwkJZ290byBwb3dl
cm9mZjsKKwl9CisKKwlib2UtPnByZXBhcmVkID0gdHJ1ZTsKKworCXJldHVybiAwOworCitwb3dl
cm9mZjoKKwlyZWd1bGF0b3JfZGlzYWJsZShib2UtPmF2ZWUpOworcG93ZXJvZmZhdmRkOgorCXJl
Z3VsYXRvcl9kaXNhYmxlKGJvZS0+YXZkZCk7Citwb3dlcm9mZjF2ODoKKwl1c2xlZXBfcmFuZ2Uo
NTAwMCwgNzAwMCk7CisJcmVndWxhdG9yX2Rpc2FibGUoYm9lLT5wcDE4MDApOworCWlmIChib2Ut
PmVuYWJsZV9ncGlvKQorCQlncGlvZF9zZXRfdmFsdWUoYm9lLT5lbmFibGVfZ3BpbywgMCk7CisJ
cmV0dXJuIHJldDsKK30KKworc3RhdGljIGludCBib2VfcGFuZWxfZW5hYmxlKHN0cnVjdCBkcm1f
cGFuZWwgKnBhbmVsKQoreworCXN0cnVjdCBib2VfcGFuZWwgKmJvZSA9IHRvX2JvZV9wYW5lbChw
YW5lbCk7CisJaW50IHJldDsKKworCWlmIChib2UtPmVuYWJsZWQpCisJCXJldHVybiAwOworCisJ
cmV0ID0gYmFja2xpZ2h0X2VuYWJsZShib2UtPmJhY2tsaWdodCk7CisJaWYgKHJldCkgeworCQlk
ZXZfZXJyKHBhbmVsLT5kZXYsICJGYWlsZWQgdG8gZW5hYmxlIGJhY2tsaWdodCAlZFxuIiwKKwkJ
CXJldCk7CisJCXJldHVybiByZXQ7CisJfQorCisJYm9lLT5lbmFibGVkID0gdHJ1ZTsKKworCXJl
dHVybiAwOworfQorCitzdGF0aWMgY29uc3Qgc3RydWN0IGRybV9kaXNwbGF5X21vZGUgYm9lX2Rl
ZmF1bHRfbW9kZSA9IHsKKwkuY2xvY2sgPSAxNTk0MjUsCisJLmhkaXNwbGF5ID0gMTIwMCwKKwku
aHN5bmNfc3RhcnQgPSAxMjAwICsgMTAwLAorCS5oc3luY19lbmQgPSAxMjAwICsgMTAwICsgNDAs
CisJLmh0b3RhbCA9IDEyMDAgKyAxMDAgKyA0MCArIDI0LAorCS52ZGlzcGxheSA9IDE5MjAsCisJ
LnZzeW5jX3N0YXJ0ID0gMTkyMCArIDEwLAorCS52c3luY19lbmQgPSAxOTIwICsgMTAgKyAxNCwK
KwkudnRvdGFsID0gMTkyMCArIDEwICsgMTQgKyA0LAorCS52cmVmcmVzaCA9IDYwLAorfTsKKwor
c3RhdGljIGNvbnN0IHN0cnVjdCBwYW5lbF9kZXNjIGJvZV90djEwMXd1bV9ubDZfZGVzYyA9IHsK
KwkubW9kZXMgPSAmYm9lX2RlZmF1bHRfbW9kZSwKKwkuYnBjID0gOCwKKwkuc2l6ZSA9IHsKKwkJ
LndpZHRoID0gMTM1LAorCQkuaGVpZ2h0ID0gMjE2LAorCX0sCisJLmxhbmVzID0gNCwKKwkuZm9y
bWF0ID0gTUlQSV9EU0lfRk1UX1JHQjg4OCwKKwkubW9kZV9mbGFncyA9IE1JUElfRFNJX01PREVf
VklERU8gfCBNSVBJX0RTSV9NT0RFX1ZJREVPX1NZTkNfUFVMU0UgfAorCQkgICAgICBNSVBJX0RT
SV9NT0RFX0xQTSwKKwkuaW5pdF9jbWRzID0gYm9lX2luaXRfY21kLAorfTsKKworc3RhdGljIGlu
dCBib2VfcGFuZWxfZ2V0X21vZGVzKHN0cnVjdCBkcm1fcGFuZWwgKnBhbmVsKQoreworCXN0cnVj
dCBib2VfcGFuZWwgKmJvZSA9IHRvX2JvZV9wYW5lbChwYW5lbCk7CisJY29uc3Qgc3RydWN0IGRy
bV9kaXNwbGF5X21vZGUgKm0gPSBib2UtPmRlc2MtPm1vZGVzOworCXN0cnVjdCBkcm1fZGlzcGxh
eV9tb2RlICptb2RlOworCisJbW9kZSA9IGRybV9tb2RlX2R1cGxpY2F0ZShwYW5lbC0+ZHJtLCBt
KTsKKwlpZiAoIW1vZGUpIHsKKwkJZGV2X2VycihwYW5lbC0+ZGV2LCAiZmFpbGVkIHRvIGFkZCBt
b2RlICV1eCV1QCV1XG4iLAorCQkJbS0+aGRpc3BsYXksIG0tPnZkaXNwbGF5LCBtLT52cmVmcmVz
aCk7CisJCXJldHVybiAtRU5PTUVNOworCX0KKworCW1vZGUtPnR5cGUgPSBEUk1fTU9ERV9UWVBF
X0RSSVZFUiB8IERSTV9NT0RFX1RZUEVfUFJFRkVSUkVEOworCWRybV9tb2RlX3NldF9uYW1lKG1v
ZGUpOworCWRybV9tb2RlX3Byb2JlZF9hZGQocGFuZWwtPmNvbm5lY3RvciwgbW9kZSk7CisKKwlw
YW5lbC0+Y29ubmVjdG9yLT5kaXNwbGF5X2luZm8ud2lkdGhfbW0gPSBib2UtPmRlc2MtPnNpemUu
d2lkdGg7CisJcGFuZWwtPmNvbm5lY3Rvci0+ZGlzcGxheV9pbmZvLmhlaWdodF9tbSA9IGJvZS0+
ZGVzYy0+c2l6ZS5oZWlnaHQ7CisJcGFuZWwtPmNvbm5lY3Rvci0+ZGlzcGxheV9pbmZvLmJwYyA9
IGJvZS0+ZGVzYy0+YnBjOworCisJcmV0dXJuIDE7Cit9CisKK3N0YXRpYyBjb25zdCBzdHJ1Y3Qg
ZHJtX3BhbmVsX2Z1bmNzIGJvZV9wYW5lbF9mdW5jcyA9IHsKKwkuZGlzYWJsZSA9IGJvZV9wYW5l
bF9kaXNhYmxlLAorCS51bnByZXBhcmUgPSBib2VfcGFuZWxfdW5wcmVwYXJlLAorCS5wcmVwYXJl
ID0gYm9lX3BhbmVsX3ByZXBhcmUsCisJLmVuYWJsZSA9IGJvZV9wYW5lbF9lbmFibGUsCisJLmdl
dF9tb2RlcyA9IGJvZV9wYW5lbF9nZXRfbW9kZXMsCit9OworCitzdGF0aWMgaW50IGJvZV9wYW5l
bF9hZGQoc3RydWN0IGJvZV9wYW5lbCAqYm9lKQoreworCXN0cnVjdCBkZXZpY2UgKmRldiA9ICZi
b2UtPmRzaS0+ZGV2OworCisJYm9lLT5hdmRkID0gZGV2bV9yZWd1bGF0b3JfZ2V0KGRldiwgImF2
ZGQiKTsKKwlpZiAoSVNfRVJSKGJvZS0+YXZkZCkpCisJCXJldHVybiBQVFJfRVJSKGJvZS0+YXZk
ZCk7CisKKwlib2UtPmF2ZWUgPSBkZXZtX3JlZ3VsYXRvcl9nZXQoZGV2LCAiYXZlZSIpOworCWlm
IChJU19FUlIoYm9lLT5hdmVlKSkKKwkJcmV0dXJuIFBUUl9FUlIoYm9lLT5hdmVlKTsKKworCWJv
ZS0+cHAxODAwID0gZGV2bV9yZWd1bGF0b3JfZ2V0KGRldiwgInBwMTgwMCIpOworCWlmIChJU19F
UlIoYm9lLT5wcDE4MDApKQorCQlyZXR1cm4gUFRSX0VSUihib2UtPnBwMTgwMCk7CisKKwlib2Ut
PmVuYWJsZV9ncGlvID0gZGV2bV9ncGlvZF9nZXQoZGV2LCAiZW5hYmxlIiwgR1BJT0RfT1VUX0xP
Vyk7CisJaWYgKElTX0VSUihib2UtPmVuYWJsZV9ncGlvKSkgeworCQlkZXZfZXJyKGRldiwgImNh
bm5vdCBnZXQgcmVzZXQtZ3Bpb3MgJWxkXG4iLAorCQkJUFRSX0VSUihib2UtPmVuYWJsZV9ncGlv
KSk7CisJCXJldHVybiBQVFJfRVJSKGJvZS0+ZW5hYmxlX2dwaW8pOworCX0KKworCWdwaW9kX3Nl
dF92YWx1ZShib2UtPmVuYWJsZV9ncGlvLCAwKTsKKworCWJvZS0+YmFja2xpZ2h0ID0gZGV2bV9v
Zl9maW5kX2JhY2tsaWdodChkZXYpOworCWlmIChJU19FUlIoYm9lLT5iYWNrbGlnaHQpKQorCQly
ZXR1cm4gUFRSX0VSUihib2UtPmJhY2tsaWdodCk7CisKKwlkcm1fcGFuZWxfaW5pdCgmYm9lLT5i
YXNlKTsKKwlib2UtPmJhc2UuZnVuY3MgPSAmYm9lX3BhbmVsX2Z1bmNzOworCWJvZS0+YmFzZS5k
ZXYgPSAmYm9lLT5kc2ktPmRldjsKKworCXJldHVybiBkcm1fcGFuZWxfYWRkKCZib2UtPmJhc2Up
OworfQorCitzdGF0aWMgaW50IGJvZV9wYW5lbF9wcm9iZShzdHJ1Y3QgbWlwaV9kc2lfZGV2aWNl
ICpkc2kpCit7CisJc3RydWN0IGJvZV9wYW5lbCAqYm9lOworCWludCByZXQ7CisJY29uc3Qgc3Ry
dWN0IHBhbmVsX2Rlc2MgKmRlc2M7CisKKwlib2UgPSBkZXZtX2t6YWxsb2MoJmRzaS0+ZGV2LCBz
aXplb2YoKmJvZSksIEdGUF9LRVJORUwpOworCWlmICghYm9lKQorCQlyZXR1cm4gLUVOT01FTTsK
KworCWRlc2MgPSBvZl9kZXZpY2VfZ2V0X21hdGNoX2RhdGEoJmRzaS0+ZGV2KTsKKwlkc2ktPmxh
bmVzID0gZGVzYy0+bGFuZXM7CisJZHNpLT5mb3JtYXQgPSBkZXNjLT5mb3JtYXQ7CisJZHNpLT5t
b2RlX2ZsYWdzID0gZGVzYy0+bW9kZV9mbGFnczsKKwlib2UtPmRlc2MgPSBkZXNjOworCWJvZS0+
ZHNpID0gZHNpOworCXJldCA9IGJvZV9wYW5lbF9hZGQoYm9lKTsKKwlpZiAocmV0IDwgMCkKKwkJ
cmV0dXJuIHJldDsKKworCW1pcGlfZHNpX3NldF9kcnZkYXRhKGRzaSwgYm9lKTsKKworCXJldHVy
biBtaXBpX2RzaV9hdHRhY2goZHNpKTsKK30KKworc3RhdGljIGludCBib2VfcGFuZWxfcmVtb3Zl
KHN0cnVjdCBtaXBpX2RzaV9kZXZpY2UgKmRzaSkKK3sKKwlzdHJ1Y3QgYm9lX3BhbmVsICpib2Ug
PSBtaXBpX2RzaV9nZXRfZHJ2ZGF0YShkc2kpOworCWludCByZXQ7CisKKwlyZXQgPSBib2VfcGFu
ZWxfZGlzYWJsZSgmYm9lLT5iYXNlKTsKKwlpZiAocmV0IDwgMCkKKwkJZGV2X2VycigmZHNpLT5k
ZXYsICJmYWlsZWQgdG8gZGlzYWJsZSBwYW5lbDogJWRcbiIsIHJldCk7CisKKwlyZXQgPSBtaXBp
X2RzaV9kZXRhY2goZHNpKTsKKwlpZiAocmV0IDwgMCkKKwkJZGV2X2VycigmZHNpLT5kZXYsICJm
YWlsZWQgdG8gZGV0YWNoIGZyb20gRFNJIGhvc3Q6ICVkXG4iLCByZXQpOworCisJaWYgKGJvZS0+
YmFzZS5kZXYpCisJCWRybV9wYW5lbF9yZW1vdmUoJmJvZS0+YmFzZSk7CisKKwlyZXR1cm4gMDsK
K30KKworc3RhdGljIHZvaWQgYm9lX3BhbmVsX3NodXRkb3duKHN0cnVjdCBtaXBpX2RzaV9kZXZp
Y2UgKmRzaSkKK3sKKwlzdHJ1Y3QgYm9lX3BhbmVsICpib2UgPSBtaXBpX2RzaV9nZXRfZHJ2ZGF0
YShkc2kpOworCisJYm9lX3BhbmVsX2Rpc2FibGUoJmJvZS0+YmFzZSk7Cit9CisKK3N0YXRpYyBj
b25zdCBzdHJ1Y3Qgb2ZfZGV2aWNlX2lkIGJvZV9vZl9tYXRjaFtdID0geworCXsgLmNvbXBhdGli
bGUgPSAiYm9lLHR2MTAxd3VtLW5sNiIsCisJICAuZGF0YSA9ICZib2VfdHYxMDF3dW1fbmw2X2Rl
c2MKKwl9LAorCXsgLyogc2VudGluZWwgKi8gfQorfTsKK01PRFVMRV9ERVZJQ0VfVEFCTEUob2Ys
IGJvZV9vZl9tYXRjaCk7CisKK3N0YXRpYyBzdHJ1Y3QgbWlwaV9kc2lfZHJpdmVyIGJvZV9wYW5l
bF9kcml2ZXIgPSB7CisJLmRyaXZlciA9IHsKKwkJLm5hbWUgPSAicGFuZWwtYm9lLXR2MTAxd3Vt
LW5sNiIsCisJCS5vZl9tYXRjaF90YWJsZSA9IGJvZV9vZl9tYXRjaCwKKwl9LAorCS5wcm9iZSA9
IGJvZV9wYW5lbF9wcm9iZSwKKwkucmVtb3ZlID0gYm9lX3BhbmVsX3JlbW92ZSwKKwkuc2h1dGRv
d24gPSBib2VfcGFuZWxfc2h1dGRvd24sCit9OworbW9kdWxlX21pcGlfZHNpX2RyaXZlcihib2Vf
cGFuZWxfZHJpdmVyKTsKKworTU9EVUxFX0FVVEhPUigiSml0YW8gU2hpIDxqaXRhby5zaGlAbWVk
aWF0ZWsuY29tPiIpOworTU9EVUxFX0RFU0NSSVBUSU9OKCJCT0UgdHYxMDF3dW0tbmw2IDEyMDB4
MTkyMCB2aWRlbyBtb2RlIHBhbmVsIGRyaXZlciIpOworTU9EVUxFX0xJQ0VOU0UoIkdQTCB2MiIp
OwotLSAKMi4yMS4wCgpfX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19f
X19fXwpkcmktZGV2ZWwgbWFpbGluZyBsaXN0CmRyaS1kZXZlbEBsaXN0cy5mcmVlZGVza3RvcC5v
cmcKaHR0cHM6Ly9saXN0cy5mcmVlZGVza3RvcC5vcmcvbWFpbG1hbi9saXN0aW5mby9kcmktZGV2
ZWw=

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To: Rob Herring <robh+dt@kernel.org>, Pawel Moll <pawel.moll@arm.com>, "Mark
 Rutland" <mark.rutland@arm.com>, Ian Campbell
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 <airlied@linux.ie>, "Matthias Brugger" <matthias.bgg@gmail.com>
Subject: [v3 2/4] drm/panel: support for BOE tv101wum-nl6 wuxga dsi video mode
 panel
Date: Wed, 26 Jun 2019 10:53:58 +0800
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Add driver for BOE tv101wum-nl6 panel is a 10.1" 1200x1920 panel.

Signed-off-by: Jitao Shi <jitao.shi@mediatek.com>
---
 drivers/gpu/drm/panel/Kconfig                 |   9 +
 drivers/gpu/drm/panel/Makefile                |   1 +
 .../gpu/drm/panel/panel-boe-tv101wum-nl6.c    | 714 ++++++++++++++++++
 3 files changed, 724 insertions(+)
 create mode 100644 drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c

diff --git a/drivers/gpu/drm/panel/Kconfig b/drivers/gpu/drm/panel/Kconfig
index e36dbb4df867..706f6ff2b4fa 100644
--- a/drivers/gpu/drm/panel/Kconfig
+++ b/drivers/gpu/drm/panel/Kconfig
@@ -17,6 +17,15 @@ config DRM_PANEL_ARM_VERSATILE
 	  reference designs. The panel is detected using special registers
 	  in the Versatile family syscon registers.
 
+config DRM_PANEL_BOE_TV101WUM_NL6
+	tristate "BOE TV101WUM 1200x1920 panel"
+	depends on OF
+	depends on DRM_MIPI_DSI
+	depends on BACKLIGHT_CLASS_DEVICE
+	help
+	  Say Y here if you want to support for BOE TV101WUM WUXGA PANEL
+	  DSI Video Mode panel
+
 config DRM_PANEL_LVDS
 	tristate "Generic LVDS panel driver"
 	depends on OF
diff --git a/drivers/gpu/drm/panel/Makefile b/drivers/gpu/drm/panel/Makefile
index 78e3dc376bdd..8d009223c44e 100644
--- a/drivers/gpu/drm/panel/Makefile
+++ b/drivers/gpu/drm/panel/Makefile
@@ -1,5 +1,6 @@
 # SPDX-License-Identifier: GPL-2.0
 obj-$(CONFIG_DRM_PANEL_ARM_VERSATILE) += panel-arm-versatile.o
+obj-$(CONFIG_DRM_PANEL_BOE_TV101WUM_NL6) += panel-boe-tv101wum-nl6.o
 obj-$(CONFIG_DRM_PANEL_LVDS) += panel-lvds.o
 obj-$(CONFIG_DRM_PANEL_SIMPLE) += panel-simple.o
 obj-$(CONFIG_DRM_PANEL_FEIYANG_FY07024DI26A30D) += panel-feiyang-fy07024di26a30d.o
diff --git a/drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c b/drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c
new file mode 100644
index 000000000000..30d1f53dcbaf
--- /dev/null
+++ b/drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c
@@ -0,0 +1,714 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2018 MediaTek Inc.
+ * Author: Jitao Shi <jitao.shi@mediatek.com>
+ */
+
+#include <linux/backlight.h>
+#include <linux/delay.h>
+#include <linux/gpio/consumer.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/regulator/consumer.h>
+
+#include <drm/drm_crtc.h>
+#include <drm/drm_mipi_dsi.h>
+#include <drm/drm_panel.h>
+
+#include <video/mipi_display.h>
+
+struct panel_desc {
+	const struct drm_display_mode *modes;
+	unsigned int bpc;
+
+	/**
+	 * @width: width (in millimeters) of the panel's active display area
+	 * @height: height (in millimeters) of the panel's active display area
+	 */
+	struct {
+		unsigned int width;
+		unsigned int height;
+	} size;
+
+	unsigned long mode_flags;
+	enum mipi_dsi_pixel_format format;
+	const struct panel_init_cmd *init_cmds;
+	unsigned int lanes;
+};
+
+struct boe_panel {
+	struct drm_panel base;
+	struct mipi_dsi_device *dsi;
+
+	const struct panel_desc *desc;
+
+	struct backlight_device *backlight;
+	struct regulator *pp1800;
+	struct regulator *avee;
+	struct regulator *avdd;
+	struct gpio_desc *enable_gpio;
+
+	bool prepared;
+	bool enabled;
+
+	const struct drm_display_mode *mode;
+};
+
+enum dsi_cmd_type {
+	INIT_DCS_CMD,
+	DELAY_CMD,
+};
+
+struct panel_init_cmd {
+	enum dsi_cmd_type type;
+	size_t len;
+	const char *data;
+};
+
+#define _INIT_DCS_CMD(...) { \
+	.type = INIT_DCS_CMD, \
+	.len = sizeof((char[]){__VA_ARGS__}), \
+	.data = (char[]){__VA_ARGS__} }
+
+#define _INIT_DELAY_CMD(...) { \
+	.type = DELAY_CMD,\
+	.len = sizeof((char[]){__VA_ARGS__}), \
+	.data = (char[]){__VA_ARGS__} }
+
+static const struct panel_init_cmd boe_init_cmd[] = {
+	_INIT_DELAY_CMD(24),
+	_INIT_DCS_CMD(0xB0, 0x05),
+	_INIT_DCS_CMD(0xB1, 0xE5),
+	_INIT_DCS_CMD(0xB3, 0x52),
+	_INIT_DCS_CMD(0xB0, 0x00),
+	_INIT_DCS_CMD(0xB3, 0x88),
+	_INIT_DCS_CMD(0xB0, 0x04),
+	_INIT_DCS_CMD(0xB8, 0x00),
+	_INIT_DCS_CMD(0xB0, 0x00),
+	_INIT_DCS_CMD(0xB6, 0x03),
+	_INIT_DCS_CMD(0xBA, 0x8B),
+	_INIT_DCS_CMD(0xBF, 0x1A),
+	_INIT_DCS_CMD(0xC0, 0x0F),
+	_INIT_DCS_CMD(0xC2, 0x0C),
+	_INIT_DCS_CMD(0xC3, 0x02),
+	_INIT_DCS_CMD(0xC4, 0x0C),
+	_INIT_DCS_CMD(0xC5, 0x02),
+	_INIT_DCS_CMD(0xB0, 0x01),
+	_INIT_DCS_CMD(0xE0, 0x26),
+	_INIT_DCS_CMD(0xE1, 0x26),
+	_INIT_DCS_CMD(0xDC, 0x00),
+	_INIT_DCS_CMD(0xDD, 0x00),
+	_INIT_DCS_CMD(0xCC, 0x26),
+	_INIT_DCS_CMD(0xCD, 0x26),
+	_INIT_DCS_CMD(0xC8, 0x00),
+	_INIT_DCS_CMD(0xC9, 0x00),
+	_INIT_DCS_CMD(0xD2, 0x03),
+	_INIT_DCS_CMD(0xD3, 0x03),
+	_INIT_DCS_CMD(0xE6, 0x04),
+	_INIT_DCS_CMD(0xE7, 0x04),
+	_INIT_DCS_CMD(0xC4, 0x09),
+	_INIT_DCS_CMD(0xC5, 0x09),
+	_INIT_DCS_CMD(0xD8, 0x0A),
+	_INIT_DCS_CMD(0xD9, 0x0A),
+	_INIT_DCS_CMD(0xC2, 0x0B),
+	_INIT_DCS_CMD(0xC3, 0x0B),
+	_INIT_DCS_CMD(0xD6, 0x0C),
+	_INIT_DCS_CMD(0xD7, 0x0C),
+	_INIT_DCS_CMD(0xC0, 0x05),
+	_INIT_DCS_CMD(0xC1, 0x05),
+	_INIT_DCS_CMD(0xD4, 0x06),
+	_INIT_DCS_CMD(0xD5, 0x06),
+	_INIT_DCS_CMD(0xCA, 0x07),
+	_INIT_DCS_CMD(0xCB, 0x07),
+	_INIT_DCS_CMD(0xDE, 0x08),
+	_INIT_DCS_CMD(0xDF, 0x08),
+	_INIT_DCS_CMD(0xB0, 0x02),
+	_INIT_DCS_CMD(0xC0, 0x00),
+	_INIT_DCS_CMD(0xC1, 0x0D),
+	_INIT_DCS_CMD(0xC2, 0x17),
+	_INIT_DCS_CMD(0xC3, 0x26),
+	_INIT_DCS_CMD(0xC4, 0x31),
+	_INIT_DCS_CMD(0xC5, 0x1C),
+	_INIT_DCS_CMD(0xC6, 0x2C),
+	_INIT_DCS_CMD(0xC7, 0x33),
+	_INIT_DCS_CMD(0xC8, 0x31),
+	_INIT_DCS_CMD(0xC9, 0x37),
+	_INIT_DCS_CMD(0xCA, 0x37),
+	_INIT_DCS_CMD(0xCB, 0x37),
+	_INIT_DCS_CMD(0xCC, 0x39),
+	_INIT_DCS_CMD(0xCD, 0x2E),
+	_INIT_DCS_CMD(0xCE, 0x2F),
+	_INIT_DCS_CMD(0xCF, 0x2F),
+	_INIT_DCS_CMD(0xD0, 0x07),
+	_INIT_DCS_CMD(0xD2, 0x00),
+	_INIT_DCS_CMD(0xD3, 0x0D),
+	_INIT_DCS_CMD(0xD4, 0x17),
+	_INIT_DCS_CMD(0xD5, 0x26),
+	_INIT_DCS_CMD(0xD6, 0x31),
+	_INIT_DCS_CMD(0xD7, 0x3F),
+	_INIT_DCS_CMD(0xD8, 0x3F),
+	_INIT_DCS_CMD(0xD9, 0x3F),
+	_INIT_DCS_CMD(0xDA, 0x3F),
+	_INIT_DCS_CMD(0xDB, 0x37),
+	_INIT_DCS_CMD(0xDC, 0x37),
+	_INIT_DCS_CMD(0xDD, 0x37),
+	_INIT_DCS_CMD(0xDE, 0x39),
+	_INIT_DCS_CMD(0xDF, 0x2E),
+	_INIT_DCS_CMD(0xE0, 0x2F),
+	_INIT_DCS_CMD(0xE1, 0x2F),
+	_INIT_DCS_CMD(0xE2, 0x07),
+	_INIT_DCS_CMD(0xB0, 0x03),
+	_INIT_DCS_CMD(0xC8, 0x0B),
+	_INIT_DCS_CMD(0xC9, 0x07),
+	_INIT_DCS_CMD(0xC3, 0x00),
+	_INIT_DCS_CMD(0xE7, 0x00),
+	_INIT_DCS_CMD(0xC5, 0x2A),
+	_INIT_DCS_CMD(0xDE, 0x2A),
+	_INIT_DCS_CMD(0xCA, 0x43),
+	_INIT_DCS_CMD(0xC9, 0x07),
+	_INIT_DCS_CMD(0xE4, 0xC0),
+	_INIT_DCS_CMD(0xE5, 0x0D),
+	_INIT_DCS_CMD(0xCB, 0x00),
+	_INIT_DCS_CMD(0xB0, 0x06),
+	_INIT_DCS_CMD(0xB8, 0xA5),
+	_INIT_DCS_CMD(0xC0, 0xA5),
+	_INIT_DCS_CMD(0xC7, 0x0F),
+	_INIT_DCS_CMD(0xD5, 0x32),
+	_INIT_DCS_CMD(0xB8, 0x00),
+	_INIT_DCS_CMD(0xC0, 0x00),
+	_INIT_DCS_CMD(0xBC, 0x00),
+	_INIT_DCS_CMD(0xB0, 0x07),
+	_INIT_DCS_CMD(0xB1, 0x00),
+	_INIT_DCS_CMD(0xB2, 0x02),
+	_INIT_DCS_CMD(0xB3, 0x0F),
+	_INIT_DCS_CMD(0xB4, 0x25),
+	_INIT_DCS_CMD(0xB5, 0x39),
+	_INIT_DCS_CMD(0xB6, 0x4E),
+	_INIT_DCS_CMD(0xB7, 0x72),
+	_INIT_DCS_CMD(0xB8, 0x97),
+	_INIT_DCS_CMD(0xB9, 0xDC),
+	_INIT_DCS_CMD(0xBA, 0x22),
+	_INIT_DCS_CMD(0xBB, 0xA4),
+	_INIT_DCS_CMD(0xBC, 0x2B),
+	_INIT_DCS_CMD(0xBD, 0x2F),
+	_INIT_DCS_CMD(0xBE, 0xA9),
+	_INIT_DCS_CMD(0xBF, 0x25),
+	_INIT_DCS_CMD(0xC0, 0x61),
+	_INIT_DCS_CMD(0xC1, 0x97),
+	_INIT_DCS_CMD(0xC2, 0xB2),
+	_INIT_DCS_CMD(0xC3, 0xCD),
+	_INIT_DCS_CMD(0xC4, 0xD9),
+	_INIT_DCS_CMD(0xC5, 0xE7),
+	_INIT_DCS_CMD(0xC6, 0xF4),
+	_INIT_DCS_CMD(0xC7, 0xFA),
+	_INIT_DCS_CMD(0xC8, 0xFC),
+	_INIT_DCS_CMD(0xC9, 0x00),
+	_INIT_DCS_CMD(0xCA, 0x00),
+	_INIT_DCS_CMD(0xCB, 0x16),
+	_INIT_DCS_CMD(0xCC, 0xAF),
+	_INIT_DCS_CMD(0xCD, 0xFF),
+	_INIT_DCS_CMD(0xCE, 0xFF),
+	_INIT_DCS_CMD(0xB0, 0x08),
+	_INIT_DCS_CMD(0xB1, 0x04),
+	_INIT_DCS_CMD(0xB2, 0x05),
+	_INIT_DCS_CMD(0xB3, 0x11),
+	_INIT_DCS_CMD(0xB4, 0x24),
+	_INIT_DCS_CMD(0xB5, 0x39),
+	_INIT_DCS_CMD(0xB6, 0x4F),
+	_INIT_DCS_CMD(0xB7, 0x72),
+	_INIT_DCS_CMD(0xB8, 0x98),
+	_INIT_DCS_CMD(0xB9, 0xDC),
+	_INIT_DCS_CMD(0xBA, 0x23),
+	_INIT_DCS_CMD(0xBB, 0xA6),
+	_INIT_DCS_CMD(0xBC, 0x2C),
+	_INIT_DCS_CMD(0xBD, 0x30),
+	_INIT_DCS_CMD(0xBE, 0xAA),
+	_INIT_DCS_CMD(0xBF, 0x26),
+	_INIT_DCS_CMD(0xC0, 0x62),
+	_INIT_DCS_CMD(0xC1, 0x9B),
+	_INIT_DCS_CMD(0xC2, 0xB5),
+	_INIT_DCS_CMD(0xC3, 0xCF),
+	_INIT_DCS_CMD(0xC4, 0xDB),
+	_INIT_DCS_CMD(0xC5, 0xE8),
+	_INIT_DCS_CMD(0xC6, 0xF5),
+	_INIT_DCS_CMD(0xC7, 0xFA),
+	_INIT_DCS_CMD(0xC8, 0xFC),
+	_INIT_DCS_CMD(0xC9, 0x00),
+	_INIT_DCS_CMD(0xCA, 0x00),
+	_INIT_DCS_CMD(0xCB, 0x16),
+	_INIT_DCS_CMD(0xCC, 0xAF),
+	_INIT_DCS_CMD(0xCD, 0xFF),
+	_INIT_DCS_CMD(0xCE, 0xFF),
+	_INIT_DCS_CMD(0xB0, 0x09),
+	_INIT_DCS_CMD(0xB1, 0x04),
+	_INIT_DCS_CMD(0xB2, 0x02),
+	_INIT_DCS_CMD(0xB3, 0x16),
+	_INIT_DCS_CMD(0xB4, 0x24),
+	_INIT_DCS_CMD(0xB5, 0x3B),
+	_INIT_DCS_CMD(0xB6, 0x4F),
+	_INIT_DCS_CMD(0xB7, 0x73),
+	_INIT_DCS_CMD(0xB8, 0x99),
+	_INIT_DCS_CMD(0xB9, 0xE0),
+	_INIT_DCS_CMD(0xBA, 0x26),
+	_INIT_DCS_CMD(0xBB, 0xAD),
+	_INIT_DCS_CMD(0xBC, 0x36),
+	_INIT_DCS_CMD(0xBD, 0x3A),
+	_INIT_DCS_CMD(0xBE, 0xAE),
+	_INIT_DCS_CMD(0xBF, 0x2A),
+	_INIT_DCS_CMD(0xC0, 0x66),
+	_INIT_DCS_CMD(0xC1, 0x9E),
+	_INIT_DCS_CMD(0xC2, 0xB8),
+	_INIT_DCS_CMD(0xC3, 0xD1),
+	_INIT_DCS_CMD(0xC4, 0xDD),
+	_INIT_DCS_CMD(0xC5, 0xE9),
+	_INIT_DCS_CMD(0xC6, 0xF6),
+	_INIT_DCS_CMD(0xC7, 0xFA),
+	_INIT_DCS_CMD(0xC8, 0xFC),
+	_INIT_DCS_CMD(0xC9, 0x00),
+	_INIT_DCS_CMD(0xCA, 0x00),
+	_INIT_DCS_CMD(0xCB, 0x16),
+	_INIT_DCS_CMD(0xCC, 0xAF),
+	_INIT_DCS_CMD(0xCD, 0xFF),
+	_INIT_DCS_CMD(0xCE, 0xFF),
+	_INIT_DCS_CMD(0xB0, 0x0A),
+	_INIT_DCS_CMD(0xB1, 0x00),
+	_INIT_DCS_CMD(0xB2, 0x02),
+	_INIT_DCS_CMD(0xB3, 0x0F),
+	_INIT_DCS_CMD(0xB4, 0x25),
+	_INIT_DCS_CMD(0xB5, 0x39),
+	_INIT_DCS_CMD(0xB6, 0x4E),
+	_INIT_DCS_CMD(0xB7, 0x72),
+	_INIT_DCS_CMD(0xB8, 0x97),
+	_INIT_DCS_CMD(0xB9, 0xDC),
+	_INIT_DCS_CMD(0xBA, 0x22),
+	_INIT_DCS_CMD(0xBB, 0xA4),
+	_INIT_DCS_CMD(0xBC, 0x2B),
+	_INIT_DCS_CMD(0xBD, 0x2F),
+	_INIT_DCS_CMD(0xBE, 0xA9),
+	_INIT_DCS_CMD(0xBF, 0x25),
+	_INIT_DCS_CMD(0xC0, 0x61),
+	_INIT_DCS_CMD(0xC1, 0x97),
+	_INIT_DCS_CMD(0xC2, 0xB2),
+	_INIT_DCS_CMD(0xC3, 0xCD),
+	_INIT_DCS_CMD(0xC4, 0xD9),
+	_INIT_DCS_CMD(0xC5, 0xE7),
+	_INIT_DCS_CMD(0xC6, 0xF4),
+	_INIT_DCS_CMD(0xC7, 0xFA),
+	_INIT_DCS_CMD(0xC8, 0xFC),
+	_INIT_DCS_CMD(0xC9, 0x00),
+	_INIT_DCS_CMD(0xCA, 0x00),
+	_INIT_DCS_CMD(0xCB, 0x16),
+	_INIT_DCS_CMD(0xCC, 0xAF),
+	_INIT_DCS_CMD(0xCD, 0xFF),
+	_INIT_DCS_CMD(0xCE, 0xFF),
+	_INIT_DCS_CMD(0xB0, 0x0B),
+	_INIT_DCS_CMD(0xB1, 0x04),
+	_INIT_DCS_CMD(0xB2, 0x05),
+	_INIT_DCS_CMD(0xB3, 0x11),
+	_INIT_DCS_CMD(0xB4, 0x24),
+	_INIT_DCS_CMD(0xB5, 0x39),
+	_INIT_DCS_CMD(0xB6, 0x4F),
+	_INIT_DCS_CMD(0xB7, 0x72),
+	_INIT_DCS_CMD(0xB8, 0x98),
+	_INIT_DCS_CMD(0xB9, 0xDC),
+	_INIT_DCS_CMD(0xBA, 0x23),
+	_INIT_DCS_CMD(0xBB, 0xA6),
+	_INIT_DCS_CMD(0xBC, 0x2C),
+	_INIT_DCS_CMD(0xBD, 0x30),
+	_INIT_DCS_CMD(0xBE, 0xAA),
+	_INIT_DCS_CMD(0xBF, 0x26),
+	_INIT_DCS_CMD(0xC0, 0x62),
+	_INIT_DCS_CMD(0xC1, 0x9B),
+	_INIT_DCS_CMD(0xC2, 0xB5),
+	_INIT_DCS_CMD(0xC3, 0xCF),
+	_INIT_DCS_CMD(0xC4, 0xDB),
+	_INIT_DCS_CMD(0xC5, 0xE8),
+	_INIT_DCS_CMD(0xC6, 0xF5),
+	_INIT_DCS_CMD(0xC7, 0xFA),
+	_INIT_DCS_CMD(0xC8, 0xFC),
+	_INIT_DCS_CMD(0xC9, 0x00),
+	_INIT_DCS_CMD(0xCA, 0x00),
+	_INIT_DCS_CMD(0xCB, 0x16),
+	_INIT_DCS_CMD(0xCC, 0xAF),
+	_INIT_DCS_CMD(0xCD, 0xFF),
+	_INIT_DCS_CMD(0xCE, 0xFF),
+	_INIT_DCS_CMD(0xB0, 0x0C),
+	_INIT_DCS_CMD(0xB1, 0x04),
+	_INIT_DCS_CMD(0xB2, 0x02),
+	_INIT_DCS_CMD(0xB3, 0x16),
+	_INIT_DCS_CMD(0xB4, 0x24),
+	_INIT_DCS_CMD(0xB5, 0x3B),
+	_INIT_DCS_CMD(0xB6, 0x4F),
+	_INIT_DCS_CMD(0xB7, 0x73),
+	_INIT_DCS_CMD(0xB8, 0x99),
+	_INIT_DCS_CMD(0xB9, 0xE0),
+	_INIT_DCS_CMD(0xBA, 0x26),
+	_INIT_DCS_CMD(0xBB, 0xAD),
+	_INIT_DCS_CMD(0xBC, 0x36),
+	_INIT_DCS_CMD(0xBD, 0x3A),
+	_INIT_DCS_CMD(0xBE, 0xAE),
+	_INIT_DCS_CMD(0xBF, 0x2A),
+	_INIT_DCS_CMD(0xC0, 0x66),
+	_INIT_DCS_CMD(0xC1, 0x9E),
+	_INIT_DCS_CMD(0xC2, 0xB8),
+	_INIT_DCS_CMD(0xC3, 0xD1),
+	_INIT_DCS_CMD(0xC4, 0xDD),
+	_INIT_DCS_CMD(0xC5, 0xE9),
+	_INIT_DCS_CMD(0xC6, 0xF6),
+	_INIT_DCS_CMD(0xC7, 0xFA),
+	_INIT_DCS_CMD(0xC8, 0xFC),
+	_INIT_DCS_CMD(0xC9, 0x00),
+	_INIT_DCS_CMD(0xCA, 0x00),
+	_INIT_DCS_CMD(0xCB, 0x16),
+	_INIT_DCS_CMD(0xCC, 0xAF),
+	_INIT_DCS_CMD(0xCD, 0xFF),
+	_INIT_DCS_CMD(0xCE, 0xFF),
+	_INIT_DCS_CMD(0xB0, 0x00),
+	_INIT_DCS_CMD(0xB3, 0x08),
+	_INIT_DCS_CMD(0xB0, 0x04),
+	_INIT_DCS_CMD(0xB8, 0x68),
+	_INIT_DELAY_CMD(150),
+	{},
+};
+
+static inline struct boe_panel *to_boe_panel(struct drm_panel *panel)
+{
+	return container_of(panel, struct boe_panel, base);
+}
+
+static int boe_panel_init(struct boe_panel *boe)
+{
+	struct mipi_dsi_device *dsi = boe->dsi;
+	struct drm_panel *panel = &boe->base;
+	int err, i;
+
+	if (boe->desc->init_cmds) {
+		const struct panel_init_cmd *init_cmds = boe->desc->init_cmds;
+
+		for (i = 0; init_cmds[i].len != 0; i++) {
+			const struct panel_init_cmd *cmd = &init_cmds[i];
+
+			switch (cmd->type) {
+			case DELAY_CMD:
+				msleep(cmd->data[0]);
+				err = 0;
+				break;
+
+			case INIT_DCS_CMD:
+				err = mipi_dsi_dcs_write(dsi, cmd->data[0],
+							 cmd->len <= 1 ? NULL :
+							 &cmd->data[1],
+							 cmd->len - 1);
+				break;
+			}
+
+			if (err < 0) {
+				dev_err(panel->dev,
+					"failed to write command %u\n", i);
+				return err;
+			}
+		}
+	}
+	return 0;
+}
+
+static int boe_panel_off(struct boe_panel *boe)
+{
+	struct mipi_dsi_device *dsi = boe->dsi;
+	int ret;
+
+	dsi->mode_flags &= ~MIPI_DSI_MODE_LPM;
+
+	ret = mipi_dsi_dcs_enter_sleep_mode(dsi);
+	if (ret < 0)
+		return ret;
+
+	return 0;
+}
+
+static int boe_panel_disable(struct drm_panel *panel)
+{
+	struct boe_panel *boe = to_boe_panel(panel);
+
+	if (!boe->enabled)
+		return 0;
+
+	backlight_disable(boe->backlight);
+
+	boe->enabled = false;
+
+	return 0;
+}
+
+static int boe_panel_unprepare(struct drm_panel *panel)
+{
+	struct boe_panel *boe = to_boe_panel(panel);
+	int ret;
+
+	if (!boe->prepared)
+		return 0;
+
+	ret = boe_panel_off(boe);
+	if (ret < 0) {
+		dev_err(panel->dev, "failed to set panel off: %d\n", ret);
+		return ret;
+	}
+
+	msleep(150);
+	if (boe->enable_gpio)
+		gpiod_set_value(boe->enable_gpio, 0);
+	usleep_range(500, 1000);
+	regulator_disable(boe->avee);
+	regulator_disable(boe->avdd);
+	usleep_range(5000, 7000);
+	regulator_disable(boe->pp1800);
+
+	boe->prepared = false;
+
+	return 0;
+}
+
+static int boe_panel_prepare(struct drm_panel *panel)
+{
+	struct boe_panel *boe = to_boe_panel(panel);
+	int ret;
+
+	if (boe->prepared)
+		return 0;
+
+	if (boe->enable_gpio) {
+		gpiod_set_value(boe->enable_gpio, 0);
+		usleep_range(1000, 1500);
+	}
+
+	ret = regulator_enable(boe->pp1800);
+	if (ret < 0)
+		return ret;
+
+	usleep_range(3000, 5000);
+
+	ret = regulator_enable(boe->avdd);
+	if (ret < 0)
+		goto poweroff1v8;
+	ret = regulator_enable(boe->avee);
+	if (ret < 0)
+		goto poweroffavdd;
+
+	msleep(100);
+
+	if (boe->enable_gpio) {
+		gpiod_set_value(boe->enable_gpio, 1);
+		usleep_range(10000, 12000);
+	}
+
+	ret = boe_panel_init(boe);
+	if (ret < 0) {
+		dev_err(panel->dev, "failed to init panel: %d\n", ret);
+		goto poweroff;
+	}
+
+	boe->prepared = true;
+
+	return 0;
+
+poweroff:
+	regulator_disable(boe->avee);
+poweroffavdd:
+	regulator_disable(boe->avdd);
+poweroff1v8:
+	usleep_range(5000, 7000);
+	regulator_disable(boe->pp1800);
+	if (boe->enable_gpio)
+		gpiod_set_value(boe->enable_gpio, 0);
+	return ret;
+}
+
+static int boe_panel_enable(struct drm_panel *panel)
+{
+	struct boe_panel *boe = to_boe_panel(panel);
+	int ret;
+
+	if (boe->enabled)
+		return 0;
+
+	ret = backlight_enable(boe->backlight);
+	if (ret) {
+		dev_err(panel->dev, "Failed to enable backlight %d\n",
+			ret);
+		return ret;
+	}
+
+	boe->enabled = true;
+
+	return 0;
+}
+
+static const struct drm_display_mode boe_default_mode = {
+	.clock = 159425,
+	.hdisplay = 1200,
+	.hsync_start = 1200 + 100,
+	.hsync_end = 1200 + 100 + 40,
+	.htotal = 1200 + 100 + 40 + 24,
+	.vdisplay = 1920,
+	.vsync_start = 1920 + 10,
+	.vsync_end = 1920 + 10 + 14,
+	.vtotal = 1920 + 10 + 14 + 4,
+	.vrefresh = 60,
+};
+
+static const struct panel_desc boe_tv101wum_nl6_desc = {
+	.modes = &boe_default_mode,
+	.bpc = 8,
+	.size = {
+		.width = 135,
+		.height = 216,
+	},
+	.lanes = 4,
+	.format = MIPI_DSI_FMT_RGB888,
+	.mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
+		      MIPI_DSI_MODE_LPM,
+	.init_cmds = boe_init_cmd,
+};
+
+static int boe_panel_get_modes(struct drm_panel *panel)
+{
+	struct boe_panel *boe = to_boe_panel(panel);
+	const struct drm_display_mode *m = boe->desc->modes;
+	struct drm_display_mode *mode;
+
+	mode = drm_mode_duplicate(panel->drm, m);
+	if (!mode) {
+		dev_err(panel->dev, "failed to add mode %ux%u@%u\n",
+			m->hdisplay, m->vdisplay, m->vrefresh);
+		return -ENOMEM;
+	}
+
+	mode->type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED;
+	drm_mode_set_name(mode);
+	drm_mode_probed_add(panel->connector, mode);
+
+	panel->connector->display_info.width_mm = boe->desc->size.width;
+	panel->connector->display_info.height_mm = boe->desc->size.height;
+	panel->connector->display_info.bpc = boe->desc->bpc;
+
+	return 1;
+}
+
+static const struct drm_panel_funcs boe_panel_funcs = {
+	.disable = boe_panel_disable,
+	.unprepare = boe_panel_unprepare,
+	.prepare = boe_panel_prepare,
+	.enable = boe_panel_enable,
+	.get_modes = boe_panel_get_modes,
+};
+
+static int boe_panel_add(struct boe_panel *boe)
+{
+	struct device *dev = &boe->dsi->dev;
+
+	boe->avdd = devm_regulator_get(dev, "avdd");
+	if (IS_ERR(boe->avdd))
+		return PTR_ERR(boe->avdd);
+
+	boe->avee = devm_regulator_get(dev, "avee");
+	if (IS_ERR(boe->avee))
+		return PTR_ERR(boe->avee);
+
+	boe->pp1800 = devm_regulator_get(dev, "pp1800");
+	if (IS_ERR(boe->pp1800))
+		return PTR_ERR(boe->pp1800);
+
+	boe->enable_gpio = devm_gpiod_get(dev, "enable", GPIOD_OUT_LOW);
+	if (IS_ERR(boe->enable_gpio)) {
+		dev_err(dev, "cannot get reset-gpios %ld\n",
+			PTR_ERR(boe->enable_gpio));
+		return PTR_ERR(boe->enable_gpio);
+	}
+
+	gpiod_set_value(boe->enable_gpio, 0);
+
+	boe->backlight = devm_of_find_backlight(dev);
+	if (IS_ERR(boe->backlight))
+		return PTR_ERR(boe->backlight);
+
+	drm_panel_init(&boe->base);
+	boe->base.funcs = &boe_panel_funcs;
+	boe->base.dev = &boe->dsi->dev;
+
+	return drm_panel_add(&boe->base);
+}
+
+static int boe_panel_probe(struct mipi_dsi_device *dsi)
+{
+	struct boe_panel *boe;
+	int ret;
+	const struct panel_desc *desc;
+
+	boe = devm_kzalloc(&dsi->dev, sizeof(*boe), GFP_KERNEL);
+	if (!boe)
+		return -ENOMEM;
+
+	desc = of_device_get_match_data(&dsi->dev);
+	dsi->lanes = desc->lanes;
+	dsi->format = desc->format;
+	dsi->mode_flags = desc->mode_flags;
+	boe->desc = desc;
+	boe->dsi = dsi;
+	ret = boe_panel_add(boe);
+	if (ret < 0)
+		return ret;
+
+	mipi_dsi_set_drvdata(dsi, boe);
+
+	return mipi_dsi_attach(dsi);
+}
+
+static int boe_panel_remove(struct mipi_dsi_device *dsi)
+{
+	struct boe_panel *boe = mipi_dsi_get_drvdata(dsi);
+	int ret;
+
+	ret = boe_panel_disable(&boe->base);
+	if (ret < 0)
+		dev_err(&dsi->dev, "failed to disable panel: %d\n", ret);
+
+	ret = mipi_dsi_detach(dsi);
+	if (ret < 0)
+		dev_err(&dsi->dev, "failed to detach from DSI host: %d\n", ret);
+
+	if (boe->base.dev)
+		drm_panel_remove(&boe->base);
+
+	return 0;
+}
+
+static void boe_panel_shutdown(struct mipi_dsi_device *dsi)
+{
+	struct boe_panel *boe = mipi_dsi_get_drvdata(dsi);
+
+	boe_panel_disable(&boe->base);
+}
+
+static const struct of_device_id boe_of_match[] = {
+	{ .compatible = "boe,tv101wum-nl6",
+	  .data = &boe_tv101wum_nl6_desc
+	},
+	{ /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, boe_of_match);
+
+static struct mipi_dsi_driver boe_panel_driver = {
+	.driver = {
+		.name = "panel-boe-tv101wum-nl6",
+		.of_match_table = boe_of_match,
+	},
+	.probe = boe_panel_probe,
+	.remove = boe_panel_remove,
+	.shutdown = boe_panel_shutdown,
+};
+module_mipi_dsi_driver(boe_panel_driver);
+
+MODULE_AUTHOR("Jitao Shi <jitao.shi@mediatek.com>");
+MODULE_DESCRIPTION("BOE tv101wum-nl6 1200x1920 video mode panel driver");
+MODULE_LICENSE("GPL v2");
-- 
2.21.0


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