* [PATCH v4 0/5] EHL port programming
@ 2019-07-03 23:37 Matt Roper
2019-07-03 23:37 ` [PATCH v4 1/5] drm/i915/gen11: Start distinguishing 'phy' from 'port' Matt Roper
` (12 more replies)
0 siblings, 13 replies; 33+ messages in thread
From: Matt Roper @ 2019-07-03 23:37 UTC (permalink / raw)
To: intel-gfx
Previous series revisions were here:
v3: https://lists.freedesktop.org/archives/intel-gfx/2019-June/203287.html
v1/2: https://lists.freedesktop.org/archives/intel-gfx/2019-June/202776.html
Only two patches from the previous series have yet to land; this
revision splits up the first of those into four separate patches to ease
the review process a bit.
This revision also updates a handful of combo PHY registers to use the
new namespace that were missed in the previous iteration and caught by
Jose.
As before, this series doesn't even try to touch the TC code (aside from
the type check function). EHL has no combo PHYs, so it's probably
better to wait until TGL support lands in the tree before tackling that
to avoid causing unnecessary conflicts. Even patch #4 of this series
may want to wait until TGL lands before being merged.
Cc: José Roberto de Souza <jose.souza@intel.com>
Matt Roper (5):
drm/i915/gen11: Start distinguishing 'phy' from 'port'
drm/i915/gen11: Program DPCLKA_CFGCR0_ICL according to PHY
drm/i915/gen11: Convert combo PHY logic to use new 'enum phy'
namespace
drm/i915: Transition port type checks to phy checks
drm/i915/ehl: Enable DDI-D
drivers/gpu/drm/i915/display/icl_dsi.c | 136 ++++++++---------
drivers/gpu/drm/i915/display/intel_bios.c | 4 +-
.../gpu/drm/i915/display/intel_combo_phy.c | 143 +++++++++---------
.../gpu/drm/i915/display/intel_combo_phy.h | 3 +-
drivers/gpu/drm/i915/display/intel_ddi.c | 130 +++++++++-------
drivers/gpu/drm/i915/display/intel_display.c | 39 +++--
drivers/gpu/drm/i915/display/intel_display.h | 20 +++
.../drm/i915/display/intel_display_power.c | 20 +--
drivers/gpu/drm/i915/display/intel_dp.c | 15 +-
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 11 +-
drivers/gpu/drm/i915/display/intel_dsi.h | 12 +-
drivers/gpu/drm/i915/i915_reg.h | 86 ++++++-----
drivers/gpu/drm/i915/intel_drv.h | 4 +-
13 files changed, 348 insertions(+), 275 deletions(-)
--
2.17.2
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 33+ messages in thread
* [PATCH v4 1/5] drm/i915/gen11: Start distinguishing 'phy' from 'port'
2019-07-03 23:37 [PATCH v4 0/5] EHL port programming Matt Roper
@ 2019-07-03 23:37 ` Matt Roper
2019-07-04 9:18 ` Ville Syrjälä
2019-07-08 23:59 ` Souza, Jose
2019-07-03 23:37 ` [PATCH v4 2/5] drm/i915/gen11: Program DPCLKA_CFGCR0_ICL according to PHY Matt Roper
` (11 subsequent siblings)
12 siblings, 2 replies; 33+ messages in thread
From: Matt Roper @ 2019-07-03 23:37 UTC (permalink / raw)
To: intel-gfx; +Cc: Jani Nikula, Lucas De Marchi
Our past DDI-based Intel platforms have had a fixed DDI<->PHY mapping.
Because of this, both the bspec documentation and our i915 code has used
the term "port" when talking about either DDI's or PHY's; it was always
easy to tell what terms like "Port A" were referring to from the
context.
Unfortunately this is starting to break down now that EHL allows PHY-A
to be driven by either DDI-A or DDI-D. Is a setup with DDI-D driving
PHY-A considered "Port A" or "Port D?" The answer depends on which
register we're working with, and even the bspec doesn't do a great job
of clarifying this.
Let's try to be more explicit about whether we're talking about the DDI
or the PHY on gen11+ by using 'port' to refer to the DDI and creating a
new 'enum phy' namespace to refer to the PHY in use.
This patch just adds the new PHY namespace, new phy-based versions of
intel_port_is_*(), and a helper to convert a port to a PHY.
Transitioning various areas of the code over to using the PHY namespace
will be done in subsequent patches to make review easier. We'll remove
the intel_port_is_*() functions at the end of the series when we
transition all callers over to using the PHY-based versions.
v2:
- Convert a few more 'port' uses to 'phy.' (Sparse)
v3:
- Switch DDI_CLK_SEL() back to 'port.' (Jose)
- Add a code comment clarifying why DPCLKA_CFGCR0_ICL needs to use PHY
for its bit definitions, even though the register description is
given in terms of DDI.
- To avoid confusion, switch CNL's DPCLKA_CFGCR0 defines back to using
port and create separate ICL+ definitions that work in terms of PHY.
v4:
- Rebase and resolve conflicts with Imre's TC series.
- This patch now just adds the namespace and a few convenience
functions; the important changes are now split out into separate
patches to make review easier.
Suggested-by: Ville Syrjala <ville.syrjala@linux.intel.com>
Cc: José Roberto de Souza <jose.souza@intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 32 +++++++++++++++++++-
drivers/gpu/drm/i915/display/intel_display.h | 16 ++++++++++
drivers/gpu/drm/i915/intel_drv.h | 2 ++
3 files changed, 49 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 919f5ac844c8..4a85abef93e7 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -6663,6 +6663,20 @@ bool intel_port_is_combophy(struct drm_i915_private *dev_priv, enum port port)
return false;
}
+bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy phy)
+{
+ if (phy == PHY_NONE)
+ return false;
+
+ if (IS_ELKHARTLAKE(dev_priv))
+ return phy <= PHY_C;
+
+ if (INTEL_GEN(dev_priv) >= 11)
+ return phy <= PHY_B;
+
+ return false;
+}
+
bool intel_port_is_tc(struct drm_i915_private *dev_priv, enum port port)
{
if (INTEL_GEN(dev_priv) >= 11 && !IS_ELKHARTLAKE(dev_priv))
@@ -6671,9 +6685,25 @@ bool intel_port_is_tc(struct drm_i915_private *dev_priv, enum port port)
return false;
}
+bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy)
+{
+ if (INTEL_GEN(dev_priv) >= 11 && !IS_ELKHARTLAKE(dev_priv))
+ return phy >= PHY_C && phy <= PHY_F;
+
+ return false;
+}
+
+enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port)
+{
+ if (IS_ELKHARTLAKE(i915) && port == PORT_D)
+ return PHY_A;
+
+ return (enum phy)port;
+}
+
enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv, enum port port)
{
- if (!intel_port_is_tc(dev_priv, port))
+ if (!intel_phy_is_tc(dev_priv, intel_port_to_phy(dev_priv, port)))
return PORT_TC_NONE;
return port - PORT_C;
diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
index d296556ed82e..d53285fb883f 100644
--- a/drivers/gpu/drm/i915/display/intel_display.h
+++ b/drivers/gpu/drm/i915/display/intel_display.h
@@ -228,6 +228,21 @@ struct intel_link_m_n {
u32 link_n;
};
+enum phy {
+ PHY_NONE = -1,
+
+ PHY_A = 0,
+ PHY_B,
+ PHY_C,
+ PHY_D,
+ PHY_E,
+ PHY_F,
+
+ I915_MAX_PHYS
+};
+
+#define phy_name(a) ((a) + 'A')
+
#define for_each_pipe(__dev_priv, __p) \
for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++)
@@ -356,5 +371,6 @@ void lpt_disable_clkout_dp(struct drm_i915_private *dev_priv);
u32 intel_plane_fb_max_stride(struct drm_i915_private *dev_priv,
u32 pixel_format, u64 modifier);
bool intel_plane_can_remap(const struct intel_plane_state *plane_state);
+enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port);
#endif
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 24c63ed45c6f..815c26c0b98c 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1493,7 +1493,9 @@ void intel_encoder_destroy(struct drm_encoder *encoder);
struct drm_display_mode *
intel_encoder_current_mode(struct intel_encoder *encoder);
bool intel_port_is_combophy(struct drm_i915_private *dev_priv, enum port port);
+bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy phy);
bool intel_port_is_tc(struct drm_i915_private *dev_priv, enum port port);
+bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy);
enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv,
enum port port);
int intel_get_pipe_from_crtc_id_ioctl(struct drm_device *dev, void *data,
--
2.17.2
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 33+ messages in thread
* [PATCH v4 2/5] drm/i915/gen11: Program DPCLKA_CFGCR0_ICL according to PHY
2019-07-03 23:37 [PATCH v4 0/5] EHL port programming Matt Roper
2019-07-03 23:37 ` [PATCH v4 1/5] drm/i915/gen11: Start distinguishing 'phy' from 'port' Matt Roper
@ 2019-07-03 23:37 ` Matt Roper
2019-07-04 1:06 ` [PATCH v5 " Matt Roper
2019-07-03 23:37 ` [PATCH v4 3/5] drm/i915/gen11: Convert combo PHY logic to use new 'enum phy' namespace Matt Roper
` (10 subsequent siblings)
12 siblings, 1 reply; 33+ messages in thread
From: Matt Roper @ 2019-07-03 23:37 UTC (permalink / raw)
To: intel-gfx
Although the register name implies that it operates on DDI's,
DPCLKA_CFGCR0_ICL actually needs to be programmed according to the PHY
that's in use. I.e., when using EHL's DDI-D on combo PHY A, the bits
described as "port A" in the bspec are what we need to set. The bspec
clarifies:
"[For EHL] DDID clock tied to DDIA clock, so DPCLKA_CFGCR0 DDIA
Clock Select chooses the PLL for both DDIA and DDID and drives
port A in all cases."
Also, since the CNL DPCLKA_CFGCR0 bit defines are still port-based, we
create separate ICL-specific defines that accept the PHY rather than
trying to share the same bit definitions between CNL and ICL.
Bspec: 33148
Cc: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/i915/display/icl_dsi.c | 17 +++++++----
drivers/gpu/drm/i915/display/intel_ddi.c | 36 ++++++++++++++++--------
drivers/gpu/drm/i915/i915_reg.h | 12 +++++---
3 files changed, 44 insertions(+), 21 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
index b8673debf932..f574af62888c 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -560,11 +560,13 @@ static void gen11_dsi_gate_clocks(struct intel_encoder *encoder)
struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
u32 tmp;
enum port port;
+ enum phy phy;
mutex_lock(&dev_priv->dpll_lock);
tmp = I915_READ(DPCLKA_CFGCR0_ICL);
for_each_dsi_port(port, intel_dsi->ports) {
- tmp |= DPCLKA_CFGCR0_DDI_CLK_OFF(port);
+ phy = intel_port_to_phy(dev_priv, port);
+ tmp |= ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
}
I915_WRITE(DPCLKA_CFGCR0_ICL, tmp);
@@ -577,11 +579,13 @@ static void gen11_dsi_ungate_clocks(struct intel_encoder *encoder)
struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
u32 tmp;
enum port port;
+ enum phy phy;
mutex_lock(&dev_priv->dpll_lock);
tmp = I915_READ(DPCLKA_CFGCR0_ICL);
for_each_dsi_port(port, intel_dsi->ports) {
- tmp &= ~DPCLKA_CFGCR0_DDI_CLK_OFF(port);
+ phy = intel_port_to_phy(dev_priv, port);
+ tmp &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
}
I915_WRITE(DPCLKA_CFGCR0_ICL, tmp);
@@ -595,19 +599,22 @@ static void gen11_dsi_map_pll(struct intel_encoder *encoder,
struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
struct intel_shared_dpll *pll = crtc_state->shared_dpll;
enum port port;
+ enum phy phy;
u32 val;
mutex_lock(&dev_priv->dpll_lock);
val = I915_READ(DPCLKA_CFGCR0_ICL);
for_each_dsi_port(port, intel_dsi->ports) {
- val &= ~DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
- val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, port);
+ phy = intel_port_to_phy(dev_priv, port);
+ val &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
+ val |= ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy);
}
I915_WRITE(DPCLKA_CFGCR0_ICL, val);
for_each_dsi_port(port, intel_dsi->ports) {
- val &= ~DPCLKA_CFGCR0_DDI_CLK_OFF(port);
+ phy = intel_port_to_phy(dev_priv, port);
+ val &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
}
I915_WRITE(DPCLKA_CFGCR0_ICL, val);
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index a4172595c8d8..a40a53527d99 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -2747,22 +2747,32 @@ static void icl_map_plls_to_ports(struct intel_encoder *encoder,
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
struct intel_shared_dpll *pll = crtc_state->shared_dpll;
- enum port port = encoder->port;
+ enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
u32 val;
mutex_lock(&dev_priv->dpll_lock);
val = I915_READ(DPCLKA_CFGCR0_ICL);
- WARN_ON((val & icl_dpclka_cfgcr0_clk_off(dev_priv, port)) == 0);
+ WARN_ON((val & icl_dpclka_cfgcr0_clk_off(dev_priv, phy)) == 0);
- if (intel_port_is_combophy(dev_priv, port)) {
- val &= ~DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
- val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, port);
+ if (intel_phy_is_combo(dev_priv, phy)) {
+ /*
+ * Even though this register references DDIs, note that we
+ * want to pass the PHY rather than the port (DDI). For
+ * ICL, port=phy in all cases so it doesn't matter, but for
+ * EHL the bspec notes the following:
+ *
+ * "DDID clock tied to DDIA clock, so DPCLKA_CFGCR0 DDIA
+ * Clock Select chooses the PLL for both DDIA and DDID and
+ * drives port A in all cases."
+ */
+ val &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
+ val |= ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy);
I915_WRITE(DPCLKA_CFGCR0_ICL, val);
POSTING_READ(DPCLKA_CFGCR0_ICL);
}
- val &= ~icl_dpclka_cfgcr0_clk_off(dev_priv, port);
+ val &= ~icl_dpclka_cfgcr0_clk_off(dev_priv, phy);
I915_WRITE(DPCLKA_CFGCR0_ICL, val);
mutex_unlock(&dev_priv->dpll_lock);
@@ -2771,13 +2781,13 @@ static void icl_map_plls_to_ports(struct intel_encoder *encoder,
static void icl_unmap_plls_to_ports(struct intel_encoder *encoder)
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
- enum port port = encoder->port;
+ enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
u32 val;
mutex_lock(&dev_priv->dpll_lock);
val = I915_READ(DPCLKA_CFGCR0_ICL);
- val |= icl_dpclka_cfgcr0_clk_off(dev_priv, port);
+ val |= icl_dpclka_cfgcr0_clk_off(dev_priv, phy);
I915_WRITE(DPCLKA_CFGCR0_ICL, val);
mutex_unlock(&dev_priv->dpll_lock);
@@ -2838,9 +2848,11 @@ void icl_sanitize_encoder_pll_mapping(struct intel_encoder *encoder)
val = I915_READ(DPCLKA_CFGCR0_ICL);
for_each_port_masked(port, port_mask) {
+ enum phy phy = intel_port_to_phy(dev_priv, port);
+
bool ddi_clk_ungated = !(val &
icl_dpclka_cfgcr0_clk_off(dev_priv,
- port));
+ phy));
if (ddi_clk_needed == ddi_clk_ungated)
continue;
@@ -2852,9 +2864,9 @@ void icl_sanitize_encoder_pll_mapping(struct intel_encoder *encoder)
if (WARN_ON(ddi_clk_needed))
continue;
- DRM_NOTE("Port %c is disabled/in DSI mode with an ungated DDI clock, gate it\n",
- port_name(port));
- val |= icl_dpclka_cfgcr0_clk_off(dev_priv, port);
+ DRM_NOTE("PHY %c is disabled/in DSI mode with an ungated DDI clock, gate it\n",
+ phy_name(port));
+ val |= icl_dpclka_cfgcr0_clk_off(dev_priv, phy);
I915_WRITE(DPCLKA_CFGCR0_ICL, val);
}
}
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index c814cc1b3ae5..c9e2e09b6f01 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -9680,17 +9680,21 @@ enum skl_power_gate {
* CNL Clocks
*/
#define DPCLKA_CFGCR0 _MMIO(0x6C200)
-#define DPCLKA_CFGCR0_ICL _MMIO(0x164280)
#define DPCLKA_CFGCR0_DDI_CLK_OFF(port) (1 << ((port) == PORT_F ? 23 : \
(port) + 10))
-#define ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(port) (1 << ((port) + 10))
-#define ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port) (1 << ((tc_port) == PORT_TC4 ? \
- 21 : (tc_port) + 12))
#define DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port) ((port) == PORT_F ? 21 : \
(port) * 2)
#define DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port) (3 << DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port))
#define DPCLKA_CFGCR0_DDI_CLK_SEL(pll, port) ((pll) << DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port))
+#define DPCLKA_CFGCR0_ICL _MMIO(0x164280)
+#define ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy) (1 << _PICK(phy, 10, 11, 24))
+#define ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port) (1 << ((tc_port) == PORT_TC4 ? \
+ 21 : (tc_port) + 12))
+#define ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy) ((phy) * 2)
+#define ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy) (3 << ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy))
+#define ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll, phy) ((pll) << ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy))
+
/* CNL PLL */
#define DPLL0_ENABLE 0x46010
#define DPLL1_ENABLE 0x46014
--
2.17.2
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 33+ messages in thread
* [PATCH v4 3/5] drm/i915/gen11: Convert combo PHY logic to use new 'enum phy' namespace
2019-07-03 23:37 [PATCH v4 0/5] EHL port programming Matt Roper
2019-07-03 23:37 ` [PATCH v4 1/5] drm/i915/gen11: Start distinguishing 'phy' from 'port' Matt Roper
2019-07-03 23:37 ` [PATCH v4 2/5] drm/i915/gen11: Program DPCLKA_CFGCR0_ICL according to PHY Matt Roper
@ 2019-07-03 23:37 ` Matt Roper
2019-07-04 9:39 ` Ville Syrjälä
2019-07-09 0:41 ` Souza, Jose
2019-07-03 23:37 ` [PATCH v4 4/5] drm/i915: Transition port type checks to phy checks Matt Roper
` (9 subsequent siblings)
12 siblings, 2 replies; 33+ messages in thread
From: Matt Roper @ 2019-07-03 23:37 UTC (permalink / raw)
To: intel-gfx
Convert the code that operates directly on gen11 combo PHY's to use the
new namespace. Combo PHY registers are those named "ICL_PORT_*" plus
ICL_DPHY_CHKN.
Note that a lot of the PHY programming happens in the MIPI DSI code.
For clarity I've added a for_each_dsi_phy() to loop over the phys used
by DSI. Since DSI always uses A & B on gen11, port=phy in all cases so
it doesn't actually matter which form we use in the DSI code. I've used
the phy iterator in code that's explicitly working with the combo PHY,
but left the rest of the DSI code using the port iterator and namespace
to minimize patch deltas. We can switch the rest of the DSI code over
to use phy terminology later if this winds up being too confusing.
Cc: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/i915/display/icl_dsi.c | 127 ++++++++--------
.../gpu/drm/i915/display/intel_combo_phy.c | 143 +++++++++---------
.../gpu/drm/i915/display/intel_combo_phy.h | 3 +-
drivers/gpu/drm/i915/display/intel_ddi.c | 45 +++---
drivers/gpu/drm/i915/display/intel_display.h | 4 +
.../drm/i915/display/intel_display_power.c | 16 +-
drivers/gpu/drm/i915/display/intel_dsi.h | 12 +-
drivers/gpu/drm/i915/i915_reg.h | 74 ++++-----
8 files changed, 213 insertions(+), 211 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
index f574af62888c..575196f892c2 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -202,63 +202,62 @@ static void dsi_program_swing_and_deemphasis(struct intel_encoder *encoder)
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
- enum port port;
+ enum phy phy;
u32 tmp;
int lane;
- for_each_dsi_port(port, intel_dsi->ports) {
-
+ for_each_dsi_phy(phy, intel_dsi->phys) {
/*
* Program voltage swing and pre-emphasis level values as per
* table in BSPEC under DDI buffer programing
*/
- tmp = I915_READ(ICL_PORT_TX_DW5_LN0(port));
+ tmp = I915_READ(ICL_PORT_TX_DW5_LN0(phy));
tmp &= ~(SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK);
tmp |= SCALING_MODE_SEL(0x2);
tmp |= TAP2_DISABLE | TAP3_DISABLE;
tmp |= RTERM_SELECT(0x6);
- I915_WRITE(ICL_PORT_TX_DW5_GRP(port), tmp);
+ I915_WRITE(ICL_PORT_TX_DW5_GRP(phy), tmp);
- tmp = I915_READ(ICL_PORT_TX_DW5_AUX(port));
+ tmp = I915_READ(ICL_PORT_TX_DW5_AUX(phy));
tmp &= ~(SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK);
tmp |= SCALING_MODE_SEL(0x2);
tmp |= TAP2_DISABLE | TAP3_DISABLE;
tmp |= RTERM_SELECT(0x6);
- I915_WRITE(ICL_PORT_TX_DW5_AUX(port), tmp);
+ I915_WRITE(ICL_PORT_TX_DW5_AUX(phy), tmp);
- tmp = I915_READ(ICL_PORT_TX_DW2_LN0(port));
+ tmp = I915_READ(ICL_PORT_TX_DW2_LN0(phy));
tmp &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK |
RCOMP_SCALAR_MASK);
tmp |= SWING_SEL_UPPER(0x2);
tmp |= SWING_SEL_LOWER(0x2);
tmp |= RCOMP_SCALAR(0x98);
- I915_WRITE(ICL_PORT_TX_DW2_GRP(port), tmp);
+ I915_WRITE(ICL_PORT_TX_DW2_GRP(phy), tmp);
- tmp = I915_READ(ICL_PORT_TX_DW2_AUX(port));
+ tmp = I915_READ(ICL_PORT_TX_DW2_AUX(phy));
tmp &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK |
RCOMP_SCALAR_MASK);
tmp |= SWING_SEL_UPPER(0x2);
tmp |= SWING_SEL_LOWER(0x2);
tmp |= RCOMP_SCALAR(0x98);
- I915_WRITE(ICL_PORT_TX_DW2_AUX(port), tmp);
+ I915_WRITE(ICL_PORT_TX_DW2_AUX(phy), tmp);
- tmp = I915_READ(ICL_PORT_TX_DW4_AUX(port));
+ tmp = I915_READ(ICL_PORT_TX_DW4_AUX(phy));
tmp &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK |
CURSOR_COEFF_MASK);
tmp |= POST_CURSOR_1(0x0);
tmp |= POST_CURSOR_2(0x0);
tmp |= CURSOR_COEFF(0x3f);
- I915_WRITE(ICL_PORT_TX_DW4_AUX(port), tmp);
+ I915_WRITE(ICL_PORT_TX_DW4_AUX(phy), tmp);
for (lane = 0; lane <= 3; lane++) {
/* Bspec: must not use GRP register for write */
- tmp = I915_READ(ICL_PORT_TX_DW4_LN(lane, port));
+ tmp = I915_READ(ICL_PORT_TX_DW4_LN(lane, phy));
tmp &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK |
CURSOR_COEFF_MASK);
tmp |= POST_CURSOR_1(0x0);
tmp |= POST_CURSOR_2(0x0);
tmp |= CURSOR_COEFF(0x3f);
- I915_WRITE(ICL_PORT_TX_DW4_LN(lane, port), tmp);
+ I915_WRITE(ICL_PORT_TX_DW4_LN(lane, phy), tmp);
}
}
}
@@ -364,10 +363,10 @@ static void gen11_dsi_power_up_lanes(struct intel_encoder *encoder)
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
- enum port port;
+ enum phy phy;
- for_each_dsi_port(port, intel_dsi->ports)
- intel_combo_phy_power_up_lanes(dev_priv, port, true,
+ for_each_dsi_phy(phy, intel_dsi->phys)
+ intel_combo_phy_power_up_lanes(dev_priv, phy, true,
intel_dsi->lane_count, false);
}
@@ -375,46 +374,46 @@ static void gen11_dsi_config_phy_lanes_sequence(struct intel_encoder *encoder)
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
- enum port port;
+ enum phy phy;
u32 tmp;
int lane;
/* Step 4b(i) set loadgen select for transmit and aux lanes */
- for_each_dsi_port(port, intel_dsi->ports) {
- tmp = I915_READ(ICL_PORT_TX_DW4_AUX(port));
+ for_each_dsi_phy(phy, intel_dsi->phys) {
+ tmp = I915_READ(ICL_PORT_TX_DW4_AUX(phy));
tmp &= ~LOADGEN_SELECT;
- I915_WRITE(ICL_PORT_TX_DW4_AUX(port), tmp);
+ I915_WRITE(ICL_PORT_TX_DW4_AUX(phy), tmp);
for (lane = 0; lane <= 3; lane++) {
- tmp = I915_READ(ICL_PORT_TX_DW4_LN(lane, port));
+ tmp = I915_READ(ICL_PORT_TX_DW4_LN(lane, phy));
tmp &= ~LOADGEN_SELECT;
if (lane != 2)
tmp |= LOADGEN_SELECT;
- I915_WRITE(ICL_PORT_TX_DW4_LN(lane, port), tmp);
+ I915_WRITE(ICL_PORT_TX_DW4_LN(lane, phy), tmp);
}
}
/* Step 4b(ii) set latency optimization for transmit and aux lanes */
- for_each_dsi_port(port, intel_dsi->ports) {
- tmp = I915_READ(ICL_PORT_TX_DW2_AUX(port));
+ for_each_dsi_phy(phy, intel_dsi->phys) {
+ tmp = I915_READ(ICL_PORT_TX_DW2_AUX(phy));
tmp &= ~FRC_LATENCY_OPTIM_MASK;
tmp |= FRC_LATENCY_OPTIM_VAL(0x5);
- I915_WRITE(ICL_PORT_TX_DW2_AUX(port), tmp);
- tmp = I915_READ(ICL_PORT_TX_DW2_LN0(port));
+ I915_WRITE(ICL_PORT_TX_DW2_AUX(phy), tmp);
+ tmp = I915_READ(ICL_PORT_TX_DW2_LN0(phy));
tmp &= ~FRC_LATENCY_OPTIM_MASK;
tmp |= FRC_LATENCY_OPTIM_VAL(0x5);
- I915_WRITE(ICL_PORT_TX_DW2_GRP(port), tmp);
+ I915_WRITE(ICL_PORT_TX_DW2_GRP(phy), tmp);
/* For EHL set latency optimization for PCS_DW1 lanes */
if (IS_ELKHARTLAKE(dev_priv)) {
- tmp = I915_READ(ICL_PORT_PCS_DW1_AUX(port));
+ tmp = I915_READ(ICL_PORT_PCS_DW1_AUX(phy));
tmp &= ~LATENCY_OPTIM_MASK;
tmp |= LATENCY_OPTIM_VAL(0);
- I915_WRITE(ICL_PORT_PCS_DW1_AUX(port), tmp);
+ I915_WRITE(ICL_PORT_PCS_DW1_AUX(phy), tmp);
- tmp = I915_READ(ICL_PORT_PCS_DW1_LN0(port));
+ tmp = I915_READ(ICL_PORT_PCS_DW1_LN0(phy));
tmp &= ~LATENCY_OPTIM_MASK;
tmp |= LATENCY_OPTIM_VAL(0x1);
- I915_WRITE(ICL_PORT_PCS_DW1_GRP(port), tmp);
+ I915_WRITE(ICL_PORT_PCS_DW1_GRP(phy), tmp);
}
}
@@ -425,16 +424,16 @@ static void gen11_dsi_voltage_swing_program_seq(struct intel_encoder *encoder)
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
u32 tmp;
- enum port port;
+ enum phy phy;
/* clear common keeper enable bit */
- for_each_dsi_port(port, intel_dsi->ports) {
- tmp = I915_READ(ICL_PORT_PCS_DW1_LN0(port));
+ for_each_dsi_phy(phy, intel_dsi->phys) {
+ tmp = I915_READ(ICL_PORT_PCS_DW1_LN0(phy));
tmp &= ~COMMON_KEEPER_EN;
- I915_WRITE(ICL_PORT_PCS_DW1_GRP(port), tmp);
- tmp = I915_READ(ICL_PORT_PCS_DW1_AUX(port));
+ I915_WRITE(ICL_PORT_PCS_DW1_GRP(phy), tmp);
+ tmp = I915_READ(ICL_PORT_PCS_DW1_AUX(phy));
tmp &= ~COMMON_KEEPER_EN;
- I915_WRITE(ICL_PORT_PCS_DW1_AUX(port), tmp);
+ I915_WRITE(ICL_PORT_PCS_DW1_AUX(phy), tmp);
}
/*
@@ -442,33 +441,33 @@ static void gen11_dsi_voltage_swing_program_seq(struct intel_encoder *encoder)
* Note: loadgen select program is done
* as part of lane phy sequence configuration
*/
- for_each_dsi_port(port, intel_dsi->ports) {
- tmp = I915_READ(ICL_PORT_CL_DW5(port));
+ for_each_dsi_phy(phy, intel_dsi->phys) {
+ tmp = I915_READ(ICL_PORT_CL_DW5(phy));
tmp |= SUS_CLOCK_CONFIG;
- I915_WRITE(ICL_PORT_CL_DW5(port), tmp);
+ I915_WRITE(ICL_PORT_CL_DW5(phy), tmp);
}
/* Clear training enable to change swing values */
- for_each_dsi_port(port, intel_dsi->ports) {
- tmp = I915_READ(ICL_PORT_TX_DW5_LN0(port));
+ for_each_dsi_phy(phy, intel_dsi->phys) {
+ tmp = I915_READ(ICL_PORT_TX_DW5_LN0(phy));
tmp &= ~TX_TRAINING_EN;
- I915_WRITE(ICL_PORT_TX_DW5_GRP(port), tmp);
- tmp = I915_READ(ICL_PORT_TX_DW5_AUX(port));
+ I915_WRITE(ICL_PORT_TX_DW5_GRP(phy), tmp);
+ tmp = I915_READ(ICL_PORT_TX_DW5_AUX(phy));
tmp &= ~TX_TRAINING_EN;
- I915_WRITE(ICL_PORT_TX_DW5_AUX(port), tmp);
+ I915_WRITE(ICL_PORT_TX_DW5_AUX(phy), tmp);
}
/* Program swing and de-emphasis */
dsi_program_swing_and_deemphasis(encoder);
/* Set training enable to trigger update */
- for_each_dsi_port(port, intel_dsi->ports) {
- tmp = I915_READ(ICL_PORT_TX_DW5_LN0(port));
+ for_each_dsi_phy(phy, intel_dsi->phys) {
+ tmp = I915_READ(ICL_PORT_TX_DW5_LN0(phy));
tmp |= TX_TRAINING_EN;
- I915_WRITE(ICL_PORT_TX_DW5_GRP(port), tmp);
- tmp = I915_READ(ICL_PORT_TX_DW5_AUX(port));
+ I915_WRITE(ICL_PORT_TX_DW5_GRP(phy), tmp);
+ tmp = I915_READ(ICL_PORT_TX_DW5_AUX(phy));
tmp |= TX_TRAINING_EN;
- I915_WRITE(ICL_PORT_TX_DW5_AUX(port), tmp);
+ I915_WRITE(ICL_PORT_TX_DW5_AUX(phy), tmp);
}
}
@@ -497,6 +496,7 @@ static void gen11_dsi_setup_dphy_timings(struct intel_encoder *encoder)
struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
u32 tmp;
enum port port;
+ enum phy phy;
/* Program T-INIT master registers */
for_each_dsi_port(port, intel_dsi->ports) {
@@ -546,10 +546,10 @@ static void gen11_dsi_setup_dphy_timings(struct intel_encoder *encoder)
}
if (IS_ELKHARTLAKE(dev_priv)) {
- for_each_dsi_port(port, intel_dsi->ports) {
- tmp = I915_READ(ICL_DPHY_CHKN(port));
+ for_each_dsi_phy(phy, intel_dsi->phys) {
+ tmp = I915_READ(ICL_DPHY_CHKN(phy));
tmp |= ICL_DPHY_CHKN_AFE_OVER_PPI_STRAP;
- I915_WRITE(ICL_DPHY_CHKN(port), tmp);
+ I915_WRITE(ICL_DPHY_CHKN(phy), tmp);
}
}
}
@@ -559,15 +559,12 @@ static void gen11_dsi_gate_clocks(struct intel_encoder *encoder)
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
u32 tmp;
- enum port port;
enum phy phy;
mutex_lock(&dev_priv->dpll_lock);
tmp = I915_READ(DPCLKA_CFGCR0_ICL);
- for_each_dsi_port(port, intel_dsi->ports) {
- phy = intel_port_to_phy(dev_priv, port);
+ for_each_dsi_phy(phy, intel_dsi->phys)
tmp |= ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
- }
I915_WRITE(DPCLKA_CFGCR0_ICL, tmp);
mutex_unlock(&dev_priv->dpll_lock);
@@ -578,15 +575,12 @@ static void gen11_dsi_ungate_clocks(struct intel_encoder *encoder)
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
u32 tmp;
- enum port port;
enum phy phy;
mutex_lock(&dev_priv->dpll_lock);
tmp = I915_READ(DPCLKA_CFGCR0_ICL);
- for_each_dsi_port(port, intel_dsi->ports) {
- phy = intel_port_to_phy(dev_priv, port);
+ for_each_dsi_phy(phy, intel_dsi->phys)
tmp &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
- }
I915_WRITE(DPCLKA_CFGCR0_ICL, tmp);
mutex_unlock(&dev_priv->dpll_lock);
@@ -598,22 +592,19 @@ static void gen11_dsi_map_pll(struct intel_encoder *encoder,
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
struct intel_shared_dpll *pll = crtc_state->shared_dpll;
- enum port port;
enum phy phy;
u32 val;
mutex_lock(&dev_priv->dpll_lock);
val = I915_READ(DPCLKA_CFGCR0_ICL);
- for_each_dsi_port(port, intel_dsi->ports) {
- phy = intel_port_to_phy(dev_priv, port);
+ for_each_dsi_phy(phy, intel_dsi->phys) {
val &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
val |= ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy);
}
I915_WRITE(DPCLKA_CFGCR0_ICL, val);
- for_each_dsi_port(port, intel_dsi->ports) {
- phy = intel_port_to_phy(dev_priv, port);
+ for_each_dsi_phy(phy, intel_dsi->phys) {
val &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
}
I915_WRITE(DPCLKA_CFGCR0_ICL, val);
diff --git a/drivers/gpu/drm/i915/display/intel_combo_phy.c b/drivers/gpu/drm/i915/display/intel_combo_phy.c
index d3d5244765e6..ac8218a040ab 100644
--- a/drivers/gpu/drm/i915/display/intel_combo_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_combo_phy.c
@@ -6,13 +6,13 @@
#include "intel_combo_phy.h"
#include "intel_drv.h"
-#define for_each_combo_port(__dev_priv, __port) \
- for ((__port) = PORT_A; (__port) < I915_MAX_PORTS; (__port)++) \
- for_each_if(intel_port_is_combophy(__dev_priv, __port))
+#define for_each_combo_phy(__dev_priv, __phy) \
+ for ((__phy) = PHY_A; (__phy) < I915_MAX_PHYS; (__phy)++) \
+ for_each_if(intel_phy_is_combo(__dev_priv, __phy))
-#define for_each_combo_port_reverse(__dev_priv, __port) \
- for ((__port) = I915_MAX_PORTS; (__port)-- > PORT_A;) \
- for_each_if(intel_port_is_combophy(__dev_priv, __port))
+#define for_each_combo_phy_reverse(__dev_priv, __phy) \
+ for ((__phy) = I915_MAX_PHYS; (__phy)-- > PHY_A;) \
+ for_each_if(intel_phy_is_combo(__dev_priv, __phy))
enum {
PROCMON_0_85V_DOT_0,
@@ -38,18 +38,17 @@ static const struct cnl_procmon {
};
/*
- * CNL has just one set of registers, while ICL has two sets: one for port A and
- * the other for port B. The CNL registers are equivalent to the ICL port A
- * registers, that's why we call the ICL macros even though the function has CNL
- * on its name.
+ * CNL has just one set of registers, while gen11 has a set for each combo PHY.
+ * The CNL registers are equivalent to the gen11 PHY A registers, that's why we
+ * call the ICL macros even though the function has CNL on its name.
*/
static const struct cnl_procmon *
-cnl_get_procmon_ref_values(struct drm_i915_private *dev_priv, enum port port)
+cnl_get_procmon_ref_values(struct drm_i915_private *dev_priv, enum phy phy)
{
const struct cnl_procmon *procmon;
u32 val;
- val = I915_READ(ICL_PORT_COMP_DW3(port));
+ val = I915_READ(ICL_PORT_COMP_DW3(phy));
switch (val & (PROCESS_INFO_MASK | VOLTAGE_INFO_MASK)) {
default:
MISSING_CASE(val);
@@ -75,32 +74,32 @@ cnl_get_procmon_ref_values(struct drm_i915_private *dev_priv, enum port port)
}
static void cnl_set_procmon_ref_values(struct drm_i915_private *dev_priv,
- enum port port)
+ enum phy phy)
{
const struct cnl_procmon *procmon;
u32 val;
- procmon = cnl_get_procmon_ref_values(dev_priv, port);
+ procmon = cnl_get_procmon_ref_values(dev_priv, phy);
- val = I915_READ(ICL_PORT_COMP_DW1(port));
+ val = I915_READ(ICL_PORT_COMP_DW1(phy));
val &= ~((0xff << 16) | 0xff);
val |= procmon->dw1;
- I915_WRITE(ICL_PORT_COMP_DW1(port), val);
+ I915_WRITE(ICL_PORT_COMP_DW1(phy), val);
- I915_WRITE(ICL_PORT_COMP_DW9(port), procmon->dw9);
- I915_WRITE(ICL_PORT_COMP_DW10(port), procmon->dw10);
+ I915_WRITE(ICL_PORT_COMP_DW9(phy), procmon->dw9);
+ I915_WRITE(ICL_PORT_COMP_DW10(phy), procmon->dw10);
}
static bool check_phy_reg(struct drm_i915_private *dev_priv,
- enum port port, i915_reg_t reg, u32 mask,
+ enum phy phy, i915_reg_t reg, u32 mask,
u32 expected_val)
{
u32 val = I915_READ(reg);
if ((val & mask) != expected_val) {
- DRM_DEBUG_DRIVER("Port %c combo PHY reg %08x state mismatch: "
+ DRM_DEBUG_DRIVER("Combo PHY %c reg %08x state mismatch: "
"current %08x mask %08x expected %08x\n",
- port_name(port),
+ phy_name(phy),
reg.reg, val, mask, expected_val);
return false;
}
@@ -109,18 +108,18 @@ static bool check_phy_reg(struct drm_i915_private *dev_priv,
}
static bool cnl_verify_procmon_ref_values(struct drm_i915_private *dev_priv,
- enum port port)
+ enum phy phy)
{
const struct cnl_procmon *procmon;
bool ret;
- procmon = cnl_get_procmon_ref_values(dev_priv, port);
+ procmon = cnl_get_procmon_ref_values(dev_priv, phy);
- ret = check_phy_reg(dev_priv, port, ICL_PORT_COMP_DW1(port),
+ ret = check_phy_reg(dev_priv, phy, ICL_PORT_COMP_DW1(phy),
(0xff << 16) | 0xff, procmon->dw1);
- ret &= check_phy_reg(dev_priv, port, ICL_PORT_COMP_DW9(port),
+ ret &= check_phy_reg(dev_priv, phy, ICL_PORT_COMP_DW9(phy),
-1U, procmon->dw9);
- ret &= check_phy_reg(dev_priv, port, ICL_PORT_COMP_DW10(port),
+ ret &= check_phy_reg(dev_priv, phy, ICL_PORT_COMP_DW10(phy),
-1U, procmon->dw10);
return ret;
@@ -134,15 +133,15 @@ static bool cnl_combo_phy_enabled(struct drm_i915_private *dev_priv)
static bool cnl_combo_phy_verify_state(struct drm_i915_private *dev_priv)
{
- enum port port = PORT_A;
+ enum phy phy = PHY_A;
bool ret;
if (!cnl_combo_phy_enabled(dev_priv))
return false;
- ret = cnl_verify_procmon_ref_values(dev_priv, port);
+ ret = cnl_verify_procmon_ref_values(dev_priv, phy);
- ret &= check_phy_reg(dev_priv, port, CNL_PORT_CL1CM_DW5,
+ ret &= check_phy_reg(dev_priv, phy, CNL_PORT_CL1CM_DW5,
CL_POWER_DOWN_ENABLE, CL_POWER_DOWN_ENABLE);
return ret;
@@ -157,7 +156,7 @@ static void cnl_combo_phys_init(struct drm_i915_private *dev_priv)
I915_WRITE(CHICKEN_MISC_2, val);
/* Dummy PORT_A to get the correct CNL register from the ICL macro */
- cnl_set_procmon_ref_values(dev_priv, PORT_A);
+ cnl_set_procmon_ref_values(dev_priv, PHY_A);
val = I915_READ(CNL_PORT_COMP_DW0);
val |= COMP_INIT;
@@ -181,39 +180,39 @@ static void cnl_combo_phys_uninit(struct drm_i915_private *dev_priv)
}
static bool icl_combo_phy_enabled(struct drm_i915_private *dev_priv,
- enum port port)
+ enum phy phy)
{
/* The PHY C added by EHL has no PHY_MISC register */
- if (IS_ELKHARTLAKE(dev_priv) && port == PORT_C)
- return I915_READ(ICL_PORT_COMP_DW0(port)) & COMP_INIT;
+ if (IS_ELKHARTLAKE(dev_priv) && phy == PHY_C)
+ return I915_READ(ICL_PORT_COMP_DW0(phy)) & COMP_INIT;
else
- return !(I915_READ(ICL_PHY_MISC(port)) &
+ return !(I915_READ(ICL_PHY_MISC(phy)) &
ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN) &&
- (I915_READ(ICL_PORT_COMP_DW0(port)) & COMP_INIT);
+ (I915_READ(ICL_PORT_COMP_DW0(phy)) & COMP_INIT);
}
static bool icl_combo_phy_verify_state(struct drm_i915_private *dev_priv,
- enum port port)
+ enum phy phy)
{
bool ret;
- if (!icl_combo_phy_enabled(dev_priv, port))
+ if (!icl_combo_phy_enabled(dev_priv, phy))
return false;
- ret = cnl_verify_procmon_ref_values(dev_priv, port);
+ ret = cnl_verify_procmon_ref_values(dev_priv, phy);
- if (port == PORT_A)
- ret &= check_phy_reg(dev_priv, port, ICL_PORT_COMP_DW8(port),
+ if (phy == PHY_A)
+ ret &= check_phy_reg(dev_priv, phy, ICL_PORT_COMP_DW8(phy),
IREFGEN, IREFGEN);
- ret &= check_phy_reg(dev_priv, port, ICL_PORT_CL_DW5(port),
+ ret &= check_phy_reg(dev_priv, phy, ICL_PORT_CL_DW5(phy),
CL_POWER_DOWN_ENABLE, CL_POWER_DOWN_ENABLE);
return ret;
}
void intel_combo_phy_power_up_lanes(struct drm_i915_private *dev_priv,
- enum port port, bool is_dsi,
+ enum phy phy, bool is_dsi,
int lane_count, bool lane_reversal)
{
u8 lane_mask;
@@ -258,10 +257,10 @@ void intel_combo_phy_power_up_lanes(struct drm_i915_private *dev_priv,
}
}
- val = I915_READ(ICL_PORT_CL_DW10(port));
+ val = I915_READ(ICL_PORT_CL_DW10(phy));
val &= ~PWR_DOWN_LN_MASK;
val |= lane_mask << PWR_DOWN_LN_SHIFT;
- I915_WRITE(ICL_PORT_CL_DW10(port), val);
+ I915_WRITE(ICL_PORT_CL_DW10(phy), val);
}
static u32 ehl_combo_phy_a_mux(struct drm_i915_private *i915, u32 val)
@@ -292,14 +291,14 @@ static u32 ehl_combo_phy_a_mux(struct drm_i915_private *i915, u32 val)
static void icl_combo_phys_init(struct drm_i915_private *dev_priv)
{
- enum port port;
+ enum phy phy;
- for_each_combo_port(dev_priv, port) {
+ for_each_combo_phy(dev_priv, phy) {
u32 val;
- if (icl_combo_phy_verify_state(dev_priv, port)) {
- DRM_DEBUG_DRIVER("Port %c combo PHY already enabled, won't reprogram it.\n",
- port_name(port));
+ if (icl_combo_phy_verify_state(dev_priv, phy)) {
+ DRM_DEBUG_DRIVER("Combo PHY %c already enabled, won't reprogram it.\n",
+ phy_name(phy));
continue;
}
@@ -308,7 +307,7 @@ static void icl_combo_phys_init(struct drm_i915_private *dev_priv)
* register for it and no need to program the
* DE_IO_COMP_PWR_DOWN setting on PHY C.
*/
- if (IS_ELKHARTLAKE(dev_priv) && port == PORT_C)
+ if (IS_ELKHARTLAKE(dev_priv) && phy == PHY_C)
goto skip_phy_misc;
/*
@@ -319,59 +318,59 @@ static void icl_combo_phys_init(struct drm_i915_private *dev_priv)
* based on whether our VBT indicates the presence of any
* "internal" child devices.
*/
- val = I915_READ(ICL_PHY_MISC(port));
- if (IS_ELKHARTLAKE(dev_priv) && port == PORT_A)
+ val = I915_READ(ICL_PHY_MISC(phy));
+ if (IS_ELKHARTLAKE(dev_priv) && phy == PHY_A)
val = ehl_combo_phy_a_mux(dev_priv, val);
val &= ~ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN;
- I915_WRITE(ICL_PHY_MISC(port), val);
+ I915_WRITE(ICL_PHY_MISC(phy), val);
skip_phy_misc:
- cnl_set_procmon_ref_values(dev_priv, port);
+ cnl_set_procmon_ref_values(dev_priv, phy);
- if (port == PORT_A) {
- val = I915_READ(ICL_PORT_COMP_DW8(port));
+ if (phy == PHY_A) {
+ val = I915_READ(ICL_PORT_COMP_DW8(phy));
val |= IREFGEN;
- I915_WRITE(ICL_PORT_COMP_DW8(port), val);
+ I915_WRITE(ICL_PORT_COMP_DW8(phy), val);
}
- val = I915_READ(ICL_PORT_COMP_DW0(port));
+ val = I915_READ(ICL_PORT_COMP_DW0(phy));
val |= COMP_INIT;
- I915_WRITE(ICL_PORT_COMP_DW0(port), val);
+ I915_WRITE(ICL_PORT_COMP_DW0(phy), val);
- val = I915_READ(ICL_PORT_CL_DW5(port));
+ val = I915_READ(ICL_PORT_CL_DW5(phy));
val |= CL_POWER_DOWN_ENABLE;
- I915_WRITE(ICL_PORT_CL_DW5(port), val);
+ I915_WRITE(ICL_PORT_CL_DW5(phy), val);
}
}
static void icl_combo_phys_uninit(struct drm_i915_private *dev_priv)
{
- enum port port;
+ enum phy phy;
- for_each_combo_port_reverse(dev_priv, port) {
+ for_each_combo_phy_reverse(dev_priv, phy) {
u32 val;
- if (port == PORT_A &&
- !icl_combo_phy_verify_state(dev_priv, port))
- DRM_WARN("Port %c combo PHY HW state changed unexpectedly\n",
- port_name(port));
+ if (phy == PHY_A &&
+ !icl_combo_phy_verify_state(dev_priv, phy))
+ DRM_WARN("Combo PHY %c HW state changed unexpectedly\n",
+ phy_name(phy));
/*
* Although EHL adds a combo PHY C, there's no PHY_MISC
* register for it and no need to program the
* DE_IO_COMP_PWR_DOWN setting on PHY C.
*/
- if (IS_ELKHARTLAKE(dev_priv) && port == PORT_C)
+ if (IS_ELKHARTLAKE(dev_priv) && phy == PHY_C)
goto skip_phy_misc;
- val = I915_READ(ICL_PHY_MISC(port));
+ val = I915_READ(ICL_PHY_MISC(phy));
val |= ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN;
- I915_WRITE(ICL_PHY_MISC(port), val);
+ I915_WRITE(ICL_PHY_MISC(phy), val);
skip_phy_misc:
- val = I915_READ(ICL_PORT_COMP_DW0(port));
+ val = I915_READ(ICL_PORT_COMP_DW0(phy));
val &= ~COMP_INIT;
- I915_WRITE(ICL_PORT_COMP_DW0(port), val);
+ I915_WRITE(ICL_PORT_COMP_DW0(phy), val);
}
}
diff --git a/drivers/gpu/drm/i915/display/intel_combo_phy.h b/drivers/gpu/drm/i915/display/intel_combo_phy.h
index e6e195a83b19..80a1386b4c87 100644
--- a/drivers/gpu/drm/i915/display/intel_combo_phy.h
+++ b/drivers/gpu/drm/i915/display/intel_combo_phy.h
@@ -10,11 +10,12 @@
#include <drm/i915_drm.h>
struct drm_i915_private;
+enum phy;
void intel_combo_phy_init(struct drm_i915_private *dev_priv);
void intel_combo_phy_uninit(struct drm_i915_private *dev_priv);
void intel_combo_phy_power_up_lanes(struct drm_i915_private *dev_priv,
- enum port port, bool is_dsi,
+ enum phy phy, bool is_dsi,
int lane_count, bool lane_reversal);
#endif /* __INTEL_COMBO_PHY_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index a40a53527d99..50dd9d731456 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -2414,7 +2414,7 @@ static void cnl_ddi_vswing_sequence(struct intel_encoder *encoder,
}
static void icl_ddi_combo_vswing_program(struct drm_i915_private *dev_priv,
- u32 level, enum port port, int type,
+ u32 level, enum phy phy, int type,
int rate)
{
const struct cnl_ddi_buf_trans *ddi_translations = NULL;
@@ -2432,41 +2432,41 @@ static void icl_ddi_combo_vswing_program(struct drm_i915_private *dev_priv,
}
/* Set PORT_TX_DW5 */
- val = I915_READ(ICL_PORT_TX_DW5_LN0(port));
+ val = I915_READ(ICL_PORT_TX_DW5_LN0(phy));
val &= ~(SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK |
TAP2_DISABLE | TAP3_DISABLE);
val |= SCALING_MODE_SEL(0x2);
val |= RTERM_SELECT(0x6);
val |= TAP3_DISABLE;
- I915_WRITE(ICL_PORT_TX_DW5_GRP(port), val);
+ I915_WRITE(ICL_PORT_TX_DW5_GRP(phy), val);
/* Program PORT_TX_DW2 */
- val = I915_READ(ICL_PORT_TX_DW2_LN0(port));
+ val = I915_READ(ICL_PORT_TX_DW2_LN0(phy));
val &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK |
RCOMP_SCALAR_MASK);
val |= SWING_SEL_UPPER(ddi_translations[level].dw2_swing_sel);
val |= SWING_SEL_LOWER(ddi_translations[level].dw2_swing_sel);
/* Program Rcomp scalar for every table entry */
val |= RCOMP_SCALAR(0x98);
- I915_WRITE(ICL_PORT_TX_DW2_GRP(port), val);
+ I915_WRITE(ICL_PORT_TX_DW2_GRP(phy), val);
/* Program PORT_TX_DW4 */
/* We cannot write to GRP. It would overwrite individual loadgen. */
for (ln = 0; ln <= 3; ln++) {
- val = I915_READ(ICL_PORT_TX_DW4_LN(ln, port));
+ val = I915_READ(ICL_PORT_TX_DW4_LN(ln, phy));
val &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK |
CURSOR_COEFF_MASK);
val |= POST_CURSOR_1(ddi_translations[level].dw4_post_cursor_1);
val |= POST_CURSOR_2(ddi_translations[level].dw4_post_cursor_2);
val |= CURSOR_COEFF(ddi_translations[level].dw4_cursor_coeff);
- I915_WRITE(ICL_PORT_TX_DW4_LN(ln, port), val);
+ I915_WRITE(ICL_PORT_TX_DW4_LN(ln, phy), val);
}
/* Program PORT_TX_DW7 */
- val = I915_READ(ICL_PORT_TX_DW7_LN0(port));
+ val = I915_READ(ICL_PORT_TX_DW7_LN0(phy));
val &= ~N_SCALAR_MASK;
val |= N_SCALAR(ddi_translations[level].dw7_n_scalar);
- I915_WRITE(ICL_PORT_TX_DW7_GRP(port), val);
+ I915_WRITE(ICL_PORT_TX_DW7_GRP(phy), val);
}
static void icl_combo_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
@@ -2474,7 +2474,7 @@ static void icl_combo_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
enum intel_output_type type)
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
- enum port port = encoder->port;
+ enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
int width = 0;
int rate = 0;
u32 val;
@@ -2495,12 +2495,12 @@ static void icl_combo_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
* set PORT_PCS_DW1 cmnkeeper_enable to 1b,
* else clear to 0b.
*/
- val = I915_READ(ICL_PORT_PCS_DW1_LN0(port));
+ val = I915_READ(ICL_PORT_PCS_DW1_LN0(phy));
if (type == INTEL_OUTPUT_HDMI)
val &= ~COMMON_KEEPER_EN;
else
val |= COMMON_KEEPER_EN;
- I915_WRITE(ICL_PORT_PCS_DW1_GRP(port), val);
+ I915_WRITE(ICL_PORT_PCS_DW1_GRP(phy), val);
/* 2. Program loadgen select */
/*
@@ -2510,33 +2510,33 @@ static void icl_combo_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
* > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0)
*/
for (ln = 0; ln <= 3; ln++) {
- val = I915_READ(ICL_PORT_TX_DW4_LN(ln, port));
+ val = I915_READ(ICL_PORT_TX_DW4_LN(ln, phy));
val &= ~LOADGEN_SELECT;
if ((rate <= 600000 && width == 4 && ln >= 1) ||
(rate <= 600000 && width < 4 && (ln == 1 || ln == 2))) {
val |= LOADGEN_SELECT;
}
- I915_WRITE(ICL_PORT_TX_DW4_LN(ln, port), val);
+ I915_WRITE(ICL_PORT_TX_DW4_LN(ln, phy), val);
}
/* 3. Set PORT_CL_DW5 SUS Clock Config to 11b */
- val = I915_READ(ICL_PORT_CL_DW5(port));
+ val = I915_READ(ICL_PORT_CL_DW5(phy));
val |= SUS_CLOCK_CONFIG;
- I915_WRITE(ICL_PORT_CL_DW5(port), val);
+ I915_WRITE(ICL_PORT_CL_DW5(phy), val);
/* 4. Clear training enable to change swing values */
- val = I915_READ(ICL_PORT_TX_DW5_LN0(port));
+ val = I915_READ(ICL_PORT_TX_DW5_LN0(phy));
val &= ~TX_TRAINING_EN;
- I915_WRITE(ICL_PORT_TX_DW5_GRP(port), val);
+ I915_WRITE(ICL_PORT_TX_DW5_GRP(phy), val);
/* 5. Program swing and de-emphasis */
- icl_ddi_combo_vswing_program(dev_priv, level, port, type, rate);
+ icl_ddi_combo_vswing_program(dev_priv, level, phy, type, rate);
/* 6. Set training enable to trigger update */
- val = I915_READ(ICL_PORT_TX_DW5_LN0(port));
+ val = I915_READ(ICL_PORT_TX_DW5_LN0(phy));
val |= TX_TRAINING_EN;
- I915_WRITE(ICL_PORT_TX_DW5_GRP(port), val);
+ I915_WRITE(ICL_PORT_TX_DW5_GRP(phy), val);
}
static void icl_mg_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
@@ -3120,6 +3120,7 @@ static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder,
struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
enum port port = encoder->port;
+ enum phy phy = intel_port_to_phy(dev_priv, port);
struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST);
int level = intel_ddi_dp_level(intel_dp);
@@ -3155,7 +3156,7 @@ static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder,
bool lane_reversal =
dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL;
- intel_combo_phy_power_up_lanes(dev_priv, port, false,
+ intel_combo_phy_power_up_lanes(dev_priv, phy, false,
crtc_state->lane_count,
lane_reversal);
}
diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
index d53285fb883f..8a4a57ef82a2 100644
--- a/drivers/gpu/drm/i915/display/intel_display.h
+++ b/drivers/gpu/drm/i915/display/intel_display.h
@@ -268,6 +268,10 @@ enum phy {
for ((__port) = PORT_A; (__port) < I915_MAX_PORTS; (__port)++) \
for_each_if((__ports_mask) & BIT(__port))
+#define for_each_phy_masked(__phy, __phys_mask) \
+ for ((__phy) = PHY_A; (__phy) < I915_MAX_PHYS; (__phy)++) \
+ for_each_if((__phys_mask) & BIT(__phy))
+
#define for_each_crtc(dev, crtc) \
list_for_each_entry(crtc, &(dev)->mode_config.crtc_list, head)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index c19b958461ca..64627c117c31 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -395,7 +395,7 @@ static void hsw_power_well_disable(struct drm_i915_private *dev_priv,
hsw_wait_for_power_well_disable(dev_priv, power_well);
}
-#define ICL_AUX_PW_TO_PORT(pw_idx) ((pw_idx) - ICL_PW_CTL_IDX_AUX_A)
+#define ICL_AUX_PW_TO_PHY(pw_idx) ((pw_idx) - ICL_PW_CTL_IDX_AUX_A)
static void
icl_combo_phy_aux_power_well_enable(struct drm_i915_private *dev_priv,
@@ -403,21 +403,21 @@ icl_combo_phy_aux_power_well_enable(struct drm_i915_private *dev_priv,
{
const struct i915_power_well_regs *regs = power_well->desc->hsw.regs;
int pw_idx = power_well->desc->hsw.idx;
- enum port port = ICL_AUX_PW_TO_PORT(pw_idx);
+ enum phy phy = ICL_AUX_PW_TO_PHY(pw_idx);
u32 val;
val = I915_READ(regs->driver);
I915_WRITE(regs->driver, val | HSW_PWR_WELL_CTL_REQ(pw_idx));
- val = I915_READ(ICL_PORT_CL_DW12(port));
- I915_WRITE(ICL_PORT_CL_DW12(port), val | ICL_LANE_ENABLE_AUX);
+ val = I915_READ(ICL_PORT_CL_DW12(phy));
+ I915_WRITE(ICL_PORT_CL_DW12(phy), val | ICL_LANE_ENABLE_AUX);
hsw_wait_for_power_well_enable(dev_priv, power_well);
/* Display WA #1178: icl */
if (IS_ICELAKE(dev_priv) &&
pw_idx >= ICL_PW_CTL_IDX_AUX_A && pw_idx <= ICL_PW_CTL_IDX_AUX_B &&
- !intel_bios_is_port_edp(dev_priv, port)) {
+ !intel_bios_is_port_edp(dev_priv, (enum port)phy)) {
val = I915_READ(ICL_AUX_ANAOVRD1(pw_idx));
val |= ICL_AUX_ANAOVRD1_ENABLE | ICL_AUX_ANAOVRD1_LDO_BYPASS;
I915_WRITE(ICL_AUX_ANAOVRD1(pw_idx), val);
@@ -430,11 +430,11 @@ icl_combo_phy_aux_power_well_disable(struct drm_i915_private *dev_priv,
{
const struct i915_power_well_regs *regs = power_well->desc->hsw.regs;
int pw_idx = power_well->desc->hsw.idx;
- enum port port = ICL_AUX_PW_TO_PORT(pw_idx);
+ enum phy phy = ICL_AUX_PW_TO_PHY(pw_idx);
u32 val;
- val = I915_READ(ICL_PORT_CL_DW12(port));
- I915_WRITE(ICL_PORT_CL_DW12(port), val & ~ICL_LANE_ENABLE_AUX);
+ val = I915_READ(ICL_PORT_CL_DW12(phy));
+ I915_WRITE(ICL_PORT_CL_DW12(phy), val & ~ICL_LANE_ENABLE_AUX);
val = I915_READ(regs->driver);
I915_WRITE(regs->driver, val & ~HSW_PWR_WELL_CTL_REQ(pw_idx));
diff --git a/drivers/gpu/drm/i915/display/intel_dsi.h b/drivers/gpu/drm/i915/display/intel_dsi.h
index 6d20434636cd..1cd24bd46518 100644
--- a/drivers/gpu/drm/i915/display/intel_dsi.h
+++ b/drivers/gpu/drm/i915/display/intel_dsi.h
@@ -49,8 +49,11 @@ struct intel_dsi {
struct intel_connector *attached_connector;
- /* bit mask of ports being driven */
- u16 ports;
+ /* bit mask of ports (vlv dsi) or phys (icl dsi) being driven */
+ union {
+ u16 ports; /* VLV DSI */
+ u16 phys; /* ICL DSI */
+ };
/* if true, use HS mode, otherwise LP */
bool hs;
@@ -132,7 +135,10 @@ static inline struct intel_dsi_host *to_intel_dsi_host(struct mipi_dsi_host *h)
return container_of(h, struct intel_dsi_host, base);
}
-#define for_each_dsi_port(__port, __ports_mask) for_each_port_masked(__port, __ports_mask)
+#define for_each_dsi_port(__port, __ports_mask) \
+ for_each_port_masked(__port, __ports_mask)
+#define for_each_dsi_phy(__phy, __phys_mask) \
+ for_each_phy_masked(__phy, __phys_mask)
static inline struct intel_dsi *enc_to_intel_dsi(struct drm_encoder *encoder)
{
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index c9e2e09b6f01..b766ba22045b 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1794,20 +1794,20 @@ enum i915_power_well_id {
#define _ICL_COMBOPHY_A 0x162000
#define _ICL_COMBOPHY_B 0x6C000
#define _EHL_COMBOPHY_C 0x160000
-#define _ICL_COMBOPHY(port) _PICK(port, _ICL_COMBOPHY_A, \
+#define _ICL_COMBOPHY(phy) _PICK(phy, _ICL_COMBOPHY_A, \
_ICL_COMBOPHY_B, \
_EHL_COMBOPHY_C)
/* CNL/ICL Port CL_DW registers */
-#define _ICL_PORT_CL_DW(dw, port) (_ICL_COMBOPHY(port) + \
+#define _ICL_PORT_CL_DW(dw, phy) (_ICL_COMBOPHY(phy) + \
4 * (dw))
#define CNL_PORT_CL1CM_DW5 _MMIO(0x162014)
-#define ICL_PORT_CL_DW5(port) _MMIO(_ICL_PORT_CL_DW(5, port))
+#define ICL_PORT_CL_DW5(phy) _MMIO(_ICL_PORT_CL_DW(5, phy))
#define CL_POWER_DOWN_ENABLE (1 << 4)
#define SUS_CLOCK_CONFIG (3 << 0)
-#define ICL_PORT_CL_DW10(port) _MMIO(_ICL_PORT_CL_DW(10, port))
+#define ICL_PORT_CL_DW10(phy) _MMIO(_ICL_PORT_CL_DW(10, phy))
#define PG_SEQ_DELAY_OVERRIDE_MASK (3 << 25)
#define PG_SEQ_DELAY_OVERRIDE_SHIFT 25
#define PG_SEQ_DELAY_OVERRIDE_ENABLE (1 << 24)
@@ -1822,23 +1822,23 @@ enum i915_power_well_id {
#define PWR_DOWN_LN_MASK (0xf << 4)
#define PWR_DOWN_LN_SHIFT 4
-#define ICL_PORT_CL_DW12(port) _MMIO(_ICL_PORT_CL_DW(12, port))
+#define ICL_PORT_CL_DW12(phy) _MMIO(_ICL_PORT_CL_DW(12, phy))
#define ICL_LANE_ENABLE_AUX (1 << 0)
/* CNL/ICL Port COMP_DW registers */
#define _ICL_PORT_COMP 0x100
-#define _ICL_PORT_COMP_DW(dw, port) (_ICL_COMBOPHY(port) + \
+#define _ICL_PORT_COMP_DW(dw, phy) (_ICL_COMBOPHY(phy) + \
_ICL_PORT_COMP + 4 * (dw))
#define CNL_PORT_COMP_DW0 _MMIO(0x162100)
-#define ICL_PORT_COMP_DW0(port) _MMIO(_ICL_PORT_COMP_DW(0, port))
+#define ICL_PORT_COMP_DW0(phy) _MMIO(_ICL_PORT_COMP_DW(0, phy))
#define COMP_INIT (1 << 31)
#define CNL_PORT_COMP_DW1 _MMIO(0x162104)
-#define ICL_PORT_COMP_DW1(port) _MMIO(_ICL_PORT_COMP_DW(1, port))
+#define ICL_PORT_COMP_DW1(phy) _MMIO(_ICL_PORT_COMP_DW(1, phy))
#define CNL_PORT_COMP_DW3 _MMIO(0x16210c)
-#define ICL_PORT_COMP_DW3(port) _MMIO(_ICL_PORT_COMP_DW(3, port))
+#define ICL_PORT_COMP_DW3(phy) _MMIO(_ICL_PORT_COMP_DW(3, phy))
#define PROCESS_INFO_DOT_0 (0 << 26)
#define PROCESS_INFO_DOT_1 (1 << 26)
#define PROCESS_INFO_DOT_4 (2 << 26)
@@ -1850,14 +1850,14 @@ enum i915_power_well_id {
#define VOLTAGE_INFO_MASK (3 << 24)
#define VOLTAGE_INFO_SHIFT 24
-#define ICL_PORT_COMP_DW8(port) _MMIO(_ICL_PORT_COMP_DW(8, port))
+#define ICL_PORT_COMP_DW8(phy) _MMIO(_ICL_PORT_COMP_DW(8, phy))
#define IREFGEN (1 << 24)
#define CNL_PORT_COMP_DW9 _MMIO(0x162124)
-#define ICL_PORT_COMP_DW9(port) _MMIO(_ICL_PORT_COMP_DW(9, port))
+#define ICL_PORT_COMP_DW9(phy) _MMIO(_ICL_PORT_COMP_DW(9, phy))
#define CNL_PORT_COMP_DW10 _MMIO(0x162128)
-#define ICL_PORT_COMP_DW10(port) _MMIO(_ICL_PORT_COMP_DW(10, port))
+#define ICL_PORT_COMP_DW10(phy) _MMIO(_ICL_PORT_COMP_DW(10, phy))
/* CNL/ICL Port PCS registers */
#define _CNL_PORT_PCS_DW1_GRP_AE 0x162304
@@ -1870,14 +1870,14 @@ enum i915_power_well_id {
#define _CNL_PORT_PCS_DW1_LN0_C 0x162C04
#define _CNL_PORT_PCS_DW1_LN0_D 0x162E04
#define _CNL_PORT_PCS_DW1_LN0_F 0x162804
-#define CNL_PORT_PCS_DW1_GRP(port) _MMIO(_PICK(port, \
+#define CNL_PORT_PCS_DW1_GRP(phy) _MMIO(_PICK(phy, \
_CNL_PORT_PCS_DW1_GRP_AE, \
_CNL_PORT_PCS_DW1_GRP_B, \
_CNL_PORT_PCS_DW1_GRP_C, \
_CNL_PORT_PCS_DW1_GRP_D, \
_CNL_PORT_PCS_DW1_GRP_AE, \
_CNL_PORT_PCS_DW1_GRP_F))
-#define CNL_PORT_PCS_DW1_LN0(port) _MMIO(_PICK(port, \
+#define CNL_PORT_PCS_DW1_LN0(phy) _MMIO(_PICK(phy, \
_CNL_PORT_PCS_DW1_LN0_AE, \
_CNL_PORT_PCS_DW1_LN0_B, \
_CNL_PORT_PCS_DW1_LN0_C, \
@@ -1888,15 +1888,15 @@ enum i915_power_well_id {
#define _ICL_PORT_PCS_AUX 0x300
#define _ICL_PORT_PCS_GRP 0x600
#define _ICL_PORT_PCS_LN(ln) (0x800 + (ln) * 0x100)
-#define _ICL_PORT_PCS_DW_AUX(dw, port) (_ICL_COMBOPHY(port) + \
+#define _ICL_PORT_PCS_DW_AUX(dw, phy) (_ICL_COMBOPHY(phy) + \
_ICL_PORT_PCS_AUX + 4 * (dw))
-#define _ICL_PORT_PCS_DW_GRP(dw, port) (_ICL_COMBOPHY(port) + \
+#define _ICL_PORT_PCS_DW_GRP(dw, phy) (_ICL_COMBOPHY(phy) + \
_ICL_PORT_PCS_GRP + 4 * (dw))
-#define _ICL_PORT_PCS_DW_LN(dw, ln, port) (_ICL_COMBOPHY(port) + \
+#define _ICL_PORT_PCS_DW_LN(dw, ln, phy) (_ICL_COMBOPHY(phy) + \
_ICL_PORT_PCS_LN(ln) + 4 * (dw))
-#define ICL_PORT_PCS_DW1_AUX(port) _MMIO(_ICL_PORT_PCS_DW_AUX(1, port))
-#define ICL_PORT_PCS_DW1_GRP(port) _MMIO(_ICL_PORT_PCS_DW_GRP(1, port))
-#define ICL_PORT_PCS_DW1_LN0(port) _MMIO(_ICL_PORT_PCS_DW_LN(1, 0, port))
+#define ICL_PORT_PCS_DW1_AUX(phy) _MMIO(_ICL_PORT_PCS_DW_AUX(1, phy))
+#define ICL_PORT_PCS_DW1_GRP(phy) _MMIO(_ICL_PORT_PCS_DW_GRP(1, phy))
+#define ICL_PORT_PCS_DW1_LN0(phy) _MMIO(_ICL_PORT_PCS_DW_LN(1, 0, phy))
#define COMMON_KEEPER_EN (1 << 26)
#define LATENCY_OPTIM_MASK (0x3 << 2)
#define LATENCY_OPTIM_VAL(x) ((x) << 2)
@@ -1933,18 +1933,18 @@ enum i915_power_well_id {
#define _ICL_PORT_TX_GRP 0x680
#define _ICL_PORT_TX_LN(ln) (0x880 + (ln) * 0x100)
-#define _ICL_PORT_TX_DW_AUX(dw, port) (_ICL_COMBOPHY(port) + \
+#define _ICL_PORT_TX_DW_AUX(dw, phy) (_ICL_COMBOPHY(phy) + \
_ICL_PORT_TX_AUX + 4 * (dw))
-#define _ICL_PORT_TX_DW_GRP(dw, port) (_ICL_COMBOPHY(port) + \
+#define _ICL_PORT_TX_DW_GRP(dw, phy) (_ICL_COMBOPHY(phy) + \
_ICL_PORT_TX_GRP + 4 * (dw))
-#define _ICL_PORT_TX_DW_LN(dw, ln, port) (_ICL_COMBOPHY(port) + \
+#define _ICL_PORT_TX_DW_LN(dw, ln, phy) (_ICL_COMBOPHY(phy) + \
_ICL_PORT_TX_LN(ln) + 4 * (dw))
#define CNL_PORT_TX_DW2_GRP(port) _MMIO(_CNL_PORT_TX_DW_GRP(2, port))
#define CNL_PORT_TX_DW2_LN0(port) _MMIO(_CNL_PORT_TX_DW_LN0(2, port))
-#define ICL_PORT_TX_DW2_AUX(port) _MMIO(_ICL_PORT_TX_DW_AUX(2, port))
-#define ICL_PORT_TX_DW2_GRP(port) _MMIO(_ICL_PORT_TX_DW_GRP(2, port))
-#define ICL_PORT_TX_DW2_LN0(port) _MMIO(_ICL_PORT_TX_DW_LN(2, 0, port))
+#define ICL_PORT_TX_DW2_AUX(phy) _MMIO(_ICL_PORT_TX_DW_AUX(2, phy))
+#define ICL_PORT_TX_DW2_GRP(phy) _MMIO(_ICL_PORT_TX_DW_GRP(2, phy))
+#define ICL_PORT_TX_DW2_LN0(phy) _MMIO(_ICL_PORT_TX_DW_LN(2, 0, phy))
#define SWING_SEL_UPPER(x) (((x) >> 3) << 15)
#define SWING_SEL_UPPER_MASK (1 << 15)
#define SWING_SEL_LOWER(x) (((x) & 0x7) << 11)
@@ -1961,10 +1961,10 @@ enum i915_power_well_id {
#define CNL_PORT_TX_DW4_LN(ln, port) _MMIO(_CNL_PORT_TX_DW_LN0(4, (port)) + \
((ln) * (_CNL_PORT_TX_DW4_LN1_AE - \
_CNL_PORT_TX_DW4_LN0_AE)))
-#define ICL_PORT_TX_DW4_AUX(port) _MMIO(_ICL_PORT_TX_DW_AUX(4, port))
-#define ICL_PORT_TX_DW4_GRP(port) _MMIO(_ICL_PORT_TX_DW_GRP(4, port))
-#define ICL_PORT_TX_DW4_LN0(port) _MMIO(_ICL_PORT_TX_DW_LN(4, 0, port))
-#define ICL_PORT_TX_DW4_LN(ln, port) _MMIO(_ICL_PORT_TX_DW_LN(4, ln, port))
+#define ICL_PORT_TX_DW4_AUX(phy) _MMIO(_ICL_PORT_TX_DW_AUX(4, phy))
+#define ICL_PORT_TX_DW4_GRP(phy) _MMIO(_ICL_PORT_TX_DW_GRP(4, phy))
+#define ICL_PORT_TX_DW4_LN0(phy) _MMIO(_ICL_PORT_TX_DW_LN(4, 0, phy))
+#define ICL_PORT_TX_DW4_LN(ln, phy) _MMIO(_ICL_PORT_TX_DW_LN(4, ln, phy))
#define LOADGEN_SELECT (1 << 31)
#define POST_CURSOR_1(x) ((x) << 12)
#define POST_CURSOR_1_MASK (0x3F << 12)
@@ -1975,9 +1975,9 @@ enum i915_power_well_id {
#define CNL_PORT_TX_DW5_GRP(port) _MMIO(_CNL_PORT_TX_DW_GRP(5, port))
#define CNL_PORT_TX_DW5_LN0(port) _MMIO(_CNL_PORT_TX_DW_LN0(5, port))
-#define ICL_PORT_TX_DW5_AUX(port) _MMIO(_ICL_PORT_TX_DW_AUX(5, port))
-#define ICL_PORT_TX_DW5_GRP(port) _MMIO(_ICL_PORT_TX_DW_GRP(5, port))
-#define ICL_PORT_TX_DW5_LN0(port) _MMIO(_ICL_PORT_TX_DW_LN(5, 0, port))
+#define ICL_PORT_TX_DW5_AUX(phy) _MMIO(_ICL_PORT_TX_DW_AUX(5, phy))
+#define ICL_PORT_TX_DW5_GRP(phy) _MMIO(_ICL_PORT_TX_DW_GRP(5, phy))
+#define ICL_PORT_TX_DW5_LN0(phy) _MMIO(_ICL_PORT_TX_DW_LN(5, 0, phy))
#define TX_TRAINING_EN (1 << 31)
#define TAP2_DISABLE (1 << 30)
#define TAP3_DISABLE (1 << 29)
@@ -1988,10 +1988,10 @@ enum i915_power_well_id {
#define CNL_PORT_TX_DW7_GRP(port) _MMIO(_CNL_PORT_TX_DW_GRP(7, (port)))
#define CNL_PORT_TX_DW7_LN0(port) _MMIO(_CNL_PORT_TX_DW_LN0(7, (port)))
-#define ICL_PORT_TX_DW7_AUX(port) _MMIO(_ICL_PORT_TX_DW_AUX(7, port))
-#define ICL_PORT_TX_DW7_GRP(port) _MMIO(_ICL_PORT_TX_DW_GRP(7, port))
-#define ICL_PORT_TX_DW7_LN0(port) _MMIO(_ICL_PORT_TX_DW_LN(7, 0, port))
-#define ICL_PORT_TX_DW7_LN(ln, port) _MMIO(_ICL_PORT_TX_DW_LN(7, ln, port))
+#define ICL_PORT_TX_DW7_AUX(phy) _MMIO(_ICL_PORT_TX_DW_AUX(7, phy))
+#define ICL_PORT_TX_DW7_GRP(phy) _MMIO(_ICL_PORT_TX_DW_GRP(7, phy))
+#define ICL_PORT_TX_DW7_LN0(phy) _MMIO(_ICL_PORT_TX_DW_LN(7, 0, phy))
+#define ICL_PORT_TX_DW7_LN(ln, phy) _MMIO(_ICL_PORT_TX_DW_LN(7, ln, phy))
#define N_SCALAR(x) ((x) << 24)
#define N_SCALAR_MASK (0x7F << 24)
--
2.17.2
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 33+ messages in thread
* [PATCH v4 4/5] drm/i915: Transition port type checks to phy checks
2019-07-03 23:37 [PATCH v4 0/5] EHL port programming Matt Roper
` (2 preceding siblings ...)
2019-07-03 23:37 ` [PATCH v4 3/5] drm/i915/gen11: Convert combo PHY logic to use new 'enum phy' namespace Matt Roper
@ 2019-07-03 23:37 ` Matt Roper
2019-07-04 0:02 ` [PATCH v5 " Matt Roper
` (2 more replies)
2019-07-03 23:37 ` [PATCH v4 5/5] drm/i915/ehl: Enable DDI-D Matt Roper
` (8 subsequent siblings)
12 siblings, 3 replies; 33+ messages in thread
From: Matt Roper @ 2019-07-03 23:37 UTC (permalink / raw)
To: intel-gfx
Transition the remaining uses of intel_port_is_* over to the equivalent
intel_phy_is_* functions and drop the port functions.
Cc: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
We might want to hold off on merging this one until after TGL lands to
avoid unnecessary conflicts there.
drivers/gpu/drm/i915/display/intel_bios.c | 4 +-
drivers/gpu/drm/i915/display/intel_ddi.c | 49 ++++++++++++-------
drivers/gpu/drm/i915/display/intel_display.c | 38 ++++----------
.../drm/i915/display/intel_display_power.c | 4 +-
drivers/gpu/drm/i915/display/intel_dp.c | 15 +++---
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 11 +++--
drivers/gpu/drm/i915/intel_drv.h | 2 -
7 files changed, 61 insertions(+), 62 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c
index 0c9808132d67..4fdbb5c35d87 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.c
+++ b/drivers/gpu/drm/i915/display/intel_bios.c
@@ -28,6 +28,7 @@
#include <drm/drm_dp_helper.h>
#include <drm/i915_drm.h>
+#include "display/intel_display.h"
#include "display/intel_gmbus.h"
#include "i915_drv.h"
@@ -1733,12 +1734,13 @@ init_vbt_missing_defaults(struct drm_i915_private *dev_priv)
for (port = PORT_A; port < I915_MAX_PORTS; port++) {
struct ddi_vbt_port_info *info =
&dev_priv->vbt.ddi_port_info[port];
+ enum phy phy = intel_port_to_phy(dev_priv, port);
/*
* VBT has the TypeC mode (native,TBT/USB) and we don't want
* to detect it.
*/
- if (intel_port_is_tc(dev_priv, port))
+ if (intel_phy_is_tc(dev_priv, phy))
continue;
info->supports_dvi = (port != PORT_A && port != PORT_E);
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 50dd9d731456..37c8cecb9a6a 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -868,11 +868,12 @@ icl_get_combo_buf_trans(struct drm_i915_private *dev_priv, int type, int rate,
static int intel_ddi_hdmi_level(struct drm_i915_private *dev_priv, enum port port)
{
int n_entries, level, default_entry;
+ enum phy phy = intel_port_to_phy(dev_priv, port);
level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift;
if (INTEL_GEN(dev_priv) >= 11) {
- if (intel_port_is_combophy(dev_priv, port))
+ if (intel_phy_is_combo(dev_priv, phy))
icl_get_combo_buf_trans(dev_priv, INTEL_OUTPUT_HDMI,
0, &n_entries);
else
@@ -1487,9 +1488,10 @@ static void icl_ddi_clock_get(struct intel_encoder *encoder,
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
struct intel_dpll_hw_state *pll_state = &pipe_config->dpll_hw_state;
enum port port = encoder->port;
+ enum phy phy = intel_port_to_phy(dev_priv, port);
int link_clock;
- if (intel_port_is_combophy(dev_priv, port)) {
+ if (intel_phy_is_combo(dev_priv, phy)) {
link_clock = cnl_calc_wrpll_link(dev_priv, pll_state);
} else {
enum intel_dpll_id pll_id = intel_get_shared_dpll_id(dev_priv,
@@ -2086,6 +2088,7 @@ static void intel_ddi_get_power_domains(struct intel_encoder *encoder,
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
struct intel_digital_port *dig_port;
+ enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
/*
* TODO: Add support for MST encoders. Atm, the following should never
@@ -2103,7 +2106,7 @@ static void intel_ddi_get_power_domains(struct intel_encoder *encoder,
* ports.
*/
if (intel_crtc_has_dp_encoder(crtc_state) ||
- intel_port_is_tc(dev_priv, encoder->port))
+ intel_phy_is_tc(dev_priv, phy))
intel_display_power_get(dev_priv,
intel_ddi_main_link_aux_domain(dig_port));
@@ -2228,10 +2231,11 @@ u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder)
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
enum port port = encoder->port;
+ enum phy phy = intel_port_to_phy(dev_priv, port);
int n_entries;
if (INTEL_GEN(dev_priv) >= 11) {
- if (intel_port_is_combophy(dev_priv, port))
+ if (intel_phy_is_combo(dev_priv, phy))
icl_get_combo_buf_trans(dev_priv, encoder->type,
intel_dp->link_rate, &n_entries);
else
@@ -2664,9 +2668,9 @@ static void icl_ddi_vswing_sequence(struct intel_encoder *encoder,
enum intel_output_type type)
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
- enum port port = encoder->port;
+ enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
- if (intel_port_is_combophy(dev_priv, port))
+ if (intel_phy_is_combo(dev_priv, phy))
icl_combo_phy_ddi_vswing_sequence(encoder, level, type);
else
icl_mg_phy_ddi_vswing_sequence(encoder, link_clock, level);
@@ -2729,12 +2733,13 @@ u32 ddi_signal_levels(struct intel_dp *intel_dp)
static inline
u32 icl_dpclka_cfgcr0_clk_off(struct drm_i915_private *dev_priv,
- enum port port)
+ enum phy phy)
{
- if (intel_port_is_combophy(dev_priv, port)) {
- return ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(port);
- } else if (intel_port_is_tc(dev_priv, port)) {
- enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
+ if (intel_phy_is_combo(dev_priv, phy)) {
+ return ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
+ } else if (intel_phy_is_tc(dev_priv, phy)) {
+ enum tc_port tc_port = intel_port_to_tc(dev_priv,
+ (enum port)phy);
return ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port);
}
@@ -2876,6 +2881,7 @@ static void intel_ddi_clk_select(struct intel_encoder *encoder,
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
enum port port = encoder->port;
+ enum phy phy = intel_port_to_phy(dev_priv, port);
u32 val;
const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
@@ -2885,7 +2891,7 @@ static void intel_ddi_clk_select(struct intel_encoder *encoder,
mutex_lock(&dev_priv->dpll_lock);
if (INTEL_GEN(dev_priv) >= 11) {
- if (!intel_port_is_combophy(dev_priv, port))
+ if (!intel_phy_is_combo(dev_priv, phy))
I915_WRITE(DDI_CLK_SEL(port),
icl_pll_to_ddi_clk_sel(encoder, crtc_state));
} else if (IS_CANNONLAKE(dev_priv)) {
@@ -2925,9 +2931,10 @@ static void intel_ddi_clk_disable(struct intel_encoder *encoder)
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
enum port port = encoder->port;
+ enum phy phy = intel_port_to_phy(dev_priv, port);
if (INTEL_GEN(dev_priv) >= 11) {
- if (!intel_port_is_combophy(dev_priv, port))
+ if (!intel_phy_is_combo(dev_priv, phy))
I915_WRITE(DDI_CLK_SEL(port), DDI_CLK_SEL_NONE);
} else if (IS_CANNONLAKE(dev_priv)) {
I915_WRITE(DPCLKA_CFGCR0, I915_READ(DPCLKA_CFGCR0) |
@@ -3134,7 +3141,7 @@ static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder,
intel_ddi_clk_select(encoder, crtc_state);
- if (!intel_port_is_tc(dev_priv, port) ||
+ if (!intel_phy_is_tc(dev_priv, phy) ||
dig_port->tc_mode != TC_PORT_TBT_ALT)
intel_display_power_get(dev_priv,
dig_port->ddi_io_power_domain);
@@ -3152,7 +3159,7 @@ static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder,
else
intel_prepare_dp_ddi_buffers(encoder, crtc_state);
- if (intel_port_is_combophy(dev_priv, port)) {
+ if (intel_phy_is_combo(dev_priv, phy)) {
bool lane_reversal =
dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL;
@@ -3304,6 +3311,7 @@ static void intel_ddi_post_disable_dp(struct intel_encoder *encoder,
struct intel_dp *intel_dp = &dig_port->dp;
bool is_mst = intel_crtc_has_type(old_crtc_state,
INTEL_OUTPUT_DP_MST);
+ enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
if (!is_mst) {
intel_ddi_disable_pipe_clock(old_crtc_state);
@@ -3319,7 +3327,7 @@ static void intel_ddi_post_disable_dp(struct intel_encoder *encoder,
intel_edp_panel_vdd_on(intel_dp);
intel_edp_panel_off(intel_dp);
- if (!intel_port_is_tc(dev_priv, encoder->port) ||
+ if (!intel_phy_is_tc(dev_priv, phy) ||
dig_port->tc_mode != TC_PORT_TBT_ALT)
intel_display_power_put_unchecked(dev_priv,
dig_port->ddi_io_power_domain);
@@ -3669,8 +3677,9 @@ intel_ddi_pre_pll_enable(struct intel_encoder *encoder,
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
- bool is_tc_port = intel_port_is_tc(dev_priv, encoder->port);
enum port port = encoder->port;
+ enum phy phy = intel_port_to_phy(dev_priv, port);
+ bool is_tc_port = intel_phy_is_tc(dev_priv, phy);
if (is_tc_port)
intel_tc_port_get_link(dig_port, crtc_state->lane_count);
@@ -3700,7 +3709,8 @@ intel_ddi_post_pll_disable(struct intel_encoder *encoder,
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
- bool is_tc_port = intel_port_is_tc(dev_priv, encoder->port);
+ enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
+ bool is_tc_port = intel_phy_is_tc(dev_priv, phy);
if (intel_crtc_has_dp_encoder(crtc_state) || is_tc_port)
intel_display_power_put_unchecked(dev_priv,
@@ -4214,6 +4224,7 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
struct drm_encoder *encoder;
bool init_hdmi, init_dp, init_lspcon = false;
enum pipe pipe;
+ enum phy phy = intel_port_to_phy(dev_priv, port);
init_hdmi = port_info->supports_dvi || port_info->supports_hdmi;
init_dp = port_info->supports_dp;
@@ -4277,7 +4288,7 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
intel_dig_port->max_lanes = intel_ddi_max_lanes(intel_dig_port);
intel_dig_port->aux_ch = intel_bios_port_aux_ch(dev_priv, port);
- if (intel_port_is_tc(dev_priv, port)) {
+ if (intel_phy_is_tc(dev_priv, phy)) {
bool is_legacy = !port_info->supports_typec_usb &&
!port_info->supports_tbt;
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 4a85abef93e7..550530cc2d24 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -6649,20 +6649,6 @@ static void i9xx_pfit_enable(const struct intel_crtc_state *crtc_state)
I915_WRITE(BCLRPAT(crtc->pipe), 0);
}
-bool intel_port_is_combophy(struct drm_i915_private *dev_priv, enum port port)
-{
- if (port == PORT_NONE)
- return false;
-
- if (IS_ELKHARTLAKE(dev_priv))
- return port <= PORT_C;
-
- if (INTEL_GEN(dev_priv) >= 11)
- return port <= PORT_B;
-
- return false;
-}
-
bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy phy)
{
if (phy == PHY_NONE)
@@ -6677,14 +6663,6 @@ bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy phy)
return false;
}
-bool intel_port_is_tc(struct drm_i915_private *dev_priv, enum port port)
-{
- if (INTEL_GEN(dev_priv) >= 11 && !IS_ELKHARTLAKE(dev_priv))
- return port >= PORT_C && port <= PORT_F;
-
- return false;
-}
-
bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy)
{
if (INTEL_GEN(dev_priv) >= 11 && !IS_ELKHARTLAKE(dev_priv))
@@ -6734,8 +6712,9 @@ enum intel_display_power_domain
intel_aux_power_domain(struct intel_digital_port *dig_port)
{
struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
+ enum phy phy = intel_port_to_phy(dev_priv, dig_port->base.port);
- if (intel_port_is_tc(dev_priv, dig_port->base.port) &&
+ if (intel_phy_is_tc(dev_priv, phy) &&
dig_port->tc_mode == TC_PORT_TBT_ALT) {
switch (dig_port->aux_ch) {
case AUX_CH_C:
@@ -10069,16 +10048,17 @@ static void icelake_get_ddi_pll(struct drm_i915_private *dev_priv,
enum port port,
struct intel_crtc_state *pipe_config)
{
+ enum phy phy = intel_port_to_phy(dev_priv, port);
enum icl_port_dpll_id port_dpll_id;
enum intel_dpll_id id;
u32 temp;
- if (intel_port_is_combophy(dev_priv, port)) {
+ if (intel_phy_is_combo(dev_priv, phy)) {
temp = I915_READ(DPCLKA_CFGCR0_ICL) &
- DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
- id = temp >> DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port);
+ ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
+ id = temp >> ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy);
port_dpll_id = ICL_PORT_DPLL_DEFAULT;
- } else if (intel_port_is_tc(dev_priv, port)) {
+ } else if (intel_phy_is_tc(dev_priv, phy)) {
u32 clk_sel = I915_READ(DDI_CLK_SEL(port)) & DDI_CLK_SEL_MASK;
if (clk_sel == DDI_CLK_SEL_MG) {
@@ -16935,9 +16915,11 @@ intel_modeset_setup_hw_state(struct drm_device *dev,
/* Sanitize the TypeC port mode upfront, encoders depend on this */
for_each_intel_encoder(dev, encoder) {
+ enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
+
/* We need to sanitize only the MST primary port. */
if (encoder->type != INTEL_OUTPUT_DP_MST &&
- intel_port_is_tc(dev_priv, encoder->port))
+ intel_phy_is_tc(dev_priv, phy))
intel_tc_port_sanitize(enc_to_dig_port(&encoder->base));
}
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index 64627c117c31..0f6ea4d6d1ef 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -487,7 +487,9 @@ static void icl_tc_port_assert_ref_held(struct drm_i915_private *dev_priv,
aux_ch = icl_tc_phy_aux_ch(dev_priv, power_well);
for_each_intel_encoder(&dev_priv->drm, encoder) {
- if (!intel_port_is_tc(dev_priv, encoder->port))
+ enum phy phy = intel_port_to_phy(encoder->port);
+
+ if (!intel_phy_is_tc(dev_priv, phy))
continue;
/* We'll check the MST primary port */
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 8f7188d71d08..67603a247e8a 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -297,9 +297,9 @@ static int icl_max_source_rate(struct intel_dp *intel_dp)
{
struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
- enum port port = dig_port->base.port;
+ enum phy phy = intel_port_to_phy(dev_priv, dig_port->base.port);
- if (intel_port_is_combophy(dev_priv, port) &&
+ if (intel_phy_is_combo(dev_priv, phy) &&
!IS_ELKHARTLAKE(dev_priv) &&
!intel_dp_is_edp(intel_dp))
return 540000;
@@ -1192,7 +1192,8 @@ intel_dp_aux_xfer(struct intel_dp *intel_dp,
struct drm_i915_private *i915 =
to_i915(intel_dig_port->base.base.dev);
struct intel_uncore *uncore = &i915->uncore;
- bool is_tc_port = intel_port_is_tc(i915, intel_dig_port->base.port);
+ enum phy phy = intel_port_to_phy(i915, intel_dig_port->base.port);
+ bool is_tc_port = intel_phy_is_tc(i915, phy);
i915_reg_t ch_ctl, ch_data[5];
u32 aux_clock_divider;
enum intel_display_power_domain aux_domain =
@@ -5211,10 +5212,11 @@ static bool icl_digital_port_connected(struct intel_encoder *encoder)
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
+ enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
- if (intel_port_is_combophy(dev_priv, encoder->port))
+ if (intel_phy_is_combo(dev_priv, phy))
return icl_combo_port_connected(dev_priv, dig_port);
- else if (intel_port_is_tc(dev_priv, encoder->port))
+ else if (intel_phy_is_tc(dev_priv, phy))
return intel_tc_port_connected(dig_port);
else
MISSING_CASE(encoder->hpd_pin);
@@ -7118,6 +7120,7 @@ intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
struct drm_device *dev = intel_encoder->base.dev;
struct drm_i915_private *dev_priv = to_i915(dev);
enum port port = intel_encoder->port;
+ enum phy phy = intel_port_to_phy(dev_priv, port);
int type;
/* Initialize the work for modeset in case of link train failure */
@@ -7144,7 +7147,7 @@ intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
* Currently we don't support eDP on TypeC ports, although in
* theory it could work on TypeC legacy ports.
*/
- WARN_ON(intel_port_is_tc(dev_priv, port));
+ WARN_ON(intel_phy_is_tc(dev_priv, phy));
type = DRM_MODE_CONNECTOR_eDP;
} else {
type = DRM_MODE_CONNECTOR_DisplayPort;
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index f953971e7c3b..f8782c24c447 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -2580,7 +2580,8 @@ static bool icl_calc_dpll_state(struct intel_crtc_state *crtc_state,
struct skl_wrpll_params pll_params = { 0 };
bool ret;
- if (intel_port_is_tc(dev_priv, encoder->port))
+ if (intel_phy_is_tc(dev_priv, intel_port_to_phy(dev_priv,
+ encoder->port)))
ret = icl_calc_tbt_pll(crtc_state, &pll_params);
else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) ||
intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI))
@@ -2993,14 +2994,14 @@ static bool icl_get_dplls(struct intel_atomic_state *state,
struct intel_encoder *encoder)
{
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
- enum port port = encoder->port;
+ enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
- if (intel_port_is_combophy(dev_priv, port))
+ if (intel_phy_is_combo(dev_priv, phy))
return icl_get_combo_phy_dpll(state, crtc, encoder);
- else if (intel_port_is_tc(dev_priv, port))
+ else if (intel_phy_is_tc(dev_priv, phy))
return icl_get_tc_phy_dplls(state, crtc, encoder);
- MISSING_CASE(port);
+ MISSING_CASE(phy);
return false;
}
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 815c26c0b98c..770f9f6aad84 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1492,9 +1492,7 @@ void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv);
void intel_encoder_destroy(struct drm_encoder *encoder);
struct drm_display_mode *
intel_encoder_current_mode(struct intel_encoder *encoder);
-bool intel_port_is_combophy(struct drm_i915_private *dev_priv, enum port port);
bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy phy);
-bool intel_port_is_tc(struct drm_i915_private *dev_priv, enum port port);
bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy);
enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv,
enum port port);
--
2.17.2
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 33+ messages in thread
* [PATCH v4 5/5] drm/i915/ehl: Enable DDI-D
2019-07-03 23:37 [PATCH v4 0/5] EHL port programming Matt Roper
` (3 preceding siblings ...)
2019-07-03 23:37 ` [PATCH v4 4/5] drm/i915: Transition port type checks to phy checks Matt Roper
@ 2019-07-03 23:37 ` Matt Roper
2019-07-03 23:51 ` ✗ Fi.CI.BAT: failure for EHL port programming (rev4) Patchwork
` (7 subsequent siblings)
12 siblings, 0 replies; 33+ messages in thread
From: Matt Roper @ 2019-07-03 23:37 UTC (permalink / raw)
To: intel-gfx
EHL has four DDI's (DDI-A and DDI-D share combo PHY A).
Cc: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 550530cc2d24..89c8fc22924a 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -15288,6 +15288,7 @@ static void intel_setup_outputs(struct drm_i915_private *dev_priv)
intel_ddi_init(dev_priv, PORT_A);
intel_ddi_init(dev_priv, PORT_B);
intel_ddi_init(dev_priv, PORT_C);
+ intel_ddi_init(dev_priv, PORT_D);
icl_dsi_init(dev_priv);
} else if (INTEL_GEN(dev_priv) >= 11) {
intel_ddi_init(dev_priv, PORT_A);
--
2.17.2
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 33+ messages in thread
* ✗ Fi.CI.BAT: failure for EHL port programming (rev4)
2019-07-03 23:37 [PATCH v4 0/5] EHL port programming Matt Roper
` (4 preceding siblings ...)
2019-07-03 23:37 ` [PATCH v4 5/5] drm/i915/ehl: Enable DDI-D Matt Roper
@ 2019-07-03 23:51 ` Patchwork
2019-07-03 23:56 ` [PATCH v4 0/5] EHL port programming Souza, Jose
` (6 subsequent siblings)
12 siblings, 0 replies; 33+ messages in thread
From: Patchwork @ 2019-07-03 23:51 UTC (permalink / raw)
To: Matt Roper; +Cc: intel-gfx
== Series Details ==
Series: EHL port programming (rev4)
URL : https://patchwork.freedesktop.org/series/62492/
State : failure
== Summary ==
CALL scripts/checksyscalls.sh
CALL scripts/atomic/check-atomics.sh
DESCEND objtool
CHK include/generated/compile.h
AR drivers/gpu/drm/i915/built-in.a
CC [M] drivers/gpu/drm/i915/header_test_i915_active_types.o
CC [M] drivers/gpu/drm/i915/header_test_i915_debugfs.o
CC [M] drivers/gpu/drm/i915/header_test_i915_drv.o
CC [M] drivers/gpu/drm/i915/header_test_i915_fixed.o
CC [M] drivers/gpu/drm/i915/header_test_i915_gem_gtt.o
CC [M] drivers/gpu/drm/i915/header_test_i915_globals.o
CC [M] drivers/gpu/drm/i915/header_test_i915_irq.o
CC [M] drivers/gpu/drm/i915/header_test_i915_params.o
CC [M] drivers/gpu/drm/i915/header_test_i915_priolist_types.o
CC [M] drivers/gpu/drm/i915/header_test_i915_pvinfo.o
CC [M] drivers/gpu/drm/i915/header_test_i915_reg.o
CC [M] drivers/gpu/drm/i915/header_test_i915_scheduler_types.o
CC [M] drivers/gpu/drm/i915/header_test_i915_utils.o
CC [M] drivers/gpu/drm/i915/header_test_i915_vgpu.o
CC [M] drivers/gpu/drm/i915/header_test_intel_csr.o
CC [M] drivers/gpu/drm/i915/header_test_intel_drv.o
CC [M] drivers/gpu/drm/i915/header_test_intel_guc_ct.o
CC [M] drivers/gpu/drm/i915/header_test_intel_guc_fwif.o
CC [M] drivers/gpu/drm/i915/header_test_intel_guc_reg.o
CC [M] drivers/gpu/drm/i915/header_test_intel_gvt.o
CC [M] drivers/gpu/drm/i915/header_test_intel_pm.o
CC [M] drivers/gpu/drm/i915/header_test_intel_runtime_pm.o
CC [M] drivers/gpu/drm/i915/header_test_intel_sideband.o
CC [M] drivers/gpu/drm/i915/header_test_intel_uc_fw.o
CC [M] drivers/gpu/drm/i915/header_test_intel_uncore.o
CC [M] drivers/gpu/drm/i915/header_test_intel_wakeref.o
CC [M] drivers/gpu/drm/i915/display/intel_display_power.o
drivers/gpu/drm/i915/display/intel_display_power.c: In function ‘icl_tc_port_assert_ref_held’:
drivers/gpu/drm/i915/display/intel_display_power.c:490:36: error: incompatible type for argument 1 of ‘intel_port_to_phy’
enum phy phy = intel_port_to_phy(encoder->port);
^~~~~~~
In file included from ./drivers/gpu/drm/i915/i915_drv.h:67:0,
from drivers/gpu/drm/i915/display/intel_display_power.c:11:
./drivers/gpu/drm/i915/display/intel_display.h:378:10: note: expected ‘struct drm_i915_private *’ but argument is of type ‘enum port’
enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port);
^~~~~~~~~~~~~~~~~
drivers/gpu/drm/i915/display/intel_display_power.c:490:18: error: too few arguments to function ‘intel_port_to_phy’
enum phy phy = intel_port_to_phy(encoder->port);
^~~~~~~~~~~~~~~~~
In file included from ./drivers/gpu/drm/i915/i915_drv.h:67:0,
from drivers/gpu/drm/i915/display/intel_display_power.c:11:
./drivers/gpu/drm/i915/display/intel_display.h:378:10: note: declared here
enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port);
^~~~~~~~~~~~~~~~~
scripts/Makefile.build:278: recipe for target 'drivers/gpu/drm/i915/display/intel_display_power.o' failed
make[4]: *** [drivers/gpu/drm/i915/display/intel_display_power.o] Error 1
scripts/Makefile.build:489: recipe for target 'drivers/gpu/drm/i915' failed
make[3]: *** [drivers/gpu/drm/i915] Error 2
scripts/Makefile.build:489: recipe for target 'drivers/gpu/drm' failed
make[2]: *** [drivers/gpu/drm] Error 2
scripts/Makefile.build:489: recipe for target 'drivers/gpu' failed
make[1]: *** [drivers/gpu] Error 2
Makefile:1071: recipe for target 'drivers' failed
make: *** [drivers] Error 2
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: [PATCH v4 0/5] EHL port programming
2019-07-03 23:37 [PATCH v4 0/5] EHL port programming Matt Roper
` (5 preceding siblings ...)
2019-07-03 23:51 ` ✗ Fi.CI.BAT: failure for EHL port programming (rev4) Patchwork
@ 2019-07-03 23:56 ` Souza, Jose
2019-07-04 0:40 ` ✗ Fi.CI.CHECKPATCH: warning for EHL port programming (rev5) Patchwork
` (5 subsequent siblings)
12 siblings, 0 replies; 33+ messages in thread
From: Souza, Jose @ 2019-07-03 23:56 UTC (permalink / raw)
To: Roper, Matthew D, intel-gfx, De Marchi, Lucas
On Wed, 2019-07-03 at 16:37 -0700, Matt Roper wrote:
> Previous series revisions were here:
> v3:
> https://lists.freedesktop.org/archives/intel-gfx/2019-June/203287.html
> v1/2:
> https://lists.freedesktop.org/archives/intel-gfx/2019-June/202776.html
>
> Only two patches from the previous series have yet to land; this
> revision splits up the first of those into four separate patches to
> ease
> the review process a bit.
>
> This revision also updates a handful of combo PHY registers to use
> the
> new namespace that were missed in the previous iteration and caught
> by
> Jose.
>
> As before, this series doesn't even try to touch the TC code (aside
> from
> the type check function). EHL has no combo PHYs, so it's probably
EHL has no TC combo phys
> better to wait until TGL support lands in the tree before tackling
> that
> to avoid causing unnecessary conflicts. Even patch #4 of this series
> may want to wait until TGL lands before being merged.
>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Should it wait? Thoughts?
> Cc: José Roberto de Souza <jose.souza@intel.com>
>
> Matt Roper (5):
> drm/i915/gen11: Start distinguishing 'phy' from 'port'
> drm/i915/gen11: Program DPCLKA_CFGCR0_ICL according to PHY
> drm/i915/gen11: Convert combo PHY logic to use new 'enum phy'
> namespace
> drm/i915: Transition port type checks to phy checks
> drm/i915/ehl: Enable DDI-D
>
> drivers/gpu/drm/i915/display/icl_dsi.c | 136 ++++++++------
> ---
> drivers/gpu/drm/i915/display/intel_bios.c | 4 +-
> .../gpu/drm/i915/display/intel_combo_phy.c | 143 +++++++++-------
> --
> .../gpu/drm/i915/display/intel_combo_phy.h | 3 +-
> drivers/gpu/drm/i915/display/intel_ddi.c | 130 +++++++++-------
> drivers/gpu/drm/i915/display/intel_display.c | 39 +++--
> drivers/gpu/drm/i915/display/intel_display.h | 20 +++
> .../drm/i915/display/intel_display_power.c | 20 +--
> drivers/gpu/drm/i915/display/intel_dp.c | 15 +-
> drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 11 +-
> drivers/gpu/drm/i915/display/intel_dsi.h | 12 +-
> drivers/gpu/drm/i915/i915_reg.h | 86 ++++++-----
> drivers/gpu/drm/i915/intel_drv.h | 4 +-
> 13 files changed, 348 insertions(+), 275 deletions(-)
>
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 33+ messages in thread
* [PATCH v5 4/5] drm/i915: Transition port type checks to phy checks
2019-07-03 23:37 ` [PATCH v4 4/5] drm/i915: Transition port type checks to phy checks Matt Roper
@ 2019-07-04 0:02 ` Matt Roper
2019-07-08 13:13 ` Ville Syrjälä
2019-07-04 16:07 ` [PATCH v4 " kbuild test robot
2019-07-09 1:00 ` Souza, Jose
2 siblings, 1 reply; 33+ messages in thread
From: Matt Roper @ 2019-07-04 0:02 UTC (permalink / raw)
To: intel-gfx; +Cc: Lucas De Marchi
Transition the remaining uses of intel_port_is_* over to the equivalent
intel_phy_is_* functions and drop the port functions.
v5: Fix a call in a debug function that's only called when
CONFIG_DRM_I915_DEBUG_RUNTIME_PM is on. (CI)
Cc: José Roberto de Souza <jose.souza@intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
To avoid conflicts with in-flight TGL patches, we may want to hold off
on merging this one until TGL lands?
drivers/gpu/drm/i915/display/intel_bios.c | 4 +-
drivers/gpu/drm/i915/display/intel_ddi.c | 49 ++++++++++++-------
drivers/gpu/drm/i915/display/intel_display.c | 38 ++++----------
.../drm/i915/display/intel_display_power.c | 4 +-
drivers/gpu/drm/i915/display/intel_dp.c | 15 +++---
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 11 +++--
drivers/gpu/drm/i915/intel_drv.h | 2 -
7 files changed, 61 insertions(+), 62 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c
index 0c9808132d67..4fdbb5c35d87 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.c
+++ b/drivers/gpu/drm/i915/display/intel_bios.c
@@ -28,6 +28,7 @@
#include <drm/drm_dp_helper.h>
#include <drm/i915_drm.h>
+#include "display/intel_display.h"
#include "display/intel_gmbus.h"
#include "i915_drv.h"
@@ -1733,12 +1734,13 @@ init_vbt_missing_defaults(struct drm_i915_private *dev_priv)
for (port = PORT_A; port < I915_MAX_PORTS; port++) {
struct ddi_vbt_port_info *info =
&dev_priv->vbt.ddi_port_info[port];
+ enum phy phy = intel_port_to_phy(dev_priv, port);
/*
* VBT has the TypeC mode (native,TBT/USB) and we don't want
* to detect it.
*/
- if (intel_port_is_tc(dev_priv, port))
+ if (intel_phy_is_tc(dev_priv, phy))
continue;
info->supports_dvi = (port != PORT_A && port != PORT_E);
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 50dd9d731456..37c8cecb9a6a 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -868,11 +868,12 @@ icl_get_combo_buf_trans(struct drm_i915_private *dev_priv, int type, int rate,
static int intel_ddi_hdmi_level(struct drm_i915_private *dev_priv, enum port port)
{
int n_entries, level, default_entry;
+ enum phy phy = intel_port_to_phy(dev_priv, port);
level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift;
if (INTEL_GEN(dev_priv) >= 11) {
- if (intel_port_is_combophy(dev_priv, port))
+ if (intel_phy_is_combo(dev_priv, phy))
icl_get_combo_buf_trans(dev_priv, INTEL_OUTPUT_HDMI,
0, &n_entries);
else
@@ -1487,9 +1488,10 @@ static void icl_ddi_clock_get(struct intel_encoder *encoder,
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
struct intel_dpll_hw_state *pll_state = &pipe_config->dpll_hw_state;
enum port port = encoder->port;
+ enum phy phy = intel_port_to_phy(dev_priv, port);
int link_clock;
- if (intel_port_is_combophy(dev_priv, port)) {
+ if (intel_phy_is_combo(dev_priv, phy)) {
link_clock = cnl_calc_wrpll_link(dev_priv, pll_state);
} else {
enum intel_dpll_id pll_id = intel_get_shared_dpll_id(dev_priv,
@@ -2086,6 +2088,7 @@ static void intel_ddi_get_power_domains(struct intel_encoder *encoder,
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
struct intel_digital_port *dig_port;
+ enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
/*
* TODO: Add support for MST encoders. Atm, the following should never
@@ -2103,7 +2106,7 @@ static void intel_ddi_get_power_domains(struct intel_encoder *encoder,
* ports.
*/
if (intel_crtc_has_dp_encoder(crtc_state) ||
- intel_port_is_tc(dev_priv, encoder->port))
+ intel_phy_is_tc(dev_priv, phy))
intel_display_power_get(dev_priv,
intel_ddi_main_link_aux_domain(dig_port));
@@ -2228,10 +2231,11 @@ u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder)
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
enum port port = encoder->port;
+ enum phy phy = intel_port_to_phy(dev_priv, port);
int n_entries;
if (INTEL_GEN(dev_priv) >= 11) {
- if (intel_port_is_combophy(dev_priv, port))
+ if (intel_phy_is_combo(dev_priv, phy))
icl_get_combo_buf_trans(dev_priv, encoder->type,
intel_dp->link_rate, &n_entries);
else
@@ -2664,9 +2668,9 @@ static void icl_ddi_vswing_sequence(struct intel_encoder *encoder,
enum intel_output_type type)
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
- enum port port = encoder->port;
+ enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
- if (intel_port_is_combophy(dev_priv, port))
+ if (intel_phy_is_combo(dev_priv, phy))
icl_combo_phy_ddi_vswing_sequence(encoder, level, type);
else
icl_mg_phy_ddi_vswing_sequence(encoder, link_clock, level);
@@ -2729,12 +2733,13 @@ u32 ddi_signal_levels(struct intel_dp *intel_dp)
static inline
u32 icl_dpclka_cfgcr0_clk_off(struct drm_i915_private *dev_priv,
- enum port port)
+ enum phy phy)
{
- if (intel_port_is_combophy(dev_priv, port)) {
- return ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(port);
- } else if (intel_port_is_tc(dev_priv, port)) {
- enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
+ if (intel_phy_is_combo(dev_priv, phy)) {
+ return ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
+ } else if (intel_phy_is_tc(dev_priv, phy)) {
+ enum tc_port tc_port = intel_port_to_tc(dev_priv,
+ (enum port)phy);
return ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port);
}
@@ -2876,6 +2881,7 @@ static void intel_ddi_clk_select(struct intel_encoder *encoder,
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
enum port port = encoder->port;
+ enum phy phy = intel_port_to_phy(dev_priv, port);
u32 val;
const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
@@ -2885,7 +2891,7 @@ static void intel_ddi_clk_select(struct intel_encoder *encoder,
mutex_lock(&dev_priv->dpll_lock);
if (INTEL_GEN(dev_priv) >= 11) {
- if (!intel_port_is_combophy(dev_priv, port))
+ if (!intel_phy_is_combo(dev_priv, phy))
I915_WRITE(DDI_CLK_SEL(port),
icl_pll_to_ddi_clk_sel(encoder, crtc_state));
} else if (IS_CANNONLAKE(dev_priv)) {
@@ -2925,9 +2931,10 @@ static void intel_ddi_clk_disable(struct intel_encoder *encoder)
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
enum port port = encoder->port;
+ enum phy phy = intel_port_to_phy(dev_priv, port);
if (INTEL_GEN(dev_priv) >= 11) {
- if (!intel_port_is_combophy(dev_priv, port))
+ if (!intel_phy_is_combo(dev_priv, phy))
I915_WRITE(DDI_CLK_SEL(port), DDI_CLK_SEL_NONE);
} else if (IS_CANNONLAKE(dev_priv)) {
I915_WRITE(DPCLKA_CFGCR0, I915_READ(DPCLKA_CFGCR0) |
@@ -3134,7 +3141,7 @@ static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder,
intel_ddi_clk_select(encoder, crtc_state);
- if (!intel_port_is_tc(dev_priv, port) ||
+ if (!intel_phy_is_tc(dev_priv, phy) ||
dig_port->tc_mode != TC_PORT_TBT_ALT)
intel_display_power_get(dev_priv,
dig_port->ddi_io_power_domain);
@@ -3152,7 +3159,7 @@ static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder,
else
intel_prepare_dp_ddi_buffers(encoder, crtc_state);
- if (intel_port_is_combophy(dev_priv, port)) {
+ if (intel_phy_is_combo(dev_priv, phy)) {
bool lane_reversal =
dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL;
@@ -3304,6 +3311,7 @@ static void intel_ddi_post_disable_dp(struct intel_encoder *encoder,
struct intel_dp *intel_dp = &dig_port->dp;
bool is_mst = intel_crtc_has_type(old_crtc_state,
INTEL_OUTPUT_DP_MST);
+ enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
if (!is_mst) {
intel_ddi_disable_pipe_clock(old_crtc_state);
@@ -3319,7 +3327,7 @@ static void intel_ddi_post_disable_dp(struct intel_encoder *encoder,
intel_edp_panel_vdd_on(intel_dp);
intel_edp_panel_off(intel_dp);
- if (!intel_port_is_tc(dev_priv, encoder->port) ||
+ if (!intel_phy_is_tc(dev_priv, phy) ||
dig_port->tc_mode != TC_PORT_TBT_ALT)
intel_display_power_put_unchecked(dev_priv,
dig_port->ddi_io_power_domain);
@@ -3669,8 +3677,9 @@ intel_ddi_pre_pll_enable(struct intel_encoder *encoder,
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
- bool is_tc_port = intel_port_is_tc(dev_priv, encoder->port);
enum port port = encoder->port;
+ enum phy phy = intel_port_to_phy(dev_priv, port);
+ bool is_tc_port = intel_phy_is_tc(dev_priv, phy);
if (is_tc_port)
intel_tc_port_get_link(dig_port, crtc_state->lane_count);
@@ -3700,7 +3709,8 @@ intel_ddi_post_pll_disable(struct intel_encoder *encoder,
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
- bool is_tc_port = intel_port_is_tc(dev_priv, encoder->port);
+ enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
+ bool is_tc_port = intel_phy_is_tc(dev_priv, phy);
if (intel_crtc_has_dp_encoder(crtc_state) || is_tc_port)
intel_display_power_put_unchecked(dev_priv,
@@ -4214,6 +4224,7 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
struct drm_encoder *encoder;
bool init_hdmi, init_dp, init_lspcon = false;
enum pipe pipe;
+ enum phy phy = intel_port_to_phy(dev_priv, port);
init_hdmi = port_info->supports_dvi || port_info->supports_hdmi;
init_dp = port_info->supports_dp;
@@ -4277,7 +4288,7 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
intel_dig_port->max_lanes = intel_ddi_max_lanes(intel_dig_port);
intel_dig_port->aux_ch = intel_bios_port_aux_ch(dev_priv, port);
- if (intel_port_is_tc(dev_priv, port)) {
+ if (intel_phy_is_tc(dev_priv, phy)) {
bool is_legacy = !port_info->supports_typec_usb &&
!port_info->supports_tbt;
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 4a85abef93e7..550530cc2d24 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -6649,20 +6649,6 @@ static void i9xx_pfit_enable(const struct intel_crtc_state *crtc_state)
I915_WRITE(BCLRPAT(crtc->pipe), 0);
}
-bool intel_port_is_combophy(struct drm_i915_private *dev_priv, enum port port)
-{
- if (port == PORT_NONE)
- return false;
-
- if (IS_ELKHARTLAKE(dev_priv))
- return port <= PORT_C;
-
- if (INTEL_GEN(dev_priv) >= 11)
- return port <= PORT_B;
-
- return false;
-}
-
bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy phy)
{
if (phy == PHY_NONE)
@@ -6677,14 +6663,6 @@ bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy phy)
return false;
}
-bool intel_port_is_tc(struct drm_i915_private *dev_priv, enum port port)
-{
- if (INTEL_GEN(dev_priv) >= 11 && !IS_ELKHARTLAKE(dev_priv))
- return port >= PORT_C && port <= PORT_F;
-
- return false;
-}
-
bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy)
{
if (INTEL_GEN(dev_priv) >= 11 && !IS_ELKHARTLAKE(dev_priv))
@@ -6734,8 +6712,9 @@ enum intel_display_power_domain
intel_aux_power_domain(struct intel_digital_port *dig_port)
{
struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
+ enum phy phy = intel_port_to_phy(dev_priv, dig_port->base.port);
- if (intel_port_is_tc(dev_priv, dig_port->base.port) &&
+ if (intel_phy_is_tc(dev_priv, phy) &&
dig_port->tc_mode == TC_PORT_TBT_ALT) {
switch (dig_port->aux_ch) {
case AUX_CH_C:
@@ -10069,16 +10048,17 @@ static void icelake_get_ddi_pll(struct drm_i915_private *dev_priv,
enum port port,
struct intel_crtc_state *pipe_config)
{
+ enum phy phy = intel_port_to_phy(dev_priv, port);
enum icl_port_dpll_id port_dpll_id;
enum intel_dpll_id id;
u32 temp;
- if (intel_port_is_combophy(dev_priv, port)) {
+ if (intel_phy_is_combo(dev_priv, phy)) {
temp = I915_READ(DPCLKA_CFGCR0_ICL) &
- DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
- id = temp >> DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port);
+ ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
+ id = temp >> ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy);
port_dpll_id = ICL_PORT_DPLL_DEFAULT;
- } else if (intel_port_is_tc(dev_priv, port)) {
+ } else if (intel_phy_is_tc(dev_priv, phy)) {
u32 clk_sel = I915_READ(DDI_CLK_SEL(port)) & DDI_CLK_SEL_MASK;
if (clk_sel == DDI_CLK_SEL_MG) {
@@ -16935,9 +16915,11 @@ intel_modeset_setup_hw_state(struct drm_device *dev,
/* Sanitize the TypeC port mode upfront, encoders depend on this */
for_each_intel_encoder(dev, encoder) {
+ enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
+
/* We need to sanitize only the MST primary port. */
if (encoder->type != INTEL_OUTPUT_DP_MST &&
- intel_port_is_tc(dev_priv, encoder->port))
+ intel_phy_is_tc(dev_priv, phy))
intel_tc_port_sanitize(enc_to_dig_port(&encoder->base));
}
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index 64627c117c31..8aabfea76d38 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -487,7 +487,9 @@ static void icl_tc_port_assert_ref_held(struct drm_i915_private *dev_priv,
aux_ch = icl_tc_phy_aux_ch(dev_priv, power_well);
for_each_intel_encoder(&dev_priv->drm, encoder) {
- if (!intel_port_is_tc(dev_priv, encoder->port))
+ enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
+
+ if (!intel_phy_is_tc(dev_priv, phy))
continue;
/* We'll check the MST primary port */
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 8f7188d71d08..67603a247e8a 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -297,9 +297,9 @@ static int icl_max_source_rate(struct intel_dp *intel_dp)
{
struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
- enum port port = dig_port->base.port;
+ enum phy phy = intel_port_to_phy(dev_priv, dig_port->base.port);
- if (intel_port_is_combophy(dev_priv, port) &&
+ if (intel_phy_is_combo(dev_priv, phy) &&
!IS_ELKHARTLAKE(dev_priv) &&
!intel_dp_is_edp(intel_dp))
return 540000;
@@ -1192,7 +1192,8 @@ intel_dp_aux_xfer(struct intel_dp *intel_dp,
struct drm_i915_private *i915 =
to_i915(intel_dig_port->base.base.dev);
struct intel_uncore *uncore = &i915->uncore;
- bool is_tc_port = intel_port_is_tc(i915, intel_dig_port->base.port);
+ enum phy phy = intel_port_to_phy(i915, intel_dig_port->base.port);
+ bool is_tc_port = intel_phy_is_tc(i915, phy);
i915_reg_t ch_ctl, ch_data[5];
u32 aux_clock_divider;
enum intel_display_power_domain aux_domain =
@@ -5211,10 +5212,11 @@ static bool icl_digital_port_connected(struct intel_encoder *encoder)
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
+ enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
- if (intel_port_is_combophy(dev_priv, encoder->port))
+ if (intel_phy_is_combo(dev_priv, phy))
return icl_combo_port_connected(dev_priv, dig_port);
- else if (intel_port_is_tc(dev_priv, encoder->port))
+ else if (intel_phy_is_tc(dev_priv, phy))
return intel_tc_port_connected(dig_port);
else
MISSING_CASE(encoder->hpd_pin);
@@ -7118,6 +7120,7 @@ intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
struct drm_device *dev = intel_encoder->base.dev;
struct drm_i915_private *dev_priv = to_i915(dev);
enum port port = intel_encoder->port;
+ enum phy phy = intel_port_to_phy(dev_priv, port);
int type;
/* Initialize the work for modeset in case of link train failure */
@@ -7144,7 +7147,7 @@ intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
* Currently we don't support eDP on TypeC ports, although in
* theory it could work on TypeC legacy ports.
*/
- WARN_ON(intel_port_is_tc(dev_priv, port));
+ WARN_ON(intel_phy_is_tc(dev_priv, phy));
type = DRM_MODE_CONNECTOR_eDP;
} else {
type = DRM_MODE_CONNECTOR_DisplayPort;
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index f953971e7c3b..f8782c24c447 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -2580,7 +2580,8 @@ static bool icl_calc_dpll_state(struct intel_crtc_state *crtc_state,
struct skl_wrpll_params pll_params = { 0 };
bool ret;
- if (intel_port_is_tc(dev_priv, encoder->port))
+ if (intel_phy_is_tc(dev_priv, intel_port_to_phy(dev_priv,
+ encoder->port)))
ret = icl_calc_tbt_pll(crtc_state, &pll_params);
else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) ||
intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI))
@@ -2993,14 +2994,14 @@ static bool icl_get_dplls(struct intel_atomic_state *state,
struct intel_encoder *encoder)
{
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
- enum port port = encoder->port;
+ enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
- if (intel_port_is_combophy(dev_priv, port))
+ if (intel_phy_is_combo(dev_priv, phy))
return icl_get_combo_phy_dpll(state, crtc, encoder);
- else if (intel_port_is_tc(dev_priv, port))
+ else if (intel_phy_is_tc(dev_priv, phy))
return icl_get_tc_phy_dplls(state, crtc, encoder);
- MISSING_CASE(port);
+ MISSING_CASE(phy);
return false;
}
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 815c26c0b98c..770f9f6aad84 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1492,9 +1492,7 @@ void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv);
void intel_encoder_destroy(struct drm_encoder *encoder);
struct drm_display_mode *
intel_encoder_current_mode(struct intel_encoder *encoder);
-bool intel_port_is_combophy(struct drm_i915_private *dev_priv, enum port port);
bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy phy);
-bool intel_port_is_tc(struct drm_i915_private *dev_priv, enum port port);
bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy);
enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv,
enum port port);
--
2.17.2
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 33+ messages in thread
* ✗ Fi.CI.CHECKPATCH: warning for EHL port programming (rev5)
2019-07-03 23:37 [PATCH v4 0/5] EHL port programming Matt Roper
` (6 preceding siblings ...)
2019-07-03 23:56 ` [PATCH v4 0/5] EHL port programming Souza, Jose
@ 2019-07-04 0:40 ` Patchwork
2019-07-04 0:43 ` ✗ Fi.CI.SPARSE: " Patchwork
` (4 subsequent siblings)
12 siblings, 0 replies; 33+ messages in thread
From: Patchwork @ 2019-07-04 0:40 UTC (permalink / raw)
To: Matt Roper; +Cc: intel-gfx
== Series Details ==
Series: EHL port programming (rev5)
URL : https://patchwork.freedesktop.org/series/62492/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
248b2ac735b0 drm/i915/gen11: Start distinguishing 'phy' from 'port'
5448b97e345e drm/i915/gen11: Program DPCLKA_CFGCR0_ICL according to PHY
-:193: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'tc_port' - possible side-effects?
#193: FILE: drivers/gpu/drm/i915/i915_reg.h:9692:
+#define ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port) (1 << ((tc_port) == PORT_TC4 ? \
+ 21 : (tc_port) + 12))
-:196: WARNING:LONG_LINE: line over 100 characters
#196: FILE: drivers/gpu/drm/i915/i915_reg.h:9695:
+#define ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy) (3 << ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy))
-:197: WARNING:LONG_LINE: line over 100 characters
#197: FILE: drivers/gpu/drm/i915/i915_reg.h:9696:
+#define ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll, phy) ((pll) << ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy))
total: 0 errors, 2 warnings, 1 checks, 155 lines checked
5b9f9ff3fbfe drm/i915/gen11: Convert combo PHY logic to use new 'enum phy' namespace
-:346: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__phy' - possible side-effects?
#346: FILE: drivers/gpu/drm/i915/display/intel_combo_phy.c:9:
+#define for_each_combo_phy(__dev_priv, __phy) \
+ for ((__phy) = PHY_A; (__phy) < I915_MAX_PHYS; (__phy)++) \
+ for_each_if(intel_phy_is_combo(__dev_priv, __phy))
-:353: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__phy' - possible side-effects?
#353: FILE: drivers/gpu/drm/i915/display/intel_combo_phy.c:13:
+#define for_each_combo_phy_reverse(__dev_priv, __phy) \
+ for ((__phy) = I915_MAX_PHYS; (__phy)-- > PHY_A;) \
+ for_each_if(intel_phy_is_combo(__dev_priv, __phy))
-:826: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__phy' - possible side-effects?
#826: FILE: drivers/gpu/drm/i915/display/intel_display.h:271:
+#define for_each_phy_masked(__phy, __phys_mask) \
+ for ((__phy) = PHY_A; (__phy) < I915_MAX_PHYS; (__phy)++) \
+ for_each_if((__phys_mask) & BIT(__phy))
-:1006: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#1006: FILE: drivers/gpu/drm/i915/i915_reg.h:1880:
+#define CNL_PORT_PCS_DW1_LN0(phy) _MMIO(_PICK(phy, \
_CNL_PORT_PCS_DW1_LN0_AE, \
_CNL_PORT_PCS_DW1_LN0_B, \
_CNL_PORT_PCS_DW1_LN0_C, \
total: 1 errors, 0 warnings, 3 checks, 998 lines checked
c8bffe246539 drm/i915: Transition port type checks to phy checks
e233d250b324 drm/i915/ehl: Enable DDI-D
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 33+ messages in thread
* ✗ Fi.CI.SPARSE: warning for EHL port programming (rev5)
2019-07-03 23:37 [PATCH v4 0/5] EHL port programming Matt Roper
` (7 preceding siblings ...)
2019-07-04 0:40 ` ✗ Fi.CI.CHECKPATCH: warning for EHL port programming (rev5) Patchwork
@ 2019-07-04 0:43 ` Patchwork
2019-07-04 1:18 ` ✓ Fi.CI.BAT: success " Patchwork
` (3 subsequent siblings)
12 siblings, 0 replies; 33+ messages in thread
From: Patchwork @ 2019-07-04 0:43 UTC (permalink / raw)
To: Matt Roper; +Cc: intel-gfx
== Series Details ==
Series: EHL port programming (rev5)
URL : https://patchwork.freedesktop.org/series/62492/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm/i915/gen11: Start distinguishing 'phy' from 'port'
Okay!
Commit: drm/i915/gen11: Program DPCLKA_CFGCR0_ICL according to PHY
+drivers/gpu/drm/i915/display/intel_ddi.c:2756:9: int enum phy versus
+drivers/gpu/drm/i915/display/intel_ddi.c:2756:9: int enum port
+drivers/gpu/drm/i915/display/intel_ddi.c:2756:9: warning: mixing different enum types
+drivers/gpu/drm/i915/display/intel_ddi.c:2775:53: int enum phy versus
+drivers/gpu/drm/i915/display/intel_ddi.c:2775:53: int enum port
+drivers/gpu/drm/i915/display/intel_ddi.c:2775:53: warning: mixing different enum types
+drivers/gpu/drm/i915/display/intel_ddi.c:2790:52: int enum phy versus
+drivers/gpu/drm/i915/display/intel_ddi.c:2790:52: int enum port
+drivers/gpu/drm/i915/display/intel_ddi.c:2790:52: warning: mixing different enum types
+drivers/gpu/drm/i915/display/intel_ddi.c:2855:68: int enum phy versus
+drivers/gpu/drm/i915/display/intel_ddi.c:2855:68: int enum port
+drivers/gpu/drm/i915/display/intel_ddi.c:2855:68: warning: mixing different enum types
+drivers/gpu/drm/i915/display/intel_ddi.c:2869:60: int enum phy versus
+drivers/gpu/drm/i915/display/intel_ddi.c:2869:60: int enum port
+drivers/gpu/drm/i915/display/intel_ddi.c:2869:60: warning: mixing different enum types
Commit: drm/i915/gen11: Convert combo PHY logic to use new 'enum phy' namespace
Okay!
Commit: drm/i915: Transition port type checks to phy checks
-drivers/gpu/drm/i915/display/intel_ddi.c:2761:9: int enum phy versus
-drivers/gpu/drm/i915/display/intel_ddi.c:2761:9: int enum port
-drivers/gpu/drm/i915/display/intel_ddi.c:2761:9: warning: mixing different enum types
-drivers/gpu/drm/i915/display/intel_ddi.c:2780:53: int enum phy versus
-drivers/gpu/drm/i915/display/intel_ddi.c:2780:53: int enum port
-drivers/gpu/drm/i915/display/intel_ddi.c:2780:53: warning: mixing different enum types
-drivers/gpu/drm/i915/display/intel_ddi.c:2795:52: int enum phy versus
-drivers/gpu/drm/i915/display/intel_ddi.c:2795:52: int enum port
-drivers/gpu/drm/i915/display/intel_ddi.c:2795:52: warning: mixing different enum types
-drivers/gpu/drm/i915/display/intel_ddi.c:2860:68: int enum phy versus
-drivers/gpu/drm/i915/display/intel_ddi.c:2860:68: int enum port
-drivers/gpu/drm/i915/display/intel_ddi.c:2860:68: warning: mixing different enum types
-drivers/gpu/drm/i915/display/intel_ddi.c:2874:60: int enum phy versus
-drivers/gpu/drm/i915/display/intel_ddi.c:2874:60: int enum port
-drivers/gpu/drm/i915/display/intel_ddi.c:2874:60: warning: mixing different enum types
Commit: drm/i915/ehl: Enable DDI-D
Okay!
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 33+ messages in thread
* [PATCH v5 2/5] drm/i915/gen11: Program DPCLKA_CFGCR0_ICL according to PHY
2019-07-03 23:37 ` [PATCH v4 2/5] drm/i915/gen11: Program DPCLKA_CFGCR0_ICL according to PHY Matt Roper
@ 2019-07-04 1:06 ` Matt Roper
2019-07-04 9:31 ` Ville Syrjälä
2019-07-09 0:15 ` Souza, Jose
0 siblings, 2 replies; 33+ messages in thread
From: Matt Roper @ 2019-07-04 1:06 UTC (permalink / raw)
To: intel-gfx
Although the register name implies that it operates on DDI's,
DPCLKA_CFGCR0_ICL actually needs to be programmed according to the PHY
that's in use. I.e., when using EHL's DDI-D on combo PHY A, the bits
described as "port A" in the bspec are what we need to set. The bspec
clarifies:
"[For EHL] DDID clock tied to DDIA clock, so DPCLKA_CFGCR0 DDIA
Clock Select chooses the PLL for both DDIA and DDID and drives
port A in all cases."
Also, since the CNL DPCLKA_CFGCR0 bit defines are still port-based, we
create separate ICL-specific defines that accept the PHY rather than
trying to share the same bit definitions between CNL and ICL.
v5: Make icl_dpclka_cfgcr0_clk_off() take phy rather than port. When
splitting the original patch the hunk to handle this wound up too
late in the series. (Sparse)
Bspec: 33148
Cc: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/i915/display/icl_dsi.c | 17 ++++++---
drivers/gpu/drm/i915/display/intel_ddi.c | 47 +++++++++++++++---------
drivers/gpu/drm/i915/i915_reg.h | 12 ++++--
3 files changed, 50 insertions(+), 26 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
index b8673debf932..f574af62888c 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -560,11 +560,13 @@ static void gen11_dsi_gate_clocks(struct intel_encoder *encoder)
struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
u32 tmp;
enum port port;
+ enum phy phy;
mutex_lock(&dev_priv->dpll_lock);
tmp = I915_READ(DPCLKA_CFGCR0_ICL);
for_each_dsi_port(port, intel_dsi->ports) {
- tmp |= DPCLKA_CFGCR0_DDI_CLK_OFF(port);
+ phy = intel_port_to_phy(dev_priv, port);
+ tmp |= ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
}
I915_WRITE(DPCLKA_CFGCR0_ICL, tmp);
@@ -577,11 +579,13 @@ static void gen11_dsi_ungate_clocks(struct intel_encoder *encoder)
struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
u32 tmp;
enum port port;
+ enum phy phy;
mutex_lock(&dev_priv->dpll_lock);
tmp = I915_READ(DPCLKA_CFGCR0_ICL);
for_each_dsi_port(port, intel_dsi->ports) {
- tmp &= ~DPCLKA_CFGCR0_DDI_CLK_OFF(port);
+ phy = intel_port_to_phy(dev_priv, port);
+ tmp &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
}
I915_WRITE(DPCLKA_CFGCR0_ICL, tmp);
@@ -595,19 +599,22 @@ static void gen11_dsi_map_pll(struct intel_encoder *encoder,
struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
struct intel_shared_dpll *pll = crtc_state->shared_dpll;
enum port port;
+ enum phy phy;
u32 val;
mutex_lock(&dev_priv->dpll_lock);
val = I915_READ(DPCLKA_CFGCR0_ICL);
for_each_dsi_port(port, intel_dsi->ports) {
- val &= ~DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
- val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, port);
+ phy = intel_port_to_phy(dev_priv, port);
+ val &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
+ val |= ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy);
}
I915_WRITE(DPCLKA_CFGCR0_ICL, val);
for_each_dsi_port(port, intel_dsi->ports) {
- val &= ~DPCLKA_CFGCR0_DDI_CLK_OFF(port);
+ phy = intel_port_to_phy(dev_priv, port);
+ val &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
}
I915_WRITE(DPCLKA_CFGCR0_ICL, val);
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index a4172595c8d8..065feb917db4 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -2729,12 +2729,13 @@ u32 ddi_signal_levels(struct intel_dp *intel_dp)
static inline
u32 icl_dpclka_cfgcr0_clk_off(struct drm_i915_private *dev_priv,
- enum port port)
+ enum phy phy)
{
- if (intel_port_is_combophy(dev_priv, port)) {
- return ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(port);
- } else if (intel_port_is_tc(dev_priv, port)) {
- enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
+ if (intel_phy_is_combo(dev_priv, phy)) {
+ return ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
+ } else if (intel_phy_is_tc(dev_priv, phy)) {
+ enum tc_port tc_port = intel_port_to_tc(dev_priv,
+ (enum port)phy);
return ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port);
}
@@ -2747,22 +2748,32 @@ static void icl_map_plls_to_ports(struct intel_encoder *encoder,
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
struct intel_shared_dpll *pll = crtc_state->shared_dpll;
- enum port port = encoder->port;
+ enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
u32 val;
mutex_lock(&dev_priv->dpll_lock);
val = I915_READ(DPCLKA_CFGCR0_ICL);
- WARN_ON((val & icl_dpclka_cfgcr0_clk_off(dev_priv, port)) == 0);
+ WARN_ON((val & icl_dpclka_cfgcr0_clk_off(dev_priv, phy)) == 0);
- if (intel_port_is_combophy(dev_priv, port)) {
- val &= ~DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
- val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, port);
+ if (intel_phy_is_combo(dev_priv, phy)) {
+ /*
+ * Even though this register references DDIs, note that we
+ * want to pass the PHY rather than the port (DDI). For
+ * ICL, port=phy in all cases so it doesn't matter, but for
+ * EHL the bspec notes the following:
+ *
+ * "DDID clock tied to DDIA clock, so DPCLKA_CFGCR0 DDIA
+ * Clock Select chooses the PLL for both DDIA and DDID and
+ * drives port A in all cases."
+ */
+ val &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
+ val |= ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy);
I915_WRITE(DPCLKA_CFGCR0_ICL, val);
POSTING_READ(DPCLKA_CFGCR0_ICL);
}
- val &= ~icl_dpclka_cfgcr0_clk_off(dev_priv, port);
+ val &= ~icl_dpclka_cfgcr0_clk_off(dev_priv, phy);
I915_WRITE(DPCLKA_CFGCR0_ICL, val);
mutex_unlock(&dev_priv->dpll_lock);
@@ -2771,13 +2782,13 @@ static void icl_map_plls_to_ports(struct intel_encoder *encoder,
static void icl_unmap_plls_to_ports(struct intel_encoder *encoder)
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
- enum port port = encoder->port;
+ enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
u32 val;
mutex_lock(&dev_priv->dpll_lock);
val = I915_READ(DPCLKA_CFGCR0_ICL);
- val |= icl_dpclka_cfgcr0_clk_off(dev_priv, port);
+ val |= icl_dpclka_cfgcr0_clk_off(dev_priv, phy);
I915_WRITE(DPCLKA_CFGCR0_ICL, val);
mutex_unlock(&dev_priv->dpll_lock);
@@ -2838,9 +2849,11 @@ void icl_sanitize_encoder_pll_mapping(struct intel_encoder *encoder)
val = I915_READ(DPCLKA_CFGCR0_ICL);
for_each_port_masked(port, port_mask) {
+ enum phy phy = intel_port_to_phy(dev_priv, port);
+
bool ddi_clk_ungated = !(val &
icl_dpclka_cfgcr0_clk_off(dev_priv,
- port));
+ phy));
if (ddi_clk_needed == ddi_clk_ungated)
continue;
@@ -2852,9 +2865,9 @@ void icl_sanitize_encoder_pll_mapping(struct intel_encoder *encoder)
if (WARN_ON(ddi_clk_needed))
continue;
- DRM_NOTE("Port %c is disabled/in DSI mode with an ungated DDI clock, gate it\n",
- port_name(port));
- val |= icl_dpclka_cfgcr0_clk_off(dev_priv, port);
+ DRM_NOTE("PHY %c is disabled/in DSI mode with an ungated DDI clock, gate it\n",
+ phy_name(port));
+ val |= icl_dpclka_cfgcr0_clk_off(dev_priv, phy);
I915_WRITE(DPCLKA_CFGCR0_ICL, val);
}
}
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index c814cc1b3ae5..c9e2e09b6f01 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -9680,17 +9680,21 @@ enum skl_power_gate {
* CNL Clocks
*/
#define DPCLKA_CFGCR0 _MMIO(0x6C200)
-#define DPCLKA_CFGCR0_ICL _MMIO(0x164280)
#define DPCLKA_CFGCR0_DDI_CLK_OFF(port) (1 << ((port) == PORT_F ? 23 : \
(port) + 10))
-#define ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(port) (1 << ((port) + 10))
-#define ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port) (1 << ((tc_port) == PORT_TC4 ? \
- 21 : (tc_port) + 12))
#define DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port) ((port) == PORT_F ? 21 : \
(port) * 2)
#define DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port) (3 << DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port))
#define DPCLKA_CFGCR0_DDI_CLK_SEL(pll, port) ((pll) << DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port))
+#define DPCLKA_CFGCR0_ICL _MMIO(0x164280)
+#define ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy) (1 << _PICK(phy, 10, 11, 24))
+#define ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port) (1 << ((tc_port) == PORT_TC4 ? \
+ 21 : (tc_port) + 12))
+#define ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy) ((phy) * 2)
+#define ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy) (3 << ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy))
+#define ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll, phy) ((pll) << ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy))
+
/* CNL PLL */
#define DPLL0_ENABLE 0x46010
#define DPLL1_ENABLE 0x46014
--
2.17.2
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 33+ messages in thread
* ✓ Fi.CI.BAT: success for EHL port programming (rev5)
2019-07-03 23:37 [PATCH v4 0/5] EHL port programming Matt Roper
` (8 preceding siblings ...)
2019-07-04 0:43 ` ✗ Fi.CI.SPARSE: " Patchwork
@ 2019-07-04 1:18 ` Patchwork
2019-07-04 1:55 ` ✗ Fi.CI.CHECKPATCH: warning for EHL port programming (rev6) Patchwork
` (2 subsequent siblings)
12 siblings, 0 replies; 33+ messages in thread
From: Patchwork @ 2019-07-04 1:18 UTC (permalink / raw)
To: Matt Roper; +Cc: intel-gfx
== Series Details ==
Series: EHL port programming (rev5)
URL : https://patchwork.freedesktop.org/series/62492/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6405 -> Patchwork_13520
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13520/
Known issues
------------
Here are the changes found in Patchwork_13520 that come from known issues:
### IGT changes ###
#### Possible fixes ####
* {igt@gem_ctx_switch@rcs0}:
- fi-icl-guc: [INCOMPLETE][1] ([fdo#107713]) -> [PASS][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6405/fi-icl-guc/igt@gem_ctx_switch@rcs0.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13520/fi-icl-guc/igt@gem_ctx_switch@rcs0.html
* igt@prime_vgem@basic-read:
- fi-icl-u3: [DMESG-WARN][3] ([fdo#107724]) -> [PASS][4]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6405/fi-icl-u3/igt@prime_vgem@basic-read.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13520/fi-icl-u3/igt@prime_vgem@basic-read.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#102505]: https://bugs.freedesktop.org/show_bug.cgi?id=102505
[fdo#105602]: https://bugs.freedesktop.org/show_bug.cgi?id=105602
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#111045]: https://bugs.freedesktop.org/show_bug.cgi?id=111045
[fdo#111049]: https://bugs.freedesktop.org/show_bug.cgi?id=111049
Participating hosts (53 -> 47)
------------------------------
Additional (2): fi-hsw-4770r fi-cml-u2
Missing (8): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-icl-y fi-byt-clapper fi-bdw-samus
Build changes
-------------
* Linux: CI_DRM_6405 -> Patchwork_13520
CI_DRM_6405: d395f3e20d154dfeabb95117f388f2e953c12ac9 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5082: f7c51e6fbf8da0784b64a1edaee5266aa9b9f829 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_13520: e233d250b3244f35bcf08538534d684ea02c9092 @ git://anongit.freedesktop.org/gfx-ci/linux
== Kernel 32bit build ==
Warning: Kernel 32bit buildtest failed:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13520/build_32bit.log
CALL scripts/checksyscalls.sh
CALL scripts/atomic/check-atomics.sh
CHK include/generated/compile.h
Kernel: arch/x86/boot/bzImage is ready (#1)
Building modules, stage 2.
MODPOST 112 modules
ERROR: "__udivdi3" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined!
ERROR: "__divdi3" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined!
scripts/Makefile.modpost:91: recipe for target '__modpost' failed
make[1]: *** [__modpost] Error 1
Makefile:1287: recipe for target 'modules' failed
make: *** [modules] Error 2
== Linux commits ==
e233d250b324 drm/i915/ehl: Enable DDI-D
c8bffe246539 drm/i915: Transition port type checks to phy checks
5b9f9ff3fbfe drm/i915/gen11: Convert combo PHY logic to use new 'enum phy' namespace
5448b97e345e drm/i915/gen11: Program DPCLKA_CFGCR0_ICL according to PHY
248b2ac735b0 drm/i915/gen11: Start distinguishing 'phy' from 'port'
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13520/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 33+ messages in thread
* ✗ Fi.CI.CHECKPATCH: warning for EHL port programming (rev6)
2019-07-03 23:37 [PATCH v4 0/5] EHL port programming Matt Roper
` (9 preceding siblings ...)
2019-07-04 1:18 ` ✓ Fi.CI.BAT: success " Patchwork
@ 2019-07-04 1:55 ` Patchwork
2019-07-04 2:16 ` ✓ Fi.CI.BAT: success " Patchwork
2019-07-05 6:44 ` ✓ Fi.CI.IGT: " Patchwork
12 siblings, 0 replies; 33+ messages in thread
From: Patchwork @ 2019-07-04 1:55 UTC (permalink / raw)
To: Matt Roper; +Cc: intel-gfx
== Series Details ==
Series: EHL port programming (rev6)
URL : https://patchwork.freedesktop.org/series/62492/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
4cf1d095c089 drm/i915/gen11: Start distinguishing 'phy' from 'port'
7e9f8a5e5eec drm/i915/gen11: Program DPCLKA_CFGCR0_ICL according to PHY
-:216: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'tc_port' - possible side-effects?
#216: FILE: drivers/gpu/drm/i915/i915_reg.h:9692:
+#define ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port) (1 << ((tc_port) == PORT_TC4 ? \
+ 21 : (tc_port) + 12))
-:219: WARNING:LONG_LINE: line over 100 characters
#219: FILE: drivers/gpu/drm/i915/i915_reg.h:9695:
+#define ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy) (3 << ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy))
-:220: WARNING:LONG_LINE: line over 100 characters
#220: FILE: drivers/gpu/drm/i915/i915_reg.h:9696:
+#define ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll, phy) ((pll) << ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy))
total: 0 errors, 2 warnings, 1 checks, 173 lines checked
7103f4d8a0ab drm/i915/gen11: Convert combo PHY logic to use new 'enum phy' namespace
-:346: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__phy' - possible side-effects?
#346: FILE: drivers/gpu/drm/i915/display/intel_combo_phy.c:9:
+#define for_each_combo_phy(__dev_priv, __phy) \
+ for ((__phy) = PHY_A; (__phy) < I915_MAX_PHYS; (__phy)++) \
+ for_each_if(intel_phy_is_combo(__dev_priv, __phy))
-:353: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__phy' - possible side-effects?
#353: FILE: drivers/gpu/drm/i915/display/intel_combo_phy.c:13:
+#define for_each_combo_phy_reverse(__dev_priv, __phy) \
+ for ((__phy) = I915_MAX_PHYS; (__phy)-- > PHY_A;) \
+ for_each_if(intel_phy_is_combo(__dev_priv, __phy))
-:826: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__phy' - possible side-effects?
#826: FILE: drivers/gpu/drm/i915/display/intel_display.h:271:
+#define for_each_phy_masked(__phy, __phys_mask) \
+ for ((__phy) = PHY_A; (__phy) < I915_MAX_PHYS; (__phy)++) \
+ for_each_if((__phys_mask) & BIT(__phy))
-:1006: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#1006: FILE: drivers/gpu/drm/i915/i915_reg.h:1880:
+#define CNL_PORT_PCS_DW1_LN0(phy) _MMIO(_PICK(phy, \
_CNL_PORT_PCS_DW1_LN0_AE, \
_CNL_PORT_PCS_DW1_LN0_B, \
_CNL_PORT_PCS_DW1_LN0_C, \
total: 1 errors, 0 warnings, 3 checks, 998 lines checked
4651fa91a8ce drm/i915: Transition port type checks to phy checks
09dfa8996618 drm/i915/ehl: Enable DDI-D
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 33+ messages in thread
* ✓ Fi.CI.BAT: success for EHL port programming (rev6)
2019-07-03 23:37 [PATCH v4 0/5] EHL port programming Matt Roper
` (10 preceding siblings ...)
2019-07-04 1:55 ` ✗ Fi.CI.CHECKPATCH: warning for EHL port programming (rev6) Patchwork
@ 2019-07-04 2:16 ` Patchwork
2019-07-05 6:44 ` ✓ Fi.CI.IGT: " Patchwork
12 siblings, 0 replies; 33+ messages in thread
From: Patchwork @ 2019-07-04 2:16 UTC (permalink / raw)
To: Matt Roper; +Cc: intel-gfx
== Series Details ==
Series: EHL port programming (rev6)
URL : https://patchwork.freedesktop.org/series/62492/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6406 -> Patchwork_13522
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13522/
Known issues
------------
Here are the changes found in Patchwork_13522 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_exec_create@basic:
- fi-icl-u3: [PASS][1] -> [DMESG-WARN][2] ([fdo#107724])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6406/fi-icl-u3/igt@gem_exec_create@basic.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13522/fi-icl-u3/igt@gem_exec_create@basic.html
* igt@kms_frontbuffer_tracking@basic:
- fi-icl-u3: [PASS][3] -> [FAIL][4] ([fdo#103167])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6406/fi-icl-u3/igt@kms_frontbuffer_tracking@basic.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13522/fi-icl-u3/igt@kms_frontbuffer_tracking@basic.html
- fi-icl-u2: [PASS][5] -> [FAIL][6] ([fdo#103167])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6406/fi-icl-u2/igt@kms_frontbuffer_tracking@basic.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13522/fi-icl-u2/igt@kms_frontbuffer_tracking@basic.html
#### Possible fixes ####
* igt@gem_exec_suspend@basic-s3:
- fi-blb-e6850: [INCOMPLETE][7] ([fdo#107718]) -> [PASS][8]
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6406/fi-blb-e6850/igt@gem_exec_suspend@basic-s3.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13522/fi-blb-e6850/igt@gem_exec_suspend@basic-s3.html
* igt@gem_mmap_gtt@basic-small-bo-tiledy:
- fi-icl-u3: [DMESG-WARN][9] ([fdo#107724]) -> [PASS][10]
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6406/fi-icl-u3/igt@gem_mmap_gtt@basic-small-bo-tiledy.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13522/fi-icl-u3/igt@gem_mmap_gtt@basic-small-bo-tiledy.html
* igt@i915_selftest@live_contexts:
- fi-skl-gvtdvm: [DMESG-FAIL][11] -> [PASS][12]
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6406/fi-skl-gvtdvm/igt@i915_selftest@live_contexts.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13522/fi-skl-gvtdvm/igt@i915_selftest@live_contexts.html
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
Participating hosts (53 -> 46)
------------------------------
Additional (2): fi-hsw-peppy fi-icl-u4
Missing (9): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-elk-e7500 fi-icl-y fi-byt-clapper fi-bdw-samus
Build changes
-------------
* Linux: CI_DRM_6406 -> Patchwork_13522
CI_DRM_6406: 3d4498e9178aebf6a0bf04ebbc0a91e7e4f893e3 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5082: f7c51e6fbf8da0784b64a1edaee5266aa9b9f829 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_13522: 09dfa89966180f9128632a77732e5a725139d5f7 @ git://anongit.freedesktop.org/gfx-ci/linux
== Kernel 32bit build ==
Warning: Kernel 32bit buildtest failed:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13522/build_32bit.log
CALL scripts/checksyscalls.sh
CALL scripts/atomic/check-atomics.sh
CHK include/generated/compile.h
Kernel: arch/x86/boot/bzImage is ready (#1)
Building modules, stage 2.
MODPOST 112 modules
ERROR: "__udivdi3" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined!
ERROR: "__divdi3" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined!
scripts/Makefile.modpost:91: recipe for target '__modpost' failed
make[1]: *** [__modpost] Error 1
Makefile:1287: recipe for target 'modules' failed
make: *** [modules] Error 2
== Linux commits ==
09dfa8996618 drm/i915/ehl: Enable DDI-D
4651fa91a8ce drm/i915: Transition port type checks to phy checks
7103f4d8a0ab drm/i915/gen11: Convert combo PHY logic to use new 'enum phy' namespace
7e9f8a5e5eec drm/i915/gen11: Program DPCLKA_CFGCR0_ICL according to PHY
4cf1d095c089 drm/i915/gen11: Start distinguishing 'phy' from 'port'
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13522/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: [PATCH v4 1/5] drm/i915/gen11: Start distinguishing 'phy' from 'port'
2019-07-03 23:37 ` [PATCH v4 1/5] drm/i915/gen11: Start distinguishing 'phy' from 'port' Matt Roper
@ 2019-07-04 9:18 ` Ville Syrjälä
2019-07-04 9:24 ` Ville Syrjälä
2019-07-04 14:54 ` Lucas De Marchi
2019-07-08 23:59 ` Souza, Jose
1 sibling, 2 replies; 33+ messages in thread
From: Ville Syrjälä @ 2019-07-04 9:18 UTC (permalink / raw)
To: Matt Roper; +Cc: Jani Nikula, intel-gfx, Lucas De Marchi
On Wed, Jul 03, 2019 at 04:37:32PM -0700, Matt Roper wrote:
> Our past DDI-based Intel platforms have had a fixed DDI<->PHY mapping.
> Because of this, both the bspec documentation and our i915 code has used
> the term "port" when talking about either DDI's or PHY's; it was always
> easy to tell what terms like "Port A" were referring to from the
> context.
>
> Unfortunately this is starting to break down now that EHL allows PHY-A
> to be driven by either DDI-A or DDI-D. Is a setup with DDI-D driving
> PHY-A considered "Port A" or "Port D?" The answer depends on which
> register we're working with, and even the bspec doesn't do a great job
> of clarifying this.
>
> Let's try to be more explicit about whether we're talking about the DDI
> or the PHY on gen11+ by using 'port' to refer to the DDI and creating a
> new 'enum phy' namespace to refer to the PHY in use.
>
> This patch just adds the new PHY namespace, new phy-based versions of
> intel_port_is_*(), and a helper to convert a port to a PHY.
> Transitioning various areas of the code over to using the PHY namespace
> will be done in subsequent patches to make review easier. We'll remove
> the intel_port_is_*() functions at the end of the series when we
> transition all callers over to using the PHY-based versions.
>
> v2:
> - Convert a few more 'port' uses to 'phy.' (Sparse)
>
> v3:
> - Switch DDI_CLK_SEL() back to 'port.' (Jose)
> - Add a code comment clarifying why DPCLKA_CFGCR0_ICL needs to use PHY
> for its bit definitions, even though the register description is
> given in terms of DDI.
> - To avoid confusion, switch CNL's DPCLKA_CFGCR0 defines back to using
> port and create separate ICL+ definitions that work in terms of PHY.
>
> v4:
> - Rebase and resolve conflicts with Imre's TC series.
> - This patch now just adds the namespace and a few convenience
> functions; the important changes are now split out into separate
> patches to make review easier.
>
> Suggested-by: Ville Syrjala <ville.syrjala@linux.intel.com>
> Cc: José Roberto de Souza <jose.souza@intel.com>
> Cc: Lucas De Marchi <lucas.demarchi@intel.com>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Cc: Imre Deak <imre.deak@intel.com>
> Cc: Jani Nikula <jani.nikula@intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 32 +++++++++++++++++++-
> drivers/gpu/drm/i915/display/intel_display.h | 16 ++++++++++
> drivers/gpu/drm/i915/intel_drv.h | 2 ++
> 3 files changed, 49 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 919f5ac844c8..4a85abef93e7 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -6663,6 +6663,20 @@ bool intel_port_is_combophy(struct drm_i915_private *dev_priv, enum port port)
> return false;
> }
>
> +bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy phy)
> +{
> + if (phy == PHY_NONE)
> + return false;
> +
> + if (IS_ELKHARTLAKE(dev_priv))
> + return phy <= PHY_C;
> +
> + if (INTEL_GEN(dev_priv) >= 11)
> + return phy <= PHY_B;
> +
> + return false;
> +}
> +
> bool intel_port_is_tc(struct drm_i915_private *dev_priv, enum port port)
> {
> if (INTEL_GEN(dev_priv) >= 11 && !IS_ELKHARTLAKE(dev_priv))
> @@ -6671,9 +6685,25 @@ bool intel_port_is_tc(struct drm_i915_private *dev_priv, enum port port)
> return false;
> }
>
> +bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy)
> +{
> + if (INTEL_GEN(dev_priv) >= 11 && !IS_ELKHARTLAKE(dev_priv))
> + return phy >= PHY_C && phy <= PHY_F;
> +
> + return false;
> +}
> +
> +enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port)
> +{
> + if (IS_ELKHARTLAKE(i915) && port == PORT_D)
> + return PHY_A;
> +
> + return (enum phy)port;
> +}
> +
> enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv, enum port port)
> {
> - if (!intel_port_is_tc(dev_priv, port))
> + if (!intel_phy_is_tc(dev_priv, intel_port_to_phy(dev_priv, port)))
> return PORT_TC_NONE;
>
> return port - PORT_C;
> diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
> index d296556ed82e..d53285fb883f 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.h
> +++ b/drivers/gpu/drm/i915/display/intel_display.h
> @@ -228,6 +228,21 @@ struct intel_link_m_n {
> u32 link_n;
> };
>
> +enum phy {
> + PHY_NONE = -1,
> +
> + PHY_A = 0,
> + PHY_B,
> + PHY_C,
> + PHY_D,
> + PHY_E,
> + PHY_F,
> +
> + I915_MAX_PHYS
> +};
I was pondering if we could eventually do something like:
enum phy {
PHY_COMBO_A = 0,
PHY_COMBO_B,
...
PHY_TC_1,
PHY_TC_2,
...
};
and probably also add encoder->phy so we can contain
that port<->phy mapping logic in the encoder init.
I think that should work more or less fine since I
don't think PHY_TC_1 needs to have any specific value.
Unfortunaltey I don't have a great idea how to do the
same for the DDIs since there the number of combo DDIs
changes but we still need the PORT_TC1 (assuming we had
one) to be DDI_<last combo DDI> + 1. One random silly
idea was to decouple the enum port from the register
definitions by having just some kind of
encoder->port_index for those. But that doesn't feel
entirely great either.
Anyways, something to think about in the future perhaps.
Patch is
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> +
> +#define phy_name(a) ((a) + 'A')
> +
> #define for_each_pipe(__dev_priv, __p) \
> for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++)
>
> @@ -356,5 +371,6 @@ void lpt_disable_clkout_dp(struct drm_i915_private *dev_priv);
> u32 intel_plane_fb_max_stride(struct drm_i915_private *dev_priv,
> u32 pixel_format, u64 modifier);
> bool intel_plane_can_remap(const struct intel_plane_state *plane_state);
> +enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port);
>
> #endif
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index 24c63ed45c6f..815c26c0b98c 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -1493,7 +1493,9 @@ void intel_encoder_destroy(struct drm_encoder *encoder);
> struct drm_display_mode *
> intel_encoder_current_mode(struct intel_encoder *encoder);
> bool intel_port_is_combophy(struct drm_i915_private *dev_priv, enum port port);
> +bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy phy);
> bool intel_port_is_tc(struct drm_i915_private *dev_priv, enum port port);
> +bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy);
> enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv,
> enum port port);
> int intel_get_pipe_from_crtc_id_ioctl(struct drm_device *dev, void *data,
> --
> 2.17.2
--
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: [PATCH v4 1/5] drm/i915/gen11: Start distinguishing 'phy' from 'port'
2019-07-04 9:18 ` Ville Syrjälä
@ 2019-07-04 9:24 ` Ville Syrjälä
2019-07-04 14:54 ` Lucas De Marchi
1 sibling, 0 replies; 33+ messages in thread
From: Ville Syrjälä @ 2019-07-04 9:24 UTC (permalink / raw)
To: Matt Roper; +Cc: Jani Nikula, intel-gfx, Lucas De Marchi
On Thu, Jul 04, 2019 at 12:18:11PM +0300, Ville Syrjälä wrote:
> On Wed, Jul 03, 2019 at 04:37:32PM -0700, Matt Roper wrote:
> > Our past DDI-based Intel platforms have had a fixed DDI<->PHY mapping.
> > Because of this, both the bspec documentation and our i915 code has used
> > the term "port" when talking about either DDI's or PHY's; it was always
> > easy to tell what terms like "Port A" were referring to from the
> > context.
> >
> > Unfortunately this is starting to break down now that EHL allows PHY-A
> > to be driven by either DDI-A or DDI-D. Is a setup with DDI-D driving
> > PHY-A considered "Port A" or "Port D?" The answer depends on which
> > register we're working with, and even the bspec doesn't do a great job
> > of clarifying this.
> >
> > Let's try to be more explicit about whether we're talking about the DDI
> > or the PHY on gen11+ by using 'port' to refer to the DDI and creating a
> > new 'enum phy' namespace to refer to the PHY in use.
> >
> > This patch just adds the new PHY namespace, new phy-based versions of
> > intel_port_is_*(), and a helper to convert a port to a PHY.
> > Transitioning various areas of the code over to using the PHY namespace
> > will be done in subsequent patches to make review easier. We'll remove
> > the intel_port_is_*() functions at the end of the series when we
> > transition all callers over to using the PHY-based versions.
> >
> > v2:
> > - Convert a few more 'port' uses to 'phy.' (Sparse)
> >
> > v3:
> > - Switch DDI_CLK_SEL() back to 'port.' (Jose)
> > - Add a code comment clarifying why DPCLKA_CFGCR0_ICL needs to use PHY
> > for its bit definitions, even though the register description is
> > given in terms of DDI.
> > - To avoid confusion, switch CNL's DPCLKA_CFGCR0 defines back to using
> > port and create separate ICL+ definitions that work in terms of PHY.
> >
> > v4:
> > - Rebase and resolve conflicts with Imre's TC series.
> > - This patch now just adds the namespace and a few convenience
> > functions; the important changes are now split out into separate
> > patches to make review easier.
> >
> > Suggested-by: Ville Syrjala <ville.syrjala@linux.intel.com>
> > Cc: José Roberto de Souza <jose.souza@intel.com>
> > Cc: Lucas De Marchi <lucas.demarchi@intel.com>
> > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > Cc: Imre Deak <imre.deak@intel.com>
> > Cc: Jani Nikula <jani.nikula@intel.com>
> > Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> > ---
> > drivers/gpu/drm/i915/display/intel_display.c | 32 +++++++++++++++++++-
> > drivers/gpu/drm/i915/display/intel_display.h | 16 ++++++++++
> > drivers/gpu/drm/i915/intel_drv.h | 2 ++
> > 3 files changed, 49 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> > index 919f5ac844c8..4a85abef93e7 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > @@ -6663,6 +6663,20 @@ bool intel_port_is_combophy(struct drm_i915_private *dev_priv, enum port port)
> > return false;
> > }
> >
> > +bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy phy)
> > +{
> > + if (phy == PHY_NONE)
> > + return false;
> > +
> > + if (IS_ELKHARTLAKE(dev_priv))
> > + return phy <= PHY_C;
> > +
> > + if (INTEL_GEN(dev_priv) >= 11)
> > + return phy <= PHY_B;
> > +
> > + return false;
> > +}
> > +
> > bool intel_port_is_tc(struct drm_i915_private *dev_priv, enum port port)
> > {
> > if (INTEL_GEN(dev_priv) >= 11 && !IS_ELKHARTLAKE(dev_priv))
> > @@ -6671,9 +6685,25 @@ bool intel_port_is_tc(struct drm_i915_private *dev_priv, enum port port)
> > return false;
> > }
> >
> > +bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy)
> > +{
> > + if (INTEL_GEN(dev_priv) >= 11 && !IS_ELKHARTLAKE(dev_priv))
> > + return phy >= PHY_C && phy <= PHY_F;
> > +
> > + return false;
> > +}
> > +
> > +enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port)
> > +{
> > + if (IS_ELKHARTLAKE(i915) && port == PORT_D)
> > + return PHY_A;
> > +
> > + return (enum phy)port;
> > +}
> > +
> > enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv, enum port port)
> > {
> > - if (!intel_port_is_tc(dev_priv, port))
> > + if (!intel_phy_is_tc(dev_priv, intel_port_to_phy(dev_priv, port)))
> > return PORT_TC_NONE;
> >
> > return port - PORT_C;
> > diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
> > index d296556ed82e..d53285fb883f 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display.h
> > +++ b/drivers/gpu/drm/i915/display/intel_display.h
> > @@ -228,6 +228,21 @@ struct intel_link_m_n {
> > u32 link_n;
> > };
> >
> > +enum phy {
> > + PHY_NONE = -1,
> > +
> > + PHY_A = 0,
> > + PHY_B,
> > + PHY_C,
> > + PHY_D,
> > + PHY_E,
> > + PHY_F,
> > +
> > + I915_MAX_PHYS
> > +};
>
> I was pondering if we could eventually do something like:
>
> enum phy {
> PHY_COMBO_A = 0,
> PHY_COMBO_B,
> ...
>
> PHY_TC_1,
> PHY_TC_2,
> ...
> };
>
> and probably also add encoder->phy so we can contain
> that port<->phy mapping logic in the encoder init.
> I think that should work more or less fine since I
> don't think PHY_TC_1 needs to have any specific value.
Another option might be to have overlapping values such that
COMBO_A == TC1 and just have a separate flag to indicate which
type we're dealing with.
--
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: [PATCH v5 2/5] drm/i915/gen11: Program DPCLKA_CFGCR0_ICL according to PHY
2019-07-04 1:06 ` [PATCH v5 " Matt Roper
@ 2019-07-04 9:31 ` Ville Syrjälä
2019-07-09 0:15 ` Souza, Jose
1 sibling, 0 replies; 33+ messages in thread
From: Ville Syrjälä @ 2019-07-04 9:31 UTC (permalink / raw)
To: Matt Roper; +Cc: intel-gfx
On Wed, Jul 03, 2019 at 06:06:58PM -0700, Matt Roper wrote:
> Although the register name implies that it operates on DDI's,
> DPCLKA_CFGCR0_ICL actually needs to be programmed according to the PHY
> that's in use. I.e., when using EHL's DDI-D on combo PHY A, the bits
> described as "port A" in the bspec are what we need to set. The bspec
> clarifies:
>
> "[For EHL] DDID clock tied to DDIA clock, so DPCLKA_CFGCR0 DDIA
> Clock Select chooses the PLL for both DDIA and DDID and drives
> port A in all cases."
>
> Also, since the CNL DPCLKA_CFGCR0 bit defines are still port-based, we
> create separate ICL-specific defines that accept the PHY rather than
> trying to share the same bit definitions between CNL and ICL.
>
> v5: Make icl_dpclka_cfgcr0_clk_off() take phy rather than port. When
> splitting the original patch the hunk to handle this wound up too
> late in the series. (Sparse)
>
> Bspec: 33148
> Cc: José Roberto de Souza <jose.souza@intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Looks correct to me.
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/display/icl_dsi.c | 17 ++++++---
> drivers/gpu/drm/i915/display/intel_ddi.c | 47 +++++++++++++++---------
> drivers/gpu/drm/i915/i915_reg.h | 12 ++++--
> 3 files changed, 50 insertions(+), 26 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
> index b8673debf932..f574af62888c 100644
> --- a/drivers/gpu/drm/i915/display/icl_dsi.c
> +++ b/drivers/gpu/drm/i915/display/icl_dsi.c
> @@ -560,11 +560,13 @@ static void gen11_dsi_gate_clocks(struct intel_encoder *encoder)
> struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
> u32 tmp;
> enum port port;
> + enum phy phy;
>
> mutex_lock(&dev_priv->dpll_lock);
> tmp = I915_READ(DPCLKA_CFGCR0_ICL);
> for_each_dsi_port(port, intel_dsi->ports) {
> - tmp |= DPCLKA_CFGCR0_DDI_CLK_OFF(port);
> + phy = intel_port_to_phy(dev_priv, port);
> + tmp |= ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
> }
>
> I915_WRITE(DPCLKA_CFGCR0_ICL, tmp);
> @@ -577,11 +579,13 @@ static void gen11_dsi_ungate_clocks(struct intel_encoder *encoder)
> struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
> u32 tmp;
> enum port port;
> + enum phy phy;
>
> mutex_lock(&dev_priv->dpll_lock);
> tmp = I915_READ(DPCLKA_CFGCR0_ICL);
> for_each_dsi_port(port, intel_dsi->ports) {
> - tmp &= ~DPCLKA_CFGCR0_DDI_CLK_OFF(port);
> + phy = intel_port_to_phy(dev_priv, port);
> + tmp &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
> }
>
> I915_WRITE(DPCLKA_CFGCR0_ICL, tmp);
> @@ -595,19 +599,22 @@ static void gen11_dsi_map_pll(struct intel_encoder *encoder,
> struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
> struct intel_shared_dpll *pll = crtc_state->shared_dpll;
> enum port port;
> + enum phy phy;
> u32 val;
>
> mutex_lock(&dev_priv->dpll_lock);
>
> val = I915_READ(DPCLKA_CFGCR0_ICL);
> for_each_dsi_port(port, intel_dsi->ports) {
> - val &= ~DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
> - val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, port);
> + phy = intel_port_to_phy(dev_priv, port);
> + val &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
> + val |= ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy);
> }
> I915_WRITE(DPCLKA_CFGCR0_ICL, val);
>
> for_each_dsi_port(port, intel_dsi->ports) {
> - val &= ~DPCLKA_CFGCR0_DDI_CLK_OFF(port);
> + phy = intel_port_to_phy(dev_priv, port);
> + val &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
> }
> I915_WRITE(DPCLKA_CFGCR0_ICL, val);
>
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> index a4172595c8d8..065feb917db4 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -2729,12 +2729,13 @@ u32 ddi_signal_levels(struct intel_dp *intel_dp)
>
> static inline
> u32 icl_dpclka_cfgcr0_clk_off(struct drm_i915_private *dev_priv,
> - enum port port)
> + enum phy phy)
> {
> - if (intel_port_is_combophy(dev_priv, port)) {
> - return ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(port);
> - } else if (intel_port_is_tc(dev_priv, port)) {
> - enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
> + if (intel_phy_is_combo(dev_priv, phy)) {
> + return ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
> + } else if (intel_phy_is_tc(dev_priv, phy)) {
> + enum tc_port tc_port = intel_port_to_tc(dev_priv,
> + (enum port)phy);
>
> return ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port);
> }
> @@ -2747,22 +2748,32 @@ static void icl_map_plls_to_ports(struct intel_encoder *encoder,
> {
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> struct intel_shared_dpll *pll = crtc_state->shared_dpll;
> - enum port port = encoder->port;
> + enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
> u32 val;
>
> mutex_lock(&dev_priv->dpll_lock);
>
> val = I915_READ(DPCLKA_CFGCR0_ICL);
> - WARN_ON((val & icl_dpclka_cfgcr0_clk_off(dev_priv, port)) == 0);
> + WARN_ON((val & icl_dpclka_cfgcr0_clk_off(dev_priv, phy)) == 0);
>
> - if (intel_port_is_combophy(dev_priv, port)) {
> - val &= ~DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
> - val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, port);
> + if (intel_phy_is_combo(dev_priv, phy)) {
> + /*
> + * Even though this register references DDIs, note that we
> + * want to pass the PHY rather than the port (DDI). For
> + * ICL, port=phy in all cases so it doesn't matter, but for
> + * EHL the bspec notes the following:
> + *
> + * "DDID clock tied to DDIA clock, so DPCLKA_CFGCR0 DDIA
> + * Clock Select chooses the PLL for both DDIA and DDID and
> + * drives port A in all cases."
> + */
> + val &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
> + val |= ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy);
> I915_WRITE(DPCLKA_CFGCR0_ICL, val);
> POSTING_READ(DPCLKA_CFGCR0_ICL);
> }
>
> - val &= ~icl_dpclka_cfgcr0_clk_off(dev_priv, port);
> + val &= ~icl_dpclka_cfgcr0_clk_off(dev_priv, phy);
> I915_WRITE(DPCLKA_CFGCR0_ICL, val);
>
> mutex_unlock(&dev_priv->dpll_lock);
> @@ -2771,13 +2782,13 @@ static void icl_map_plls_to_ports(struct intel_encoder *encoder,
> static void icl_unmap_plls_to_ports(struct intel_encoder *encoder)
> {
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> - enum port port = encoder->port;
> + enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
> u32 val;
>
> mutex_lock(&dev_priv->dpll_lock);
>
> val = I915_READ(DPCLKA_CFGCR0_ICL);
> - val |= icl_dpclka_cfgcr0_clk_off(dev_priv, port);
> + val |= icl_dpclka_cfgcr0_clk_off(dev_priv, phy);
> I915_WRITE(DPCLKA_CFGCR0_ICL, val);
>
> mutex_unlock(&dev_priv->dpll_lock);
> @@ -2838,9 +2849,11 @@ void icl_sanitize_encoder_pll_mapping(struct intel_encoder *encoder)
>
> val = I915_READ(DPCLKA_CFGCR0_ICL);
> for_each_port_masked(port, port_mask) {
> + enum phy phy = intel_port_to_phy(dev_priv, port);
> +
> bool ddi_clk_ungated = !(val &
> icl_dpclka_cfgcr0_clk_off(dev_priv,
> - port));
> + phy));
>
> if (ddi_clk_needed == ddi_clk_ungated)
> continue;
> @@ -2852,9 +2865,9 @@ void icl_sanitize_encoder_pll_mapping(struct intel_encoder *encoder)
> if (WARN_ON(ddi_clk_needed))
> continue;
>
> - DRM_NOTE("Port %c is disabled/in DSI mode with an ungated DDI clock, gate it\n",
> - port_name(port));
> - val |= icl_dpclka_cfgcr0_clk_off(dev_priv, port);
> + DRM_NOTE("PHY %c is disabled/in DSI mode with an ungated DDI clock, gate it\n",
> + phy_name(port));
> + val |= icl_dpclka_cfgcr0_clk_off(dev_priv, phy);
> I915_WRITE(DPCLKA_CFGCR0_ICL, val);
> }
> }
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index c814cc1b3ae5..c9e2e09b6f01 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -9680,17 +9680,21 @@ enum skl_power_gate {
> * CNL Clocks
> */
> #define DPCLKA_CFGCR0 _MMIO(0x6C200)
> -#define DPCLKA_CFGCR0_ICL _MMIO(0x164280)
> #define DPCLKA_CFGCR0_DDI_CLK_OFF(port) (1 << ((port) == PORT_F ? 23 : \
> (p`:wqort) + 10))
> -#define ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(port) (1 << ((port) + 10))
> -#define ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port) (1 << ((tc_port) == PORT_TC4 ? \
> - 21 : (tc_port) + 12))
> #define DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port) ((port) == PORT_F ? 21 : \
> (port) * 2)
> #define DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port) (3 << DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port))
> #define DPCLKA_CFGCR0_DDI_CLK_SEL(pll, port) ((pll) << DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port))
>
> +#define DPCLKA_CFGCR0_ICL _MMIO(0x164280)
> +#define ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy) (1 << _PICK(phy, 10, 11, 24))
> +#define ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port) (1 << ((tc_port) == PORT_TC4 ? \
> + 21 : (tc_port) + 12))
> +#define ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy) ((phy) * 2)
> +#define ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy) (3 << ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy))
> +#define ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll, phy) ((pll) << ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy))
> +
> /* CNL PLL */
> #define DPLL0_ENABLE 0x46010
> #define DPLL1_ENABLE 0x46014
> --
> 2.17.2
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: [PATCH v4 3/5] drm/i915/gen11: Convert combo PHY logic to use new 'enum phy' namespace
2019-07-03 23:37 ` [PATCH v4 3/5] drm/i915/gen11: Convert combo PHY logic to use new 'enum phy' namespace Matt Roper
@ 2019-07-04 9:39 ` Ville Syrjälä
2019-07-09 0:41 ` Souza, Jose
1 sibling, 0 replies; 33+ messages in thread
From: Ville Syrjälä @ 2019-07-04 9:39 UTC (permalink / raw)
To: Matt Roper; +Cc: intel-gfx
On Wed, Jul 03, 2019 at 04:37:34PM -0700, Matt Roper wrote:
> Convert the code that operates directly on gen11 combo PHY's to use the
> new namespace. Combo PHY registers are those named "ICL_PORT_*" plus
> ICL_DPHY_CHKN.
>
> Note that a lot of the PHY programming happens in the MIPI DSI code.
> For clarity I've added a for_each_dsi_phy() to loop over the phys used
> by DSI. Since DSI always uses A & B on gen11, port=phy in all cases so
> it doesn't actually matter which form we use in the DSI code. I've used
> the phy iterator in code that's explicitly working with the combo PHY,
> but left the rest of the DSI code using the port iterator and namespace
> to minimize patch deltas. We can switch the rest of the DSI code over
> to use phy terminology later if this winds up being too confusing.
>
> Cc: José Roberto de Souza <jose.souza@intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> ---
> drivers/gpu/drm/i915/display/icl_dsi.c | 127 ++++++++--------
> .../gpu/drm/i915/display/intel_combo_phy.c | 143 +++++++++---------
> .../gpu/drm/i915/display/intel_combo_phy.h | 3 +-
> drivers/gpu/drm/i915/display/intel_ddi.c | 45 +++---
> drivers/gpu/drm/i915/display/intel_display.h | 4 +
> .../drm/i915/display/intel_display_power.c | 16 +-
> drivers/gpu/drm/i915/display/intel_dsi.h | 12 +-
> drivers/gpu/drm/i915/i915_reg.h | 74 ++++-----
> 8 files changed, 213 insertions(+), 211 deletions(-)
>
<snip>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
> index d53285fb883f..8a4a57ef82a2 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.h
> +++ b/drivers/gpu/drm/i915/display/intel_display.h
> @@ -268,6 +268,10 @@ enum phy {
> for ((__port) = PORT_A; (__port) < I915_MAX_PORTS; (__port)++) \
> for_each_if((__ports_mask) & BIT(__port))
>
> +#define for_each_phy_masked(__phy, __phys_mask) \
> + for ((__phy) = PHY_A; (__phy) < I915_MAX_PHYS; (__phy)++) \
> + for_each_if((__phys_mask) & BIT(__phy))
> +
> #define for_each_crtc(dev, crtc) \
> list_for_each_entry(crtc, &(dev)->mode_config.crtc_list, head)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
> index c19b958461ca..64627c117c31 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> @@ -395,7 +395,7 @@ static void hsw_power_well_disable(struct drm_i915_private *dev_priv,
> hsw_wait_for_power_well_disable(dev_priv, power_well);
> }
>
> -#define ICL_AUX_PW_TO_PORT(pw_idx) ((pw_idx) - ICL_PW_CTL_IDX_AUX_A)
> +#define ICL_AUX_PW_TO_PHY(pw_idx) ((pw_idx) - ICL_PW_CTL_IDX_AUX_A)
>
> static void
> icl_combo_phy_aux_power_well_enable(struct drm_i915_private *dev_priv,
> @@ -403,21 +403,21 @@ icl_combo_phy_aux_power_well_enable(struct drm_i915_private *dev_priv,
> {
> const struct i915_power_well_regs *regs = power_well->desc->hsw.regs;
> int pw_idx = power_well->desc->hsw.idx;
> - enum port port = ICL_AUX_PW_TO_PORT(pw_idx);
> + enum phy phy = ICL_AUX_PW_TO_PHY(pw_idx);
> u32 val;
>
> val = I915_READ(regs->driver);
> I915_WRITE(regs->driver, val | HSW_PWR_WELL_CTL_REQ(pw_idx));
>
> - val = I915_READ(ICL_PORT_CL_DW12(port));
> - I915_WRITE(ICL_PORT_CL_DW12(port), val | ICL_LANE_ENABLE_AUX);
> + val = I915_READ(ICL_PORT_CL_DW12(phy));
> + I915_WRITE(ICL_PORT_CL_DW12(phy), val | ICL_LANE_ENABLE_AUX);
>
> hsw_wait_for_power_well_enable(dev_priv, power_well);
>
> /* Display WA #1178: icl */
> if (IS_ICELAKE(dev_priv) &&
> pw_idx >= ICL_PW_CTL_IDX_AUX_A && pw_idx <= ICL_PW_CTL_IDX_AUX_B &&
> - !intel_bios_is_port_edp(dev_priv, port)) {
> + !intel_bios_is_port_edp(dev_priv, (enum port)phy)) {
We don't need this on ehl?
Patch is
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> val = I915_READ(ICL_AUX_ANAOVRD1(pw_idx));
> val |= ICL_AUX_ANAOVRD1_ENABLE | ICL_AUX_ANAOVRD1_LDO_BYPASS;
> I915_WRITE(ICL_AUX_ANAOVRD1(pw_idx), val);
> @@ -430,11 +430,11 @@ icl_combo_phy_aux_power_well_disable(struct drm_i915_private *dev_priv,
> {
> const struct i915_power_well_regs *regs = power_well->desc->hsw.regs;
> int pw_idx = power_well->desc->hsw.idx;
> - enum port port = ICL_AUX_PW_TO_PORT(pw_idx);
> + enum phy phy = ICL_AUX_PW_TO_PHY(pw_idx);
> u32 val;
>
> - val = I915_READ(ICL_PORT_CL_DW12(port));
> - I915_WRITE(ICL_PORT_CL_DW12(port), val & ~ICL_LANE_ENABLE_AUX);
> + val = I915_READ(ICL_PORT_CL_DW12(phy));
> + I915_WRITE(ICL_PORT_CL_DW12(phy), val & ~ICL_LANE_ENABLE_AUX);
>
> val = I915_READ(regs->driver);
> I915_WRITE(regs->driver, val & ~HSW_PWR_WELL_CTL_REQ(pw_idx));
> diff --git a/drivers/gpu/drm/i915/display/intel_dsi.h b/drivers/gpu/drm/i915/display/intel_dsi.h
> index 6d20434636cd..1cd24bd46518 100644
> --- a/drivers/gpu/drm/i915/display/intel_dsi.h
> +++ b/drivers/gpu/drm/i915/display/intel_dsi.h
> @@ -49,8 +49,11 @@ struct intel_dsi {
>
> struct intel_connector *attached_connector;
>
> - /* bit mask of ports being driven */
> - u16 ports;
> + /* bit mask of ports (vlv dsi) or phys (icl dsi) being driven */
> + union {
> + u16 ports; /* VLV DSI */
> + u16 phys; /* ICL DSI */
> + };
>
> /* if true, use HS mode, otherwise LP */
> bool hs;
> @@ -132,7 +135,10 @@ static inline struct intel_dsi_host *to_intel_dsi_host(struct mipi_dsi_host *h)
> return container_of(h, struct intel_dsi_host, base);
> }
>
> -#define for_each_dsi_port(__port, __ports_mask) for_each_port_masked(__port, __ports_mask)
> +#define for_each_dsi_port(__port, __ports_mask) \
> + for_each_port_masked(__port, __ports_mask)
> +#define for_each_dsi_phy(__phy, __phys_mask) \
> + for_each_phy_masked(__phy, __phys_mask)
>
> static inline struct intel_dsi *enc_to_intel_dsi(struct drm_encoder *encoder)
> {
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index c9e2e09b6f01..b766ba22045b 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1794,20 +1794,20 @@ enum i915_power_well_id {
> #define _ICL_COMBOPHY_A 0x162000
> #define _ICL_COMBOPHY_B 0x6C000
> #define _EHL_COMBOPHY_C 0x160000
> -#define _ICL_COMBOPHY(port) _PICK(port, _ICL_COMBOPHY_A, \
> +#define _ICL_COMBOPHY(phy) _PICK(phy, _ICL_COMBOPHY_A, \
> _ICL_COMBOPHY_B, \
> _EHL_COMBOPHY_C)
>
> /* CNL/ICL Port CL_DW registers */
> -#define _ICL_PORT_CL_DW(dw, port) (_ICL_COMBOPHY(port) + \
> +#define _ICL_PORT_CL_DW(dw, phy) (_ICL_COMBOPHY(phy) + \
> 4 * (dw))
>
> #define CNL_PORT_CL1CM_DW5 _MMIO(0x162014)
> -#define ICL_PORT_CL_DW5(port) _MMIO(_ICL_PORT_CL_DW(5, port))
> +#define ICL_PORT_CL_DW5(phy) _MMIO(_ICL_PORT_CL_DW(5, phy))
> #define CL_POWER_DOWN_ENABLE (1 << 4)
> #define SUS_CLOCK_CONFIG (3 << 0)
>
> -#define ICL_PORT_CL_DW10(port) _MMIO(_ICL_PORT_CL_DW(10, port))
> +#define ICL_PORT_CL_DW10(phy) _MMIO(_ICL_PORT_CL_DW(10, phy))
> #define PG_SEQ_DELAY_OVERRIDE_MASK (3 << 25)
> #define PG_SEQ_DELAY_OVERRIDE_SHIFT 25
> #define PG_SEQ_DELAY_OVERRIDE_ENABLE (1 << 24)
> @@ -1822,23 +1822,23 @@ enum i915_power_well_id {
> #define PWR_DOWN_LN_MASK (0xf << 4)
> #define PWR_DOWN_LN_SHIFT 4
>
> -#define ICL_PORT_CL_DW12(port) _MMIO(_ICL_PORT_CL_DW(12, port))
> +#define ICL_PORT_CL_DW12(phy) _MMIO(_ICL_PORT_CL_DW(12, phy))
> #define ICL_LANE_ENABLE_AUX (1 << 0)
>
> /* CNL/ICL Port COMP_DW registers */
> #define _ICL_PORT_COMP 0x100
> -#define _ICL_PORT_COMP_DW(dw, port) (_ICL_COMBOPHY(port) + \
> +#define _ICL_PORT_COMP_DW(dw, phy) (_ICL_COMBOPHY(phy) + \
> _ICL_PORT_COMP + 4 * (dw))
>
> #define CNL_PORT_COMP_DW0 _MMIO(0x162100)
> -#define ICL_PORT_COMP_DW0(port) _MMIO(_ICL_PORT_COMP_DW(0, port))
> +#define ICL_PORT_COMP_DW0(phy) _MMIO(_ICL_PORT_COMP_DW(0, phy))
> #define COMP_INIT (1 << 31)
>
> #define CNL_PORT_COMP_DW1 _MMIO(0x162104)
> -#define ICL_PORT_COMP_DW1(port) _MMIO(_ICL_PORT_COMP_DW(1, port))
> +#define ICL_PORT_COMP_DW1(phy) _MMIO(_ICL_PORT_COMP_DW(1, phy))
>
> #define CNL_PORT_COMP_DW3 _MMIO(0x16210c)
> -#define ICL_PORT_COMP_DW3(port) _MMIO(_ICL_PORT_COMP_DW(3, port))
> +#define ICL_PORT_COMP_DW3(phy) _MMIO(_ICL_PORT_COMP_DW(3, phy))
> #define PROCESS_INFO_DOT_0 (0 << 26)
> #define PROCESS_INFO_DOT_1 (1 << 26)
> #define PROCESS_INFO_DOT_4 (2 << 26)
> @@ -1850,14 +1850,14 @@ enum i915_power_well_id {
> #define VOLTAGE_INFO_MASK (3 << 24)
> #define VOLTAGE_INFO_SHIFT 24
>
> -#define ICL_PORT_COMP_DW8(port) _MMIO(_ICL_PORT_COMP_DW(8, port))
> +#define ICL_PORT_COMP_DW8(phy) _MMIO(_ICL_PORT_COMP_DW(8, phy))
> #define IREFGEN (1 << 24)
>
> #define CNL_PORT_COMP_DW9 _MMIO(0x162124)
> -#define ICL_PORT_COMP_DW9(port) _MMIO(_ICL_PORT_COMP_DW(9, port))
> +#define ICL_PORT_COMP_DW9(phy) _MMIO(_ICL_PORT_COMP_DW(9, phy))
>
> #define CNL_PORT_COMP_DW10 _MMIO(0x162128)
> -#define ICL_PORT_COMP_DW10(port) _MMIO(_ICL_PORT_COMP_DW(10, port))
> +#define ICL_PORT_COMP_DW10(phy) _MMIO(_ICL_PORT_COMP_DW(10, phy))
>
> /* CNL/ICL Port PCS registers */
> #define _CNL_PORT_PCS_DW1_GRP_AE 0x162304
> @@ -1870,14 +1870,14 @@ enum i915_power_well_id {
> #define _CNL_PORT_PCS_DW1_LN0_C 0x162C04
> #define _CNL_PORT_PCS_DW1_LN0_D 0x162E04
> #define _CNL_PORT_PCS_DW1_LN0_F 0x162804
> -#define CNL_PORT_PCS_DW1_GRP(port) _MMIO(_PICK(port, \
> +#define CNL_PORT_PCS_DW1_GRP(phy) _MMIO(_PICK(phy, \
> _CNL_PORT_PCS_DW1_GRP_AE, \
> _CNL_PORT_PCS_DW1_GRP_B, \
> _CNL_PORT_PCS_DW1_GRP_C, \
> _CNL_PORT_PCS_DW1_GRP_D, \
> _CNL_PORT_PCS_DW1_GRP_AE, \
> _CNL_PORT_PCS_DW1_GRP_F))
> -#define CNL_PORT_PCS_DW1_LN0(port) _MMIO(_PICK(port, \
> +#define CNL_PORT_PCS_DW1_LN0(phy) _MMIO(_PICK(phy, \
> _CNL_PORT_PCS_DW1_LN0_AE, \
> _CNL_PORT_PCS_DW1_LN0_B, \
> _CNL_PORT_PCS_DW1_LN0_C, \
> @@ -1888,15 +1888,15 @@ enum i915_power_well_id {
> #define _ICL_PORT_PCS_AUX 0x300
> #define _ICL_PORT_PCS_GRP 0x600
> #define _ICL_PORT_PCS_LN(ln) (0x800 + (ln) * 0x100)
> -#define _ICL_PORT_PCS_DW_AUX(dw, port) (_ICL_COMBOPHY(port) + \
> +#define _ICL_PORT_PCS_DW_AUX(dw, phy) (_ICL_COMBOPHY(phy) + \
> _ICL_PORT_PCS_AUX + 4 * (dw))
> -#define _ICL_PORT_PCS_DW_GRP(dw, port) (_ICL_COMBOPHY(port) + \
> +#define _ICL_PORT_PCS_DW_GRP(dw, phy) (_ICL_COMBOPHY(phy) + \
> _ICL_PORT_PCS_GRP + 4 * (dw))
> -#define _ICL_PORT_PCS_DW_LN(dw, ln, port) (_ICL_COMBOPHY(port) + \
> +#define _ICL_PORT_PCS_DW_LN(dw, ln, phy) (_ICL_COMBOPHY(phy) + \
> _ICL_PORT_PCS_LN(ln) + 4 * (dw))
> -#define ICL_PORT_PCS_DW1_AUX(port) _MMIO(_ICL_PORT_PCS_DW_AUX(1, port))
> -#define ICL_PORT_PCS_DW1_GRP(port) _MMIO(_ICL_PORT_PCS_DW_GRP(1, port))
> -#define ICL_PORT_PCS_DW1_LN0(port) _MMIO(_ICL_PORT_PCS_DW_LN(1, 0, port))
> +#define ICL_PORT_PCS_DW1_AUX(phy) _MMIO(_ICL_PORT_PCS_DW_AUX(1, phy))
> +#define ICL_PORT_PCS_DW1_GRP(phy) _MMIO(_ICL_PORT_PCS_DW_GRP(1, phy))
> +#define ICL_PORT_PCS_DW1_LN0(phy) _MMIO(_ICL_PORT_PCS_DW_LN(1, 0, phy))
> #define COMMON_KEEPER_EN (1 << 26)
> #define LATENCY_OPTIM_MASK (0x3 << 2)
> #define LATENCY_OPTIM_VAL(x) ((x) << 2)
> @@ -1933,18 +1933,18 @@ enum i915_power_well_id {
> #define _ICL_PORT_TX_GRP 0x680
> #define _ICL_PORT_TX_LN(ln) (0x880 + (ln) * 0x100)
>
> -#define _ICL_PORT_TX_DW_AUX(dw, port) (_ICL_COMBOPHY(port) + \
> +#define _ICL_PORT_TX_DW_AUX(dw, phy) (_ICL_COMBOPHY(phy) + \
> _ICL_PORT_TX_AUX + 4 * (dw))
> -#define _ICL_PORT_TX_DW_GRP(dw, port) (_ICL_COMBOPHY(port) + \
> +#define _ICL_PORT_TX_DW_GRP(dw, phy) (_ICL_COMBOPHY(phy) + \
> _ICL_PORT_TX_GRP + 4 * (dw))
> -#define _ICL_PORT_TX_DW_LN(dw, ln, port) (_ICL_COMBOPHY(port) + \
> +#define _ICL_PORT_TX_DW_LN(dw, ln, phy) (_ICL_COMBOPHY(phy) + \
> _ICL_PORT_TX_LN(ln) + 4 * (dw))
>
> #define CNL_PORT_TX_DW2_GRP(port) _MMIO(_CNL_PORT_TX_DW_GRP(2, port))
> #define CNL_PORT_TX_DW2_LN0(port) _MMIO(_CNL_PORT_TX_DW_LN0(2, port))
> -#define ICL_PORT_TX_DW2_AUX(port) _MMIO(_ICL_PORT_TX_DW_AUX(2, port))
> -#define ICL_PORT_TX_DW2_GRP(port) _MMIO(_ICL_PORT_TX_DW_GRP(2, port))
> -#define ICL_PORT_TX_DW2_LN0(port) _MMIO(_ICL_PORT_TX_DW_LN(2, 0, port))
> +#define ICL_PORT_TX_DW2_AUX(phy) _MMIO(_ICL_PORT_TX_DW_AUX(2, phy))
> +#define ICL_PORT_TX_DW2_GRP(phy) _MMIO(_ICL_PORT_TX_DW_GRP(2, phy))
> +#define ICL_PORT_TX_DW2_LN0(phy) _MMIO(_ICL_PORT_TX_DW_LN(2, 0, phy))
> #define SWING_SEL_UPPER(x) (((x) >> 3) << 15)
> #define SWING_SEL_UPPER_MASK (1 << 15)
> #define SWING_SEL_LOWER(x) (((x) & 0x7) << 11)
> @@ -1961,10 +1961,10 @@ enum i915_power_well_id {
> #define CNL_PORT_TX_DW4_LN(ln, port) _MMIO(_CNL_PORT_TX_DW_LN0(4, (port)) + \
> ((ln) * (_CNL_PORT_TX_DW4_LN1_AE - \
> _CNL_PORT_TX_DW4_LN0_AE)))
> -#define ICL_PORT_TX_DW4_AUX(port) _MMIO(_ICL_PORT_TX_DW_AUX(4, port))
> -#define ICL_PORT_TX_DW4_GRP(port) _MMIO(_ICL_PORT_TX_DW_GRP(4, port))
> -#define ICL_PORT_TX_DW4_LN0(port) _MMIO(_ICL_PORT_TX_DW_LN(4, 0, port))
> -#define ICL_PORT_TX_DW4_LN(ln, port) _MMIO(_ICL_PORT_TX_DW_LN(4, ln, port))
> +#define ICL_PORT_TX_DW4_AUX(phy) _MMIO(_ICL_PORT_TX_DW_AUX(4, phy))
> +#define ICL_PORT_TX_DW4_GRP(phy) _MMIO(_ICL_PORT_TX_DW_GRP(4, phy))
> +#define ICL_PORT_TX_DW4_LN0(phy) _MMIO(_ICL_PORT_TX_DW_LN(4, 0, phy))
> +#define ICL_PORT_TX_DW4_LN(ln, phy) _MMIO(_ICL_PORT_TX_DW_LN(4, ln, phy))
> #define LOADGEN_SELECT (1 << 31)
> #define POST_CURSOR_1(x) ((x) << 12)
> #define POST_CURSOR_1_MASK (0x3F << 12)
> @@ -1975,9 +1975,9 @@ enum i915_power_well_id {
>
> #define CNL_PORT_TX_DW5_GRP(port) _MMIO(_CNL_PORT_TX_DW_GRP(5, port))
> #define CNL_PORT_TX_DW5_LN0(port) _MMIO(_CNL_PORT_TX_DW_LN0(5, port))
> -#define ICL_PORT_TX_DW5_AUX(port) _MMIO(_ICL_PORT_TX_DW_AUX(5, port))
> -#define ICL_PORT_TX_DW5_GRP(port) _MMIO(_ICL_PORT_TX_DW_GRP(5, port))
> -#define ICL_PORT_TX_DW5_LN0(port) _MMIO(_ICL_PORT_TX_DW_LN(5, 0, port))
> +#define ICL_PORT_TX_DW5_AUX(phy) _MMIO(_ICL_PORT_TX_DW_AUX(5, phy))
> +#define ICL_PORT_TX_DW5_GRP(phy) _MMIO(_ICL_PORT_TX_DW_GRP(5, phy))
> +#define ICL_PORT_TX_DW5_LN0(phy) _MMIO(_ICL_PORT_TX_DW_LN(5, 0, phy))
> #define TX_TRAINING_EN (1 << 31)
> #define TAP2_DISABLE (1 << 30)
> #define TAP3_DISABLE (1 << 29)
> @@ -1988,10 +1988,10 @@ enum i915_power_well_id {
>
> #define CNL_PORT_TX_DW7_GRP(port) _MMIO(_CNL_PORT_TX_DW_GRP(7, (port)))
> #define CNL_PORT_TX_DW7_LN0(port) _MMIO(_CNL_PORT_TX_DW_LN0(7, (port)))
> -#define ICL_PORT_TX_DW7_AUX(port) _MMIO(_ICL_PORT_TX_DW_AUX(7, port))
> -#define ICL_PORT_TX_DW7_GRP(port) _MMIO(_ICL_PORT_TX_DW_GRP(7, port))
> -#define ICL_PORT_TX_DW7_LN0(port) _MMIO(_ICL_PORT_TX_DW_LN(7, 0, port))
> -#define ICL_PORT_TX_DW7_LN(ln, port) _MMIO(_ICL_PORT_TX_DW_LN(7, ln, port))
> +#define ICL_PORT_TX_DW7_AUX(phy) _MMIO(_ICL_PORT_TX_DW_AUX(7, phy))
> +#define ICL_PORT_TX_DW7_GRP(phy) _MMIO(_ICL_PORT_TX_DW_GRP(7, phy))
> +#define ICL_PORT_TX_DW7_LN0(phy) _MMIO(_ICL_PORT_TX_DW_LN(7, 0, phy))
> +#define ICL_PORT_TX_DW7_LN(ln, phy) _MMIO(_ICL_PORT_TX_DW_LN(7, ln, phy))
> #define N_SCALAR(x) ((x) << 24)
> #define N_SCALAR_MASK (0x7F << 24)
>
> --
> 2.17.2
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: [PATCH v4 1/5] drm/i915/gen11: Start distinguishing 'phy' from 'port'
2019-07-04 9:18 ` Ville Syrjälä
2019-07-04 9:24 ` Ville Syrjälä
@ 2019-07-04 14:54 ` Lucas De Marchi
2019-07-04 15:09 ` Ville Syrjälä
1 sibling, 1 reply; 33+ messages in thread
From: Lucas De Marchi @ 2019-07-04 14:54 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: Jani Nikula, intel-gfx
On Thu, Jul 04, 2019 at 12:18:11PM +0300, Ville Syrjälä wrote:
>On Wed, Jul 03, 2019 at 04:37:32PM -0700, Matt Roper wrote:
>> Our past DDI-based Intel platforms have had a fixed DDI<->PHY mapping.
>> Because of this, both the bspec documentation and our i915 code has used
>> the term "port" when talking about either DDI's or PHY's; it was always
>> easy to tell what terms like "Port A" were referring to from the
>> context.
>>
>> Unfortunately this is starting to break down now that EHL allows PHY-A
>> to be driven by either DDI-A or DDI-D. Is a setup with DDI-D driving
>> PHY-A considered "Port A" or "Port D?" The answer depends on which
>> register we're working with, and even the bspec doesn't do a great job
>> of clarifying this.
>>
>> Let's try to be more explicit about whether we're talking about the DDI
>> or the PHY on gen11+ by using 'port' to refer to the DDI and creating a
>> new 'enum phy' namespace to refer to the PHY in use.
>>
>> This patch just adds the new PHY namespace, new phy-based versions of
>> intel_port_is_*(), and a helper to convert a port to a PHY.
>> Transitioning various areas of the code over to using the PHY namespace
>> will be done in subsequent patches to make review easier. We'll remove
>> the intel_port_is_*() functions at the end of the series when we
>> transition all callers over to using the PHY-based versions.
>>
>> v2:
>> - Convert a few more 'port' uses to 'phy.' (Sparse)
>>
>> v3:
>> - Switch DDI_CLK_SEL() back to 'port.' (Jose)
>> - Add a code comment clarifying why DPCLKA_CFGCR0_ICL needs to use PHY
>> for its bit definitions, even though the register description is
>> given in terms of DDI.
>> - To avoid confusion, switch CNL's DPCLKA_CFGCR0 defines back to using
>> port and create separate ICL+ definitions that work in terms of PHY.
>>
>> v4:
>> - Rebase and resolve conflicts with Imre's TC series.
>> - This patch now just adds the namespace and a few convenience
>> functions; the important changes are now split out into separate
>> patches to make review easier.
>>
>> Suggested-by: Ville Syrjala <ville.syrjala@linux.intel.com>
>> Cc: José Roberto de Souza <jose.souza@intel.com>
>> Cc: Lucas De Marchi <lucas.demarchi@intel.com>
>> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
>> Cc: Imre Deak <imre.deak@intel.com>
>> Cc: Jani Nikula <jani.nikula@intel.com>
>> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
>> ---
>> drivers/gpu/drm/i915/display/intel_display.c | 32 +++++++++++++++++++-
>> drivers/gpu/drm/i915/display/intel_display.h | 16 ++++++++++
>> drivers/gpu/drm/i915/intel_drv.h | 2 ++
>> 3 files changed, 49 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
>> index 919f5ac844c8..4a85abef93e7 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display.c
>> +++ b/drivers/gpu/drm/i915/display/intel_display.c
>> @@ -6663,6 +6663,20 @@ bool intel_port_is_combophy(struct drm_i915_private *dev_priv, enum port port)
>> return false;
>> }
>>
>> +bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy phy)
>> +{
>> + if (phy == PHY_NONE)
>> + return false;
>> +
>> + if (IS_ELKHARTLAKE(dev_priv))
>> + return phy <= PHY_C;
>> +
>> + if (INTEL_GEN(dev_priv) >= 11)
>> + return phy <= PHY_B;
>> +
>> + return false;
>> +}
>> +
>> bool intel_port_is_tc(struct drm_i915_private *dev_priv, enum port port)
>> {
>> if (INTEL_GEN(dev_priv) >= 11 && !IS_ELKHARTLAKE(dev_priv))
>> @@ -6671,9 +6685,25 @@ bool intel_port_is_tc(struct drm_i915_private *dev_priv, enum port port)
>> return false;
>> }
>>
>> +bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy)
>> +{
>> + if (INTEL_GEN(dev_priv) >= 11 && !IS_ELKHARTLAKE(dev_priv))
>> + return phy >= PHY_C && phy <= PHY_F;
>> +
>> + return false;
>> +}
>> +
>> +enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port)
>> +{
>> + if (IS_ELKHARTLAKE(i915) && port == PORT_D)
>> + return PHY_A;
>> +
>> + return (enum phy)port;
>> +}
>> +
>> enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv, enum port port)
>> {
>> - if (!intel_port_is_tc(dev_priv, port))
>> + if (!intel_phy_is_tc(dev_priv, intel_port_to_phy(dev_priv, port)))
>> return PORT_TC_NONE;
>>
>> return port - PORT_C;
>> diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
>> index d296556ed82e..d53285fb883f 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display.h
>> +++ b/drivers/gpu/drm/i915/display/intel_display.h
>> @@ -228,6 +228,21 @@ struct intel_link_m_n {
>> u32 link_n;
>> };
>>
>> +enum phy {
>> + PHY_NONE = -1,
>> +
>> + PHY_A = 0,
>> + PHY_B,
>> + PHY_C,
>> + PHY_D,
>> + PHY_E,
>> + PHY_F,
>> +
>> + I915_MAX_PHYS
>> +};
>
>I was pondering if we could eventually do something like:
>
>enum phy {
> PHY_COMBO_A = 0,
> PHY_COMBO_B,
> ...
>
> PHY_TC_1,
> PHY_TC_2,
> ...
>};
>
>and probably also add encoder->phy so we can contain
>that port<->phy mapping logic in the encoder init.
>I think that should work more or less fine since I
>don't think PHY_TC_1 needs to have any specific value.
that's not true. All TC registers are based off the TC phy number.
Hence all the conversion we do port_to_tc()... I'd like to remove that
in future and just stuff the phy index in intel_digital_port, as we
already do for other tc_phy_* fields (we could add a union there so each
phy adds its own fields).
And I'd rather not do the single phy namespace - it doesn't
play well with TGL and the combo/tc.
Lucas De Marchi
>
>Unfortunaltey I don't have a great idea how to do the
>same for the DDIs since there the number of combo DDIs
>changes but we still need the PORT_TC1 (assuming we had
>one) to be DDI_<last combo DDI> + 1. One random silly
>idea was to decouple the enum port from the register
>definitions by having just some kind of
>encoder->port_index for those. But that doesn't feel
>entirely great either.
>
>Anyways, something to think about in the future perhaps.
>
>Patch is
>Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
>> +
>> +#define phy_name(a) ((a) + 'A')
>> +
>> #define for_each_pipe(__dev_priv, __p) \
>> for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++)
>>
>> @@ -356,5 +371,6 @@ void lpt_disable_clkout_dp(struct drm_i915_private *dev_priv);
>> u32 intel_plane_fb_max_stride(struct drm_i915_private *dev_priv,
>> u32 pixel_format, u64 modifier);
>> bool intel_plane_can_remap(const struct intel_plane_state *plane_state);
>> +enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port);
>>
>> #endif
>> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
>> index 24c63ed45c6f..815c26c0b98c 100644
>> --- a/drivers/gpu/drm/i915/intel_drv.h
>> +++ b/drivers/gpu/drm/i915/intel_drv.h
>> @@ -1493,7 +1493,9 @@ void intel_encoder_destroy(struct drm_encoder *encoder);
>> struct drm_display_mode *
>> intel_encoder_current_mode(struct intel_encoder *encoder);
>> bool intel_port_is_combophy(struct drm_i915_private *dev_priv, enum port port);
>> +bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy phy);
>> bool intel_port_is_tc(struct drm_i915_private *dev_priv, enum port port);
>> +bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy);
>> enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv,
>> enum port port);
>> int intel_get_pipe_from_crtc_id_ioctl(struct drm_device *dev, void *data,
>> --
>> 2.17.2
>
>--
>Ville Syrjälä
>Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: [PATCH v4 1/5] drm/i915/gen11: Start distinguishing 'phy' from 'port'
2019-07-04 14:54 ` Lucas De Marchi
@ 2019-07-04 15:09 ` Ville Syrjälä
2019-07-04 15:55 ` Lucas De Marchi
0 siblings, 1 reply; 33+ messages in thread
From: Ville Syrjälä @ 2019-07-04 15:09 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: Jani Nikula, intel-gfx
On Thu, Jul 04, 2019 at 07:54:26AM -0700, Lucas De Marchi wrote:
> On Thu, Jul 04, 2019 at 12:18:11PM +0300, Ville Syrjälä wrote:
> >On Wed, Jul 03, 2019 at 04:37:32PM -0700, Matt Roper wrote:
> >> Our past DDI-based Intel platforms have had a fixed DDI<->PHY mapping.
> >> Because of this, both the bspec documentation and our i915 code has used
> >> the term "port" when talking about either DDI's or PHY's; it was always
> >> easy to tell what terms like "Port A" were referring to from the
> >> context.
> >>
> >> Unfortunately this is starting to break down now that EHL allows PHY-A
> >> to be driven by either DDI-A or DDI-D. Is a setup with DDI-D driving
> >> PHY-A considered "Port A" or "Port D?" The answer depends on which
> >> register we're working with, and even the bspec doesn't do a great job
> >> of clarifying this.
> >>
> >> Let's try to be more explicit about whether we're talking about the DDI
> >> or the PHY on gen11+ by using 'port' to refer to the DDI and creating a
> >> new 'enum phy' namespace to refer to the PHY in use.
> >>
> >> This patch just adds the new PHY namespace, new phy-based versions of
> >> intel_port_is_*(), and a helper to convert a port to a PHY.
> >> Transitioning various areas of the code over to using the PHY namespace
> >> will be done in subsequent patches to make review easier. We'll remove
> >> the intel_port_is_*() functions at the end of the series when we
> >> transition all callers over to using the PHY-based versions.
> >>
> >> v2:
> >> - Convert a few more 'port' uses to 'phy.' (Sparse)
> >>
> >> v3:
> >> - Switch DDI_CLK_SEL() back to 'port.' (Jose)
> >> - Add a code comment clarifying why DPCLKA_CFGCR0_ICL needs to use PHY
> >> for its bit definitions, even though the register description is
> >> given in terms of DDI.
> >> - To avoid confusion, switch CNL's DPCLKA_CFGCR0 defines back to using
> >> port and create separate ICL+ definitions that work in terms of PHY.
> >>
> >> v4:
> >> - Rebase and resolve conflicts with Imre's TC series.
> >> - This patch now just adds the namespace and a few convenience
> >> functions; the important changes are now split out into separate
> >> patches to make review easier.
> >>
> >> Suggested-by: Ville Syrjala <ville.syrjala@linux.intel.com>
> >> Cc: José Roberto de Souza <jose.souza@intel.com>
> >> Cc: Lucas De Marchi <lucas.demarchi@intel.com>
> >> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >> Cc: Imre Deak <imre.deak@intel.com>
> >> Cc: Jani Nikula <jani.nikula@intel.com>
> >> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> >> ---
> >> drivers/gpu/drm/i915/display/intel_display.c | 32 +++++++++++++++++++-
> >> drivers/gpu/drm/i915/display/intel_display.h | 16 ++++++++++
> >> drivers/gpu/drm/i915/intel_drv.h | 2 ++
> >> 3 files changed, 49 insertions(+), 1 deletion(-)
> >>
> >> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> >> index 919f5ac844c8..4a85abef93e7 100644
> >> --- a/drivers/gpu/drm/i915/display/intel_display.c
> >> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> >> @@ -6663,6 +6663,20 @@ bool intel_port_is_combophy(struct drm_i915_private *dev_priv, enum port port)
> >> return false;
> >> }
> >>
> >> +bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy phy)
> >> +{
> >> + if (phy == PHY_NONE)
> >> + return false;
> >> +
> >> + if (IS_ELKHARTLAKE(dev_priv))
> >> + return phy <= PHY_C;
> >> +
> >> + if (INTEL_GEN(dev_priv) >= 11)
> >> + return phy <= PHY_B;
> >> +
> >> + return false;
> >> +}
> >> +
> >> bool intel_port_is_tc(struct drm_i915_private *dev_priv, enum port port)
> >> {
> >> if (INTEL_GEN(dev_priv) >= 11 && !IS_ELKHARTLAKE(dev_priv))
> >> @@ -6671,9 +6685,25 @@ bool intel_port_is_tc(struct drm_i915_private *dev_priv, enum port port)
> >> return false;
> >> }
> >>
> >> +bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy)
> >> +{
> >> + if (INTEL_GEN(dev_priv) >= 11 && !IS_ELKHARTLAKE(dev_priv))
> >> + return phy >= PHY_C && phy <= PHY_F;
> >> +
> >> + return false;
> >> +}
> >> +
> >> +enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port)
> >> +{
> >> + if (IS_ELKHARTLAKE(i915) && port == PORT_D)
> >> + return PHY_A;
> >> +
> >> + return (enum phy)port;
> >> +}
> >> +
> >> enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv, enum port port)
> >> {
> >> - if (!intel_port_is_tc(dev_priv, port))
> >> + if (!intel_phy_is_tc(dev_priv, intel_port_to_phy(dev_priv, port)))
> >> return PORT_TC_NONE;
> >>
> >> return port - PORT_C;
> >> diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
> >> index d296556ed82e..d53285fb883f 100644
> >> --- a/drivers/gpu/drm/i915/display/intel_display.h
> >> +++ b/drivers/gpu/drm/i915/display/intel_display.h
> >> @@ -228,6 +228,21 @@ struct intel_link_m_n {
> >> u32 link_n;
> >> };
> >>
> >> +enum phy {
> >> + PHY_NONE = -1,
> >> +
> >> + PHY_A = 0,
> >> + PHY_B,
> >> + PHY_C,
> >> + PHY_D,
> >> + PHY_E,
> >> + PHY_F,
> >> +
> >> + I915_MAX_PHYS
> >> +};
> >
> >I was pondering if we could eventually do something like:
> >
> >enum phy {
> > PHY_COMBO_A = 0,
> > PHY_COMBO_B,
> > ...
> >
> > PHY_TC_1,
> > PHY_TC_2,
> > ...
> >};
> >
> >and probably also add encoder->phy so we can contain
> >that port<->phy mapping logic in the encoder init.
> >I think that should work more or less fine since I
> >don't think PHY_TC_1 needs to have any specific value.
>
> that's not true. All TC registers are based off the TC phy number.
That's just a trivial (x)-TC1, so I stand by what I said.
> Hence all the conversion we do port_to_tc()... I'd like to remove that
> in future and just stuff the phy index in intel_digital_port, as we
> already do for other tc_phy_* fields (we could add a union there so each
> phy adds its own fields).
>
> And I'd rather not do the single phy namespace - it doesn't
> play well with TGL and the combo/tc.
I think it would work just fine for that. A single namespace would allow
us to remove all the crazy port->PHY type mapping we have going on
currently. Probably the best alternative would be separate namespaces
for each type with a new enum to identify the type.
>
> Lucas De Marchi
>
> >
> >Unfortunaltey I don't have a great idea how to do the
> >same for the DDIs since there the number of combo DDIs
> >changes but we still need the PORT_TC1 (assuming we had
> >one) to be DDI_<last combo DDI> + 1. One random silly
> >idea was to decouple the enum port from the register
> >definitions by having just some kind of
> >encoder->port_index for those. But that doesn't feel
> >entirely great either.
> >
> >Anyways, something to think about in the future perhaps.
> >
> >Patch is
> >Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> >> +
> >> +#define phy_name(a) ((a) + 'A')
> >> +
> >> #define for_each_pipe(__dev_priv, __p) \
> >> for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++)
> >>
> >> @@ -356,5 +371,6 @@ void lpt_disable_clkout_dp(struct drm_i915_private *dev_priv);
> >> u32 intel_plane_fb_max_stride(struct drm_i915_private *dev_priv,
> >> u32 pixel_format, u64 modifier);
> >> bool intel_plane_can_remap(const struct intel_plane_state *plane_state);
> >> +enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port);
> >>
> >> #endif
> >> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> >> index 24c63ed45c6f..815c26c0b98c 100644
> >> --- a/drivers/gpu/drm/i915/intel_drv.h
> >> +++ b/drivers/gpu/drm/i915/intel_drv.h
> >> @@ -1493,7 +1493,9 @@ void intel_encoder_destroy(struct drm_encoder *encoder);
> >> struct drm_display_mode *
> >> intel_encoder_current_mode(struct intel_encoder *encoder);
> >> bool intel_port_is_combophy(struct drm_i915_private *dev_priv, enum port port);
> >> +bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy phy);
> >> bool intel_port_is_tc(struct drm_i915_private *dev_priv, enum port port);
> >> +bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy);
> >> enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv,
> >> enum port port);
> >> int intel_get_pipe_from_crtc_id_ioctl(struct drm_device *dev, void *data,
> >> --
> >> 2.17.2
> >
> >--
> >Ville Syrjälä
> >Intel
--
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: [PATCH v4 1/5] drm/i915/gen11: Start distinguishing 'phy' from 'port'
2019-07-04 15:09 ` Ville Syrjälä
@ 2019-07-04 15:55 ` Lucas De Marchi
2019-07-05 10:33 ` Ville Syrjälä
0 siblings, 1 reply; 33+ messages in thread
From: Lucas De Marchi @ 2019-07-04 15:55 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: Jani Nikula, intel-gfx
On Thu, Jul 04, 2019 at 06:09:04PM +0300, Ville Syrjälä wrote:
>On Thu, Jul 04, 2019 at 07:54:26AM -0700, Lucas De Marchi wrote:
>> On Thu, Jul 04, 2019 at 12:18:11PM +0300, Ville Syrjälä wrote:
>> >On Wed, Jul 03, 2019 at 04:37:32PM -0700, Matt Roper wrote:
>> >> Our past DDI-based Intel platforms have had a fixed DDI<->PHY mapping.
>> >> Because of this, both the bspec documentation and our i915 code has used
>> >> the term "port" when talking about either DDI's or PHY's; it was always
>> >> easy to tell what terms like "Port A" were referring to from the
>> >> context.
>> >>
>> >> Unfortunately this is starting to break down now that EHL allows PHY-A
>> >> to be driven by either DDI-A or DDI-D. Is a setup with DDI-D driving
>> >> PHY-A considered "Port A" or "Port D?" The answer depends on which
>> >> register we're working with, and even the bspec doesn't do a great job
>> >> of clarifying this.
>> >>
>> >> Let's try to be more explicit about whether we're talking about the DDI
>> >> or the PHY on gen11+ by using 'port' to refer to the DDI and creating a
>> >> new 'enum phy' namespace to refer to the PHY in use.
>> >>
>> >> This patch just adds the new PHY namespace, new phy-based versions of
>> >> intel_port_is_*(), and a helper to convert a port to a PHY.
>> >> Transitioning various areas of the code over to using the PHY namespace
>> >> will be done in subsequent patches to make review easier. We'll remove
>> >> the intel_port_is_*() functions at the end of the series when we
>> >> transition all callers over to using the PHY-based versions.
>> >>
>> >> v2:
>> >> - Convert a few more 'port' uses to 'phy.' (Sparse)
>> >>
>> >> v3:
>> >> - Switch DDI_CLK_SEL() back to 'port.' (Jose)
>> >> - Add a code comment clarifying why DPCLKA_CFGCR0_ICL needs to use PHY
>> >> for its bit definitions, even though the register description is
>> >> given in terms of DDI.
>> >> - To avoid confusion, switch CNL's DPCLKA_CFGCR0 defines back to using
>> >> port and create separate ICL+ definitions that work in terms of PHY.
>> >>
>> >> v4:
>> >> - Rebase and resolve conflicts with Imre's TC series.
>> >> - This patch now just adds the namespace and a few convenience
>> >> functions; the important changes are now split out into separate
>> >> patches to make review easier.
>> >>
>> >> Suggested-by: Ville Syrjala <ville.syrjala@linux.intel.com>
>> >> Cc: José Roberto de Souza <jose.souza@intel.com>
>> >> Cc: Lucas De Marchi <lucas.demarchi@intel.com>
>> >> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
>> >> Cc: Imre Deak <imre.deak@intel.com>
>> >> Cc: Jani Nikula <jani.nikula@intel.com>
>> >> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
>> >> ---
>> >> drivers/gpu/drm/i915/display/intel_display.c | 32 +++++++++++++++++++-
>> >> drivers/gpu/drm/i915/display/intel_display.h | 16 ++++++++++
>> >> drivers/gpu/drm/i915/intel_drv.h | 2 ++
>> >> 3 files changed, 49 insertions(+), 1 deletion(-)
>> >>
>> >> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
>> >> index 919f5ac844c8..4a85abef93e7 100644
>> >> --- a/drivers/gpu/drm/i915/display/intel_display.c
>> >> +++ b/drivers/gpu/drm/i915/display/intel_display.c
>> >> @@ -6663,6 +6663,20 @@ bool intel_port_is_combophy(struct drm_i915_private *dev_priv, enum port port)
>> >> return false;
>> >> }
>> >>
>> >> +bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy phy)
>> >> +{
>> >> + if (phy == PHY_NONE)
>> >> + return false;
>> >> +
>> >> + if (IS_ELKHARTLAKE(dev_priv))
>> >> + return phy <= PHY_C;
>> >> +
>> >> + if (INTEL_GEN(dev_priv) >= 11)
>> >> + return phy <= PHY_B;
>> >> +
>> >> + return false;
>> >> +}
>> >> +
>> >> bool intel_port_is_tc(struct drm_i915_private *dev_priv, enum port port)
>> >> {
>> >> if (INTEL_GEN(dev_priv) >= 11 && !IS_ELKHARTLAKE(dev_priv))
>> >> @@ -6671,9 +6685,25 @@ bool intel_port_is_tc(struct drm_i915_private *dev_priv, enum port port)
>> >> return false;
>> >> }
>> >>
>> >> +bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy)
>> >> +{
>> >> + if (INTEL_GEN(dev_priv) >= 11 && !IS_ELKHARTLAKE(dev_priv))
>> >> + return phy >= PHY_C && phy <= PHY_F;
>> >> +
>> >> + return false;
>> >> +}
>> >> +
>> >> +enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port)
>> >> +{
>> >> + if (IS_ELKHARTLAKE(i915) && port == PORT_D)
>> >> + return PHY_A;
>> >> +
>> >> + return (enum phy)port;
>> >> +}
>> >> +
>> >> enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv, enum port port)
>> >> {
>> >> - if (!intel_port_is_tc(dev_priv, port))
>> >> + if (!intel_phy_is_tc(dev_priv, intel_port_to_phy(dev_priv, port)))
>> >> return PORT_TC_NONE;
>> >>
>> >> return port - PORT_C;
>> >> diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
>> >> index d296556ed82e..d53285fb883f 100644
>> >> --- a/drivers/gpu/drm/i915/display/intel_display.h
>> >> +++ b/drivers/gpu/drm/i915/display/intel_display.h
>> >> @@ -228,6 +228,21 @@ struct intel_link_m_n {
>> >> u32 link_n;
>> >> };
>> >>
>> >> +enum phy {
>> >> + PHY_NONE = -1,
>> >> +
>> >> + PHY_A = 0,
>> >> + PHY_B,
>> >> + PHY_C,
>> >> + PHY_D,
>> >> + PHY_E,
>> >> + PHY_F,
>> >> +
>> >> + I915_MAX_PHYS
>> >> +};
>> >
>> >I was pondering if we could eventually do something like:
>> >
>> >enum phy {
>> > PHY_COMBO_A = 0,
>> > PHY_COMBO_B,
>> > ...
>> >
>> > PHY_TC_1,
>> > PHY_TC_2,
>> > ...
>> >};
>> >
>> >and probably also add encoder->phy so we can contain
>> >that port<->phy mapping logic in the encoder init.
>> >I think that should work more or less fine since I
>> >don't think PHY_TC_1 needs to have any specific value.
>>
>> that's not true. All TC registers are based off the TC phy number.
>
>That's just a trivial (x)-TC1, so I stand by what I said.
EHL and TGL have 3 combo phys. ICL has 2. So TC1 would have to be a
different value for ICL and the others for this to work.
I think we should treat the index as just a number we use to compute the
right base for the registers in that hw IP.
>
>> Hence all the conversion we do port_to_tc()... I'd like to remove that
>> in future and just stuff the phy index in intel_digital_port, as we
>> already do for other tc_phy_* fields (we could add a union there so each
>> phy adds its own fields).
>>
>> And I'd rather not do the single phy namespace - it doesn't
>> play well with TGL and the combo/tc.
>
>I think it would work just fine for that. A single namespace would allow
>us to remove all the crazy port->PHY type mapping we have going on
>currently. Probably the best alternative would be separate namespaces
>for each type with a new enum to identify the type.
My proposal is in the lines of that alternative approach. Save the phy
type and the phy index in intel_digital_port. And allow each phy to store
its fields there. Something along:
struct intel_digital_port {
...
struct {
enum phy_type type;
u8 idx;
union {
struct {
struct mutex lock; /* protects the TypeC port mode */
intel_wakeref_t lock_wakeref;
int link_refcount;
char tc_port_name[8];
enum tc_port_mode tc_mode;
bool legacy_port;
u8 fia;
} tc;
struct {
...
} combo;
struct {
...
} dpio??;
};
} phy;
};
From a quick look I don't think the idx is relevant enough to have its
own enum, but I wouldn't mind.
then no more port->phy everywhere as we have right now and we only
assign idx to the right value during init. The TC rework we had recently
makes it nice and I'm starting to do it, but I'd rather merge the TGL
patches before. For Modular FIA I'm already stashing the fia index
there (since I had to redo the support due to the TC rework),
but without the additional struct.
See https://patchwork.freedesktop.org/series/63175/
Lucas De Marchi
>
>>
>> Lucas De Marchi
>>
>> >
>> >Unfortunaltey I don't have a great idea how to do the
>> >same for the DDIs since there the number of combo DDIs
>> >changes but we still need the PORT_TC1 (assuming we had
>> >one) to be DDI_<last combo DDI> + 1. One random silly
>> >idea was to decouple the enum port from the register
>> >definitions by having just some kind of
>> >encoder->port_index for those. But that doesn't feel
>> >entirely great either.
>> >
>> >Anyways, something to think about in the future perhaps.
>> >
>> >Patch is
>> >Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>> >
>> >> +
>> >> +#define phy_name(a) ((a) + 'A')
>> >> +
>> >> #define for_each_pipe(__dev_priv, __p) \
>> >> for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++)
>> >>
>> >> @@ -356,5 +371,6 @@ void lpt_disable_clkout_dp(struct drm_i915_private *dev_priv);
>> >> u32 intel_plane_fb_max_stride(struct drm_i915_private *dev_priv,
>> >> u32 pixel_format, u64 modifier);
>> >> bool intel_plane_can_remap(const struct intel_plane_state *plane_state);
>> >> +enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port);
>> >>
>> >> #endif
>> >> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
>> >> index 24c63ed45c6f..815c26c0b98c 100644
>> >> --- a/drivers/gpu/drm/i915/intel_drv.h
>> >> +++ b/drivers/gpu/drm/i915/intel_drv.h
>> >> @@ -1493,7 +1493,9 @@ void intel_encoder_destroy(struct drm_encoder *encoder);
>> >> struct drm_display_mode *
>> >> intel_encoder_current_mode(struct intel_encoder *encoder);
>> >> bool intel_port_is_combophy(struct drm_i915_private *dev_priv, enum port port);
>> >> +bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy phy);
>> >> bool intel_port_is_tc(struct drm_i915_private *dev_priv, enum port port);
>> >> +bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy);
>> >> enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv,
>> >> enum port port);
>> >> int intel_get_pipe_from_crtc_id_ioctl(struct drm_device *dev, void *data,
>> >> --
>> >> 2.17.2
>> >
>> >--
>> >Ville Syrjälä
>> >Intel
>
>--
>Ville Syrjälä
>Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: [PATCH v4 4/5] drm/i915: Transition port type checks to phy checks
2019-07-03 23:37 ` [PATCH v4 4/5] drm/i915: Transition port type checks to phy checks Matt Roper
2019-07-04 0:02 ` [PATCH v5 " Matt Roper
@ 2019-07-04 16:07 ` kbuild test robot
2019-07-09 1:00 ` Souza, Jose
2 siblings, 0 replies; 33+ messages in thread
From: kbuild test robot @ 2019-07-04 16:07 UTC (permalink / raw)
To: Matt Roper; +Cc: intel-gfx, kbuild-all
[-- Attachment #1: Type: text/plain, Size: 3544 bytes --]
Hi Matt,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on drm-intel/for-linux-next]
[also build test ERROR on next-20190704]
[cannot apply to v5.2-rc7]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]
url: https://github.com/0day-ci/linux/commits/Matt-Roper/EHL-port-programming/20190704-143105
base: git://anongit.freedesktop.org/drm-intel for-linux-next
config: x86_64-allyesconfig (attached as .config)
compiler: gcc-7 (Debian 7.4.0-6) 7.4.0
reproduce:
# save the attached .config to linux build tree
make ARCH=x86_64
If you fix the issue, kindly add following tag
Reported-by: kbuild test robot <lkp@intel.com>
All errors (new ones prefixed by >>):
drivers/gpu/drm/i915/display/intel_display_power.c: In function 'icl_tc_port_assert_ref_held':
>> drivers/gpu/drm/i915/display/intel_display_power.c:490:36: error: incompatible type for argument 1 of 'intel_port_to_phy'
enum phy phy = intel_port_to_phy(encoder->port);
^~~~~~~
In file included from drivers/gpu/drm/i915/i915_drv.h:67:0,
from drivers/gpu/drm/i915/display/intel_display_power.c:11:
drivers/gpu/drm/i915/display/intel_display.h:378:10: note: expected 'struct drm_i915_private *' but argument is of type 'enum port'
enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port);
^~~~~~~~~~~~~~~~~
>> drivers/gpu/drm/i915/display/intel_display_power.c:490:18: error: too few arguments to function 'intel_port_to_phy'
enum phy phy = intel_port_to_phy(encoder->port);
^~~~~~~~~~~~~~~~~
In file included from drivers/gpu/drm/i915/i915_drv.h:67:0,
from drivers/gpu/drm/i915/display/intel_display_power.c:11:
drivers/gpu/drm/i915/display/intel_display.h:378:10: note: declared here
enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port);
^~~~~~~~~~~~~~~~~
vim +/intel_port_to_phy +490 drivers/gpu/drm/i915/display/intel_display_power.c
474
475 static void icl_tc_port_assert_ref_held(struct drm_i915_private *dev_priv,
476 struct i915_power_well *power_well)
477 {
478 enum aux_ch aux_ch = icl_tc_phy_aux_ch(dev_priv, power_well);
479 struct intel_digital_port *dig_port = NULL;
480 struct intel_encoder *encoder;
481
482 /* Bypass the check if all references are released asynchronously */
483 if (power_well_async_ref_count(dev_priv, power_well) ==
484 power_well->count)
485 return;
486
487 aux_ch = icl_tc_phy_aux_ch(dev_priv, power_well);
488
489 for_each_intel_encoder(&dev_priv->drm, encoder) {
> 490 enum phy phy = intel_port_to_phy(encoder->port);
491
492 if (!intel_phy_is_tc(dev_priv, phy))
493 continue;
494
495 /* We'll check the MST primary port */
496 if (encoder->type == INTEL_OUTPUT_DP_MST)
497 continue;
498
499 dig_port = enc_to_dig_port(&encoder->base);
500 if (WARN_ON(!dig_port))
501 continue;
502
503 if (dig_port->aux_ch != aux_ch) {
504 dig_port = NULL;
505 continue;
506 }
507
508 break;
509 }
510
511 if (WARN_ON(!dig_port))
512 return;
513
514 WARN_ON(!intel_tc_port_ref_held(dig_port));
515 }
516
---
0-DAY kernel test infrastructure Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all Intel Corporation
[-- Attachment #2: .config.gz --]
[-- Type: application/gzip, Size: 68695 bytes --]
[-- Attachment #3: Type: text/plain, Size: 159 bytes --]
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 33+ messages in thread
* ✓ Fi.CI.IGT: success for EHL port programming (rev6)
2019-07-03 23:37 [PATCH v4 0/5] EHL port programming Matt Roper
` (11 preceding siblings ...)
2019-07-04 2:16 ` ✓ Fi.CI.BAT: success " Patchwork
@ 2019-07-05 6:44 ` Patchwork
12 siblings, 0 replies; 33+ messages in thread
From: Patchwork @ 2019-07-05 6:44 UTC (permalink / raw)
To: Matt Roper; +Cc: intel-gfx
== Series Details ==
Series: EHL port programming (rev6)
URL : https://patchwork.freedesktop.org/series/62492/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6406_full -> Patchwork_13522_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Known issues
------------
Here are the changes found in Patchwork_13522_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_busy@close-race:
- shard-skl: [PASS][1] -> [DMESG-FAIL][2] ([fdo#111063])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6406/shard-skl9/igt@gem_busy@close-race.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13522/shard-skl9/igt@gem_busy@close-race.html
* igt@gem_eio@reset-stress:
- shard-snb: [PASS][3] -> [FAIL][4] ([fdo#109661])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6406/shard-snb5/igt@gem_eio@reset-stress.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13522/shard-snb2/igt@gem_eio@reset-stress.html
* igt@gem_tiled_swapping@non-threaded:
- shard-apl: [PASS][5] -> [DMESG-WARN][6] ([fdo#108686])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6406/shard-apl5/igt@gem_tiled_swapping@non-threaded.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13522/shard-apl3/igt@gem_tiled_swapping@non-threaded.html
* igt@gem_workarounds@suspend-resume:
- shard-apl: [PASS][7] -> [DMESG-WARN][8] ([fdo#108566]) +1 similar issue
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6406/shard-apl1/igt@gem_workarounds@suspend-resume.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13522/shard-apl7/igt@gem_workarounds@suspend-resume.html
* igt@kms_cursor_crc@pipe-b-cursor-suspend:
- shard-skl: [PASS][9] -> [INCOMPLETE][10] ([fdo#110741])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6406/shard-skl1/igt@kms_cursor_crc@pipe-b-cursor-suspend.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13522/shard-skl8/igt@kms_cursor_crc@pipe-b-cursor-suspend.html
* igt@kms_frontbuffer_tracking@fbc-rgb565-draw-pwrite:
- shard-iclb: [PASS][11] -> [FAIL][12] ([fdo#103167]) +3 similar issues
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6406/shard-iclb8/igt@kms_frontbuffer_tracking@fbc-rgb565-draw-pwrite.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13522/shard-iclb3/igt@kms_frontbuffer_tracking@fbc-rgb565-draw-pwrite.html
* igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
- shard-skl: [PASS][13] -> [FAIL][14] ([fdo#108145] / [fdo#110403])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6406/shard-skl9/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13522/shard-skl9/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
* igt@kms_psr@psr2_sprite_plane_move:
- shard-iclb: [PASS][15] -> [SKIP][16] ([fdo#109441]) +3 similar issues
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6406/shard-iclb2/igt@kms_psr@psr2_sprite_plane_move.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13522/shard-iclb3/igt@kms_psr@psr2_sprite_plane_move.html
#### Possible fixes ####
* igt@gem_busy@close-race:
- shard-snb: [INCOMPLETE][17] ([fdo#105411]) -> [PASS][18]
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6406/shard-snb1/igt@gem_busy@close-race.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13522/shard-snb5/igt@gem_busy@close-race.html
- shard-hsw: [DMESG-FAIL][19] ([fdo#111063]) -> [PASS][20]
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6406/shard-hsw2/igt@gem_busy@close-race.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13522/shard-hsw1/igt@gem_busy@close-race.html
* igt@gem_exec_balancer@smoke:
- shard-iclb: [SKIP][21] ([fdo#110854]) -> [PASS][22]
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6406/shard-iclb8/igt@gem_exec_balancer@smoke.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13522/shard-iclb2/igt@gem_exec_balancer@smoke.html
* igt@i915_suspend@sysfs-reader:
- shard-apl: [DMESG-WARN][23] ([fdo#108566]) -> [PASS][24] +4 similar issues
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6406/shard-apl5/igt@i915_suspend@sysfs-reader.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13522/shard-apl4/igt@i915_suspend@sysfs-reader.html
* igt@kms_cursor_legacy@2x-long-cursor-vs-flip-atomic:
- shard-hsw: [FAIL][25] ([fdo#105767]) -> [PASS][26]
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6406/shard-hsw4/igt@kms_cursor_legacy@2x-long-cursor-vs-flip-atomic.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13522/shard-hsw7/igt@kms_cursor_legacy@2x-long-cursor-vs-flip-atomic.html
* igt@kms_frontbuffer_tracking@fbc-tilingchange:
- shard-iclb: [FAIL][27] ([fdo#103167]) -> [PASS][28] +3 similar issues
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6406/shard-iclb7/igt@kms_frontbuffer_tracking@fbc-tilingchange.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13522/shard-iclb4/igt@kms_frontbuffer_tracking@fbc-tilingchange.html
- shard-skl: [FAIL][29] ([fdo#108040]) -> [PASS][30]
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6406/shard-skl1/igt@kms_frontbuffer_tracking@fbc-tilingchange.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13522/shard-skl3/igt@kms_frontbuffer_tracking@fbc-tilingchange.html
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-indfb-draw-mmap-gtt:
- shard-skl: [FAIL][31] ([fdo#103167]) -> [PASS][32]
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6406/shard-skl1/igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-indfb-draw-mmap-gtt.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13522/shard-skl3/igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-indfb-draw-mmap-gtt.html
* igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min:
- shard-skl: [FAIL][33] ([fdo#108145]) -> [PASS][34] +1 similar issue
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6406/shard-skl8/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13522/shard-skl3/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min.html
* igt@kms_psr@no_drrs:
- shard-iclb: [FAIL][35] ([fdo#108341]) -> [PASS][36]
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6406/shard-iclb1/igt@kms_psr@no_drrs.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13522/shard-iclb8/igt@kms_psr@no_drrs.html
* igt@kms_psr@psr2_cursor_render:
- shard-iclb: [SKIP][37] ([fdo#109441]) -> [PASS][38]
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6406/shard-iclb8/igt@kms_psr@psr2_cursor_render.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13522/shard-iclb2/igt@kms_psr@psr2_cursor_render.html
* igt@kms_setmode@basic:
- shard-skl: [FAIL][39] ([fdo#99912]) -> [PASS][40]
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6406/shard-skl1/igt@kms_setmode@basic.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13522/shard-skl3/igt@kms_setmode@basic.html
* igt@perf@blocking:
- shard-skl: [FAIL][41] ([fdo#110728]) -> [PASS][42]
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6406/shard-skl9/igt@perf@blocking.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13522/shard-skl10/igt@perf@blocking.html
* igt@tools_test@tools_test:
- shard-snb: [SKIP][43] ([fdo#109271]) -> [PASS][44]
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6406/shard-snb1/igt@tools_test@tools_test.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13522/shard-snb4/igt@tools_test@tools_test.html
#### Warnings ####
* igt@kms_dp_dsc@basic-dsc-enable-edp:
- shard-iclb: [DMESG-WARN][45] ([fdo#107724]) -> [SKIP][46] ([fdo#109349])
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6406/shard-iclb2/igt@kms_dp_dsc@basic-dsc-enable-edp.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13522/shard-iclb3/igt@kms_dp_dsc@basic-dsc-enable-edp.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-shrfb-draw-blt:
- shard-skl: [FAIL][47] ([fdo#108040]) -> [FAIL][48] ([fdo#103167])
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6406/shard-skl3/igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-shrfb-draw-blt.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13522/shard-skl10/igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-shrfb-draw-blt.html
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#105411]: https://bugs.freedesktop.org/show_bug.cgi?id=105411
[fdo#105767]: https://bugs.freedesktop.org/show_bug.cgi?id=105767
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#108040]: https://bugs.freedesktop.org/show_bug.cgi?id=108040
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#108341]: https://bugs.freedesktop.org/show_bug.cgi?id=108341
[fdo#108566]: https://bugs.freedesktop.org/show_bug.cgi?id=108566
[fdo#108686]: https://bugs.freedesktop.org/show_bug.cgi?id=108686
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109349]: https://bugs.freedesktop.org/show_bug.cgi?id=109349
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#109661]: https://bugs.freedesktop.org/show_bug.cgi?id=109661
[fdo#110403]: https://bugs.freedesktop.org/show_bug.cgi?id=110403
[fdo#110728]: https://bugs.freedesktop.org/show_bug.cgi?id=110728
[fdo#110741]: https://bugs.freedesktop.org/show_bug.cgi?id=110741
[fdo#110854]: https://bugs.freedesktop.org/show_bug.cgi?id=110854
[fdo#111063]: https://bugs.freedesktop.org/show_bug.cgi?id=111063
[fdo#99912]: https://bugs.freedesktop.org/show_bug.cgi?id=99912
Participating hosts (10 -> 10)
------------------------------
No changes in participating hosts
Build changes
-------------
* Linux: CI_DRM_6406 -> Patchwork_13522
CI_DRM_6406: 3d4498e9178aebf6a0bf04ebbc0a91e7e4f893e3 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5082: f7c51e6fbf8da0784b64a1edaee5266aa9b9f829 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_13522: 09dfa89966180f9128632a77732e5a725139d5f7 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13522/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: [PATCH v4 1/5] drm/i915/gen11: Start distinguishing 'phy' from 'port'
2019-07-04 15:55 ` Lucas De Marchi
@ 2019-07-05 10:33 ` Ville Syrjälä
2019-07-08 14:02 ` Lucas De Marchi
0 siblings, 1 reply; 33+ messages in thread
From: Ville Syrjälä @ 2019-07-05 10:33 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: Jani Nikula, intel-gfx
On Thu, Jul 04, 2019 at 08:55:51AM -0700, Lucas De Marchi wrote:
> On Thu, Jul 04, 2019 at 06:09:04PM +0300, Ville Syrjälä wrote:
> >On Thu, Jul 04, 2019 at 07:54:26AM -0700, Lucas De Marchi wrote:
> >> On Thu, Jul 04, 2019 at 12:18:11PM +0300, Ville Syrjälä wrote:
> >> >On Wed, Jul 03, 2019 at 04:37:32PM -0700, Matt Roper wrote:
> >> >> Our past DDI-based Intel platforms have had a fixed DDI<->PHY mapping.
> >> >> Because of this, both the bspec documentation and our i915 code has used
> >> >> the term "port" when talking about either DDI's or PHY's; it was always
> >> >> easy to tell what terms like "Port A" were referring to from the
> >> >> context.
> >> >>
> >> >> Unfortunately this is starting to break down now that EHL allows PHY-A
> >> >> to be driven by either DDI-A or DDI-D. Is a setup with DDI-D driving
> >> >> PHY-A considered "Port A" or "Port D?" The answer depends on which
> >> >> register we're working with, and even the bspec doesn't do a great job
> >> >> of clarifying this.
> >> >>
> >> >> Let's try to be more explicit about whether we're talking about the DDI
> >> >> or the PHY on gen11+ by using 'port' to refer to the DDI and creating a
> >> >> new 'enum phy' namespace to refer to the PHY in use.
> >> >>
> >> >> This patch just adds the new PHY namespace, new phy-based versions of
> >> >> intel_port_is_*(), and a helper to convert a port to a PHY.
> >> >> Transitioning various areas of the code over to using the PHY namespace
> >> >> will be done in subsequent patches to make review easier. We'll remove
> >> >> the intel_port_is_*() functions at the end of the series when we
> >> >> transition all callers over to using the PHY-based versions.
> >> >>
> >> >> v2:
> >> >> - Convert a few more 'port' uses to 'phy.' (Sparse)
> >> >>
> >> >> v3:
> >> >> - Switch DDI_CLK_SEL() back to 'port.' (Jose)
> >> >> - Add a code comment clarifying why DPCLKA_CFGCR0_ICL needs to use PHY
> >> >> for its bit definitions, even though the register description is
> >> >> given in terms of DDI.
> >> >> - To avoid confusion, switch CNL's DPCLKA_CFGCR0 defines back to using
> >> >> port and create separate ICL+ definitions that work in terms of PHY.
> >> >>
> >> >> v4:
> >> >> - Rebase and resolve conflicts with Imre's TC series.
> >> >> - This patch now just adds the namespace and a few convenience
> >> >> functions; the important changes are now split out into separate
> >> >> patches to make review easier.
> >> >>
> >> >> Suggested-by: Ville Syrjala <ville.syrjala@linux.intel.com>
> >> >> Cc: José Roberto de Souza <jose.souza@intel.com>
> >> >> Cc: Lucas De Marchi <lucas.demarchi@intel.com>
> >> >> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >> >> Cc: Imre Deak <imre.deak@intel.com>
> >> >> Cc: Jani Nikula <jani.nikula@intel.com>
> >> >> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> >> >> ---
> >> >> drivers/gpu/drm/i915/display/intel_display.c | 32 +++++++++++++++++++-
> >> >> drivers/gpu/drm/i915/display/intel_display.h | 16 ++++++++++
> >> >> drivers/gpu/drm/i915/intel_drv.h | 2 ++
> >> >> 3 files changed, 49 insertions(+), 1 deletion(-)
> >> >>
> >> >> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> >> >> index 919f5ac844c8..4a85abef93e7 100644
> >> >> --- a/drivers/gpu/drm/i915/display/intel_display.c
> >> >> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> >> >> @@ -6663,6 +6663,20 @@ bool intel_port_is_combophy(struct drm_i915_private *dev_priv, enum port port)
> >> >> return false;
> >> >> }
> >> >>
> >> >> +bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy phy)
> >> >> +{
> >> >> + if (phy == PHY_NONE)
> >> >> + return false;
> >> >> +
> >> >> + if (IS_ELKHARTLAKE(dev_priv))
> >> >> + return phy <= PHY_C;
> >> >> +
> >> >> + if (INTEL_GEN(dev_priv) >= 11)
> >> >> + return phy <= PHY_B;
> >> >> +
> >> >> + return false;
> >> >> +}
> >> >> +
> >> >> bool intel_port_is_tc(struct drm_i915_private *dev_priv, enum port port)
> >> >> {
> >> >> if (INTEL_GEN(dev_priv) >= 11 && !IS_ELKHARTLAKE(dev_priv))
> >> >> @@ -6671,9 +6685,25 @@ bool intel_port_is_tc(struct drm_i915_private *dev_priv, enum port port)
> >> >> return false;
> >> >> }
> >> >>
> >> >> +bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy)
> >> >> +{
> >> >> + if (INTEL_GEN(dev_priv) >= 11 && !IS_ELKHARTLAKE(dev_priv))
> >> >> + return phy >= PHY_C && phy <= PHY_F;
> >> >> +
> >> >> + return false;
> >> >> +}
> >> >> +
> >> >> +enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port)
> >> >> +{
> >> >> + if (IS_ELKHARTLAKE(i915) && port == PORT_D)
> >> >> + return PHY_A;
> >> >> +
> >> >> + return (enum phy)port;
> >> >> +}
> >> >> +
> >> >> enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv, enum port port)
> >> >> {
> >> >> - if (!intel_port_is_tc(dev_priv, port))
> >> >> + if (!intel_phy_is_tc(dev_priv, intel_port_to_phy(dev_priv, port)))
> >> >> return PORT_TC_NONE;
> >> >>
> >> >> return port - PORT_C;
> >> >> diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
> >> >> index d296556ed82e..d53285fb883f 100644
> >> >> --- a/drivers/gpu/drm/i915/display/intel_display.h
> >> >> +++ b/drivers/gpu/drm/i915/display/intel_display.h
> >> >> @@ -228,6 +228,21 @@ struct intel_link_m_n {
> >> >> u32 link_n;
> >> >> };
> >> >>
> >> >> +enum phy {
> >> >> + PHY_NONE = -1,
> >> >> +
> >> >> + PHY_A = 0,
> >> >> + PHY_B,
> >> >> + PHY_C,
> >> >> + PHY_D,
> >> >> + PHY_E,
> >> >> + PHY_F,
> >> >> +
> >> >> + I915_MAX_PHYS
> >> >> +};
> >> >
> >> >I was pondering if we could eventually do something like:
> >> >
> >> >enum phy {
> >> > PHY_COMBO_A = 0,
> >> > PHY_COMBO_B,
> >> > ...
> >> >
> >> > PHY_TC_1,
> >> > PHY_TC_2,
> >> > ...
> >> >};
> >> >
> >> >and probably also add encoder->phy so we can contain
> >> >that port<->phy mapping logic in the encoder init.
> >> >I think that should work more or less fine since I
> >> >don't think PHY_TC_1 needs to have any specific value.
> >>
> >> that's not true. All TC registers are based off the TC phy number.
> >
> >That's just a trivial (x)-TC1, so I stand by what I said.
>
> EHL and TGL have 3 combo phys. ICL has 2. So TC1 would have to be a
> different value for ICL and the others for this to work.
It would just be an arbitrary number (eg. 8).
> I think we should treat the index as just a number we use to compute the
> right base for the registers in that hw IP.
>
> >
> >> Hence all the conversion we do port_to_tc()... I'd like to remove that
> >> in future and just stuff the phy index in intel_digital_port, as we
> >> already do for other tc_phy_* fields (we could add a union there so each
> >> phy adds its own fields).
> >>
> >> And I'd rather not do the single phy namespace - it doesn't
> >> play well with TGL and the combo/tc.
> >
> >I think it would work just fine for that. A single namespace would allow
> >us to remove all the crazy port->PHY type mapping we have going on
> >currently. Probably the best alternative would be separate namespaces
> >for each type with a new enum to identify the type.
>
> My proposal is in the lines of that alternative approach. Save the phy
> type and the phy index in intel_digital_port. And allow each phy to store
> its fields there. Something along:
>
> struct intel_digital_port {
> ...
> struct {
> enum phy_type type;
> u8 idx;
> union {
> struct {
> struct mutex lock; /* protects the TypeC port mode */
> intel_wakeref_t lock_wakeref;
> int link_refcount;
> char tc_port_name[8];
> enum tc_port_mode tc_mode;
> bool legacy_port;
> u8 fia;
> } tc;
> struct {
> ...
> } combo;
> struct {
> ...
> } dpio??;
> };
> } phy;
> };
>
> >From a quick look I don't think the idx is relevant enough to have its
> own enum, but I wouldn't mind.
>
> then no more port->phy everywhere as we have right now and we only
> assign idx to the right value during init. The TC rework we had recently
> makes it nice and I'm starting to do it, but I'd rather merge the TGL
> patches before. For Modular FIA I'm already stashing the fia index
> there (since I had to redo the support due to the TC rework),
> but without the additional struct.
> See https://patchwork.freedesktop.org/series/63175/
>
> Lucas De Marchi
>
> >
> >>
> >> Lucas De Marchi
> >>
> >> >
> >> >Unfortunaltey I don't have a great idea how to do the
> >> >same for the DDIs since there the number of combo DDIs
> >> >changes but we still need the PORT_TC1 (assuming we had
> >> >one) to be DDI_<last combo DDI> + 1. One random silly
> >> >idea was to decouple the enum port from the register
> >> >definitions by having just some kind of
> >> >encoder->port_index for those. But that doesn't feel
> >> >entirely great either.
> >> >
> >> >Anyways, something to think about in the future perhaps.
> >> >
> >> >Patch is
> >> >Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >> >
> >> >> +
> >> >> +#define phy_name(a) ((a) + 'A')
> >> >> +
> >> >> #define for_each_pipe(__dev_priv, __p) \
> >> >> for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++)
> >> >>
> >> >> @@ -356,5 +371,6 @@ void lpt_disable_clkout_dp(struct drm_i915_private *dev_priv);
> >> >> u32 intel_plane_fb_max_stride(struct drm_i915_private *dev_priv,
> >> >> u32 pixel_format, u64 modifier);
> >> >> bool intel_plane_can_remap(const struct intel_plane_state *plane_state);
> >> >> +enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port);
> >> >>
> >> >> #endif
> >> >> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> >> >> index 24c63ed45c6f..815c26c0b98c 100644
> >> >> --- a/drivers/gpu/drm/i915/intel_drv.h
> >> >> +++ b/drivers/gpu/drm/i915/intel_drv.h
> >> >> @@ -1493,7 +1493,9 @@ void intel_encoder_destroy(struct drm_encoder *encoder);
> >> >> struct drm_display_mode *
> >> >> intel_encoder_current_mode(struct intel_encoder *encoder);
> >> >> bool intel_port_is_combophy(struct drm_i915_private *dev_priv, enum port port);
> >> >> +bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy phy);
> >> >> bool intel_port_is_tc(struct drm_i915_private *dev_priv, enum port port);
> >> >> +bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy);
> >> >> enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv,
> >> >> enum port port);
> >> >> int intel_get_pipe_from_crtc_id_ioctl(struct drm_device *dev, void *data,
> >> >> --
> >> >> 2.17.2
> >> >
> >> >--
> >> >Ville Syrjälä
> >> >Intel
> >
> >--
> >Ville Syrjälä
> >Intel
--
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: [PATCH v5 4/5] drm/i915: Transition port type checks to phy checks
2019-07-04 0:02 ` [PATCH v5 " Matt Roper
@ 2019-07-08 13:13 ` Ville Syrjälä
0 siblings, 0 replies; 33+ messages in thread
From: Ville Syrjälä @ 2019-07-08 13:13 UTC (permalink / raw)
To: Matt Roper; +Cc: intel-gfx, Lucas De Marchi
On Wed, Jul 03, 2019 at 05:02:11PM -0700, Matt Roper wrote:
> Transition the remaining uses of intel_port_is_* over to the equivalent
> intel_phy_is_* functions and drop the port functions.
>
> v5: Fix a call in a debug function that's only called when
> CONFIG_DRM_I915_DEBUG_RUNTIME_PM is on. (CI)
>
> Cc: José Roberto de Souza <jose.souza@intel.com>
> Cc: Lucas De Marchi <lucas.demarchi@intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> To avoid conflicts with in-flight TGL patches, we may want to hold off
> on merging this one until TGL lands?
>
> drivers/gpu/drm/i915/display/intel_bios.c | 4 +-
> drivers/gpu/drm/i915/display/intel_ddi.c | 49 ++++++++++++-------
> drivers/gpu/drm/i915/display/intel_display.c | 38 ++++----------
> .../drm/i915/display/intel_display_power.c | 4 +-
> drivers/gpu/drm/i915/display/intel_dp.c | 15 +++---
> drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 11 +++--
> drivers/gpu/drm/i915/intel_drv.h | 2 -
> 7 files changed, 61 insertions(+), 62 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c
> index 0c9808132d67..4fdbb5c35d87 100644
> --- a/drivers/gpu/drm/i915/display/intel_bios.c
> +++ b/drivers/gpu/drm/i915/display/intel_bios.c
> @@ -28,6 +28,7 @@
> #include <drm/drm_dp_helper.h>
> #include <drm/i915_drm.h>
>
> +#include "display/intel_display.h"
> #include "display/intel_gmbus.h"
>
> #include "i915_drv.h"
> @@ -1733,12 +1734,13 @@ init_vbt_missing_defaults(struct drm_i915_private *dev_priv)
> for (port = PORT_A; port < I915_MAX_PORTS; port++) {
> struct ddi_vbt_port_info *info =
> &dev_priv->vbt.ddi_port_info[port];
> + enum phy phy = intel_port_to_phy(dev_priv, port);
>
> /*
> * VBT has the TypeC mode (native,TBT/USB) and we don't want
> * to detect it.
> */
> - if (intel_port_is_tc(dev_priv, port))
> + if (intel_phy_is_tc(dev_priv, phy))
> continue;
>
> info->supports_dvi = (port != PORT_A && port != PORT_E);
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 50dd9d731456..37c8cecb9a6a 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -868,11 +868,12 @@ icl_get_combo_buf_trans(struct drm_i915_private *dev_priv, int type, int rate,
> static int intel_ddi_hdmi_level(struct drm_i915_private *dev_priv, enum port port)
> {
> int n_entries, level, default_entry;
> + enum phy phy = intel_port_to_phy(dev_priv, port);
>
> level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift;
>
> if (INTEL_GEN(dev_priv) >= 11) {
> - if (intel_port_is_combophy(dev_priv, port))
> + if (intel_phy_is_combo(dev_priv, phy))
> icl_get_combo_buf_trans(dev_priv, INTEL_OUTPUT_HDMI,
> 0, &n_entries);
> else
> @@ -1487,9 +1488,10 @@ static void icl_ddi_clock_get(struct intel_encoder *encoder,
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> struct intel_dpll_hw_state *pll_state = &pipe_config->dpll_hw_state;
> enum port port = encoder->port;
> + enum phy phy = intel_port_to_phy(dev_priv, port);
> int link_clock;
>
> - if (intel_port_is_combophy(dev_priv, port)) {
> + if (intel_phy_is_combo(dev_priv, phy)) {
> link_clock = cnl_calc_wrpll_link(dev_priv, pll_state);
> } else {
> enum intel_dpll_id pll_id = intel_get_shared_dpll_id(dev_priv,
> @@ -2086,6 +2088,7 @@ static void intel_ddi_get_power_domains(struct intel_encoder *encoder,
> {
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> struct intel_digital_port *dig_port;
> + enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
>
> /*
> * TODO: Add support for MST encoders. Atm, the following should never
> @@ -2103,7 +2106,7 @@ static void intel_ddi_get_power_domains(struct intel_encoder *encoder,
> * ports.
> */
> if (intel_crtc_has_dp_encoder(crtc_state) ||
> - intel_port_is_tc(dev_priv, encoder->port))
> + intel_phy_is_tc(dev_priv, phy))
> intel_display_power_get(dev_priv,
> intel_ddi_main_link_aux_domain(dig_port));
>
> @@ -2228,10 +2231,11 @@ u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder)
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
> enum port port = encoder->port;
> + enum phy phy = intel_port_to_phy(dev_priv, port);
> int n_entries;
>
> if (INTEL_GEN(dev_priv) >= 11) {
> - if (intel_port_is_combophy(dev_priv, port))
> + if (intel_phy_is_combo(dev_priv, phy))
> icl_get_combo_buf_trans(dev_priv, encoder->type,
> intel_dp->link_rate, &n_entries);
> else
> @@ -2664,9 +2668,9 @@ static void icl_ddi_vswing_sequence(struct intel_encoder *encoder,
> enum intel_output_type type)
> {
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> - enum port port = encoder->port;
> + enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
>
> - if (intel_port_is_combophy(dev_priv, port))
> + if (intel_phy_is_combo(dev_priv, phy))
> icl_combo_phy_ddi_vswing_sequence(encoder, level, type);
> else
> icl_mg_phy_ddi_vswing_sequence(encoder, link_clock, level);
> @@ -2729,12 +2733,13 @@ u32 ddi_signal_levels(struct intel_dp *intel_dp)
>
> static inline
> u32 icl_dpclka_cfgcr0_clk_off(struct drm_i915_private *dev_priv,
> - enum port port)
> + enum phy phy)
> {
> - if (intel_port_is_combophy(dev_priv, port)) {
> - return ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(port);
> - } else if (intel_port_is_tc(dev_priv, port)) {
> - enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
> + if (intel_phy_is_combo(dev_priv, phy)) {
> + return ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
> + } else if (intel_phy_is_tc(dev_priv, phy)) {
> + enum tc_port tc_port = intel_port_to_tc(dev_priv,
> + (enum port)phy);
>
> return ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port);
> }
> @@ -2876,6 +2881,7 @@ static void intel_ddi_clk_select(struct intel_encoder *encoder,
> {
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> enum port port = encoder->port;
> + enum phy phy = intel_port_to_phy(dev_priv, port);
> u32 val;
> const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
>
> @@ -2885,7 +2891,7 @@ static void intel_ddi_clk_select(struct intel_encoder *encoder,
> mutex_lock(&dev_priv->dpll_lock);
>
> if (INTEL_GEN(dev_priv) >= 11) {
> - if (!intel_port_is_combophy(dev_priv, port))
> + if (!intel_phy_is_combo(dev_priv, phy))
> I915_WRITE(DDI_CLK_SEL(port),
> icl_pll_to_ddi_clk_sel(encoder, crtc_state));
> } else if (IS_CANNONLAKE(dev_priv)) {
> @@ -2925,9 +2931,10 @@ static void intel_ddi_clk_disable(struct intel_encoder *encoder)
> {
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> enum port port = encoder->port;
> + enum phy phy = intel_port_to_phy(dev_priv, port);
>
> if (INTEL_GEN(dev_priv) >= 11) {
> - if (!intel_port_is_combophy(dev_priv, port))
> + if (!intel_phy_is_combo(dev_priv, phy))
> I915_WRITE(DDI_CLK_SEL(port), DDI_CLK_SEL_NONE);
> } else if (IS_CANNONLAKE(dev_priv)) {
> I915_WRITE(DPCLKA_CFGCR0, I915_READ(DPCLKA_CFGCR0) |
> @@ -3134,7 +3141,7 @@ static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder,
>
> intel_ddi_clk_select(encoder, crtc_state);
>
> - if (!intel_port_is_tc(dev_priv, port) ||
> + if (!intel_phy_is_tc(dev_priv, phy) ||
> dig_port->tc_mode != TC_PORT_TBT_ALT)
> intel_display_power_get(dev_priv,
> dig_port->ddi_io_power_domain);
> @@ -3152,7 +3159,7 @@ static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder,
> else
> intel_prepare_dp_ddi_buffers(encoder, crtc_state);
>
> - if (intel_port_is_combophy(dev_priv, port)) {
> + if (intel_phy_is_combo(dev_priv, phy)) {
> bool lane_reversal =
> dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL;
>
> @@ -3304,6 +3311,7 @@ static void intel_ddi_post_disable_dp(struct intel_encoder *encoder,
> struct intel_dp *intel_dp = &dig_port->dp;
> bool is_mst = intel_crtc_has_type(old_crtc_state,
> INTEL_OUTPUT_DP_MST);
> + enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
>
> if (!is_mst) {
> intel_ddi_disable_pipe_clock(old_crtc_state);
> @@ -3319,7 +3327,7 @@ static void intel_ddi_post_disable_dp(struct intel_encoder *encoder,
> intel_edp_panel_vdd_on(intel_dp);
> intel_edp_panel_off(intel_dp);
>
> - if (!intel_port_is_tc(dev_priv, encoder->port) ||
> + if (!intel_phy_is_tc(dev_priv, phy) ||
> dig_port->tc_mode != TC_PORT_TBT_ALT)
> intel_display_power_put_unchecked(dev_priv,
> dig_port->ddi_io_power_domain);
> @@ -3669,8 +3677,9 @@ intel_ddi_pre_pll_enable(struct intel_encoder *encoder,
> {
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
> - bool is_tc_port = intel_port_is_tc(dev_priv, encoder->port);
> enum port port = encoder->port;
> + enum phy phy = intel_port_to_phy(dev_priv, port);
> + bool is_tc_port = intel_phy_is_tc(dev_priv, phy);
>
> if (is_tc_port)
> intel_tc_port_get_link(dig_port, crtc_state->lane_count);
> @@ -3700,7 +3709,8 @@ intel_ddi_post_pll_disable(struct intel_encoder *encoder,
> {
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
> - bool is_tc_port = intel_port_is_tc(dev_priv, encoder->port);
> + enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
> + bool is_tc_port = intel_phy_is_tc(dev_priv, phy);
>
> if (intel_crtc_has_dp_encoder(crtc_state) || is_tc_port)
> intel_display_power_put_unchecked(dev_priv,
> @@ -4214,6 +4224,7 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
> struct drm_encoder *encoder;
> bool init_hdmi, init_dp, init_lspcon = false;
> enum pipe pipe;
> + enum phy phy = intel_port_to_phy(dev_priv, port);
>
> init_hdmi = port_info->supports_dvi || port_info->supports_hdmi;
> init_dp = port_info->supports_dp;
> @@ -4277,7 +4288,7 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
> intel_dig_port->max_lanes = intel_ddi_max_lanes(intel_dig_port);
> intel_dig_port->aux_ch = intel_bios_port_aux_ch(dev_priv, port);
>
> - if (intel_port_is_tc(dev_priv, port)) {
> + if (intel_phy_is_tc(dev_priv, phy)) {
> bool is_legacy = !port_info->supports_typec_usb &&
> !port_info->supports_tbt;
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 4a85abef93e7..550530cc2d24 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -6649,20 +6649,6 @@ static void i9xx_pfit_enable(const struct intel_crtc_state *crtc_state)
> I915_WRITE(BCLRPAT(crtc->pipe), 0);
> }
>
> -bool intel_port_is_combophy(struct drm_i915_private *dev_priv, enum port port)
> -{
> - if (port == PORT_NONE)
> - return false;
> -
> - if (IS_ELKHARTLAKE(dev_priv))
> - return port <= PORT_C;
> -
> - if (INTEL_GEN(dev_priv) >= 11)
> - return port <= PORT_B;
> -
> - return false;
> -}
> -
> bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy phy)
> {
> if (phy == PHY_NONE)
> @@ -6677,14 +6663,6 @@ bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy phy)
> return false;
> }
>
> -bool intel_port_is_tc(struct drm_i915_private *dev_priv, enum port port)
> -{
> - if (INTEL_GEN(dev_priv) >= 11 && !IS_ELKHARTLAKE(dev_priv))
> - return port >= PORT_C && port <= PORT_F;
> -
> - return false;
> -}
> -
> bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy)
> {
> if (INTEL_GEN(dev_priv) >= 11 && !IS_ELKHARTLAKE(dev_priv))
> @@ -6734,8 +6712,9 @@ enum intel_display_power_domain
> intel_aux_power_domain(struct intel_digital_port *dig_port)
> {
> struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
> + enum phy phy = intel_port_to_phy(dev_priv, dig_port->base.port);
>
> - if (intel_port_is_tc(dev_priv, dig_port->base.port) &&
> + if (intel_phy_is_tc(dev_priv, phy) &&
> dig_port->tc_mode == TC_PORT_TBT_ALT) {
> switch (dig_port->aux_ch) {
> case AUX_CH_C:
> @@ -10069,16 +10048,17 @@ static void icelake_get_ddi_pll(struct drm_i915_private *dev_priv,
> enum port port,
> struct intel_crtc_state *pipe_config)
> {
> + enum phy phy = intel_port_to_phy(dev_priv, port);
> enum icl_port_dpll_id port_dpll_id;
> enum intel_dpll_id id;
> u32 temp;
>
> - if (intel_port_is_combophy(dev_priv, port)) {
> + if (intel_phy_is_combo(dev_priv, phy)) {
> temp = I915_READ(DPCLKA_CFGCR0_ICL) &
> - DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
> - id = temp >> DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port);
> + ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
> + id = temp >> ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy);
> port_dpll_id = ICL_PORT_DPLL_DEFAULT;
> - } else if (intel_port_is_tc(dev_priv, port)) {
> + } else if (intel_phy_is_tc(dev_priv, phy)) {
> u32 clk_sel = I915_READ(DDI_CLK_SEL(port)) & DDI_CLK_SEL_MASK;
>
> if (clk_sel == DDI_CLK_SEL_MG) {
> @@ -16935,9 +16915,11 @@ intel_modeset_setup_hw_state(struct drm_device *dev,
>
> /* Sanitize the TypeC port mode upfront, encoders depend on this */
> for_each_intel_encoder(dev, encoder) {
> + enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
> +
> /* We need to sanitize only the MST primary port. */
> if (encoder->type != INTEL_OUTPUT_DP_MST &&
> - intel_port_is_tc(dev_priv, encoder->port))
> + intel_phy_is_tc(dev_priv, phy))
> intel_tc_port_sanitize(enc_to_dig_port(&encoder->base));
> }
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
> index 64627c117c31..8aabfea76d38 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> @@ -487,7 +487,9 @@ static void icl_tc_port_assert_ref_held(struct drm_i915_private *dev_priv,
> aux_ch = icl_tc_phy_aux_ch(dev_priv, power_well);
>
> for_each_intel_encoder(&dev_priv->drm, encoder) {
> - if (!intel_port_is_tc(dev_priv, encoder->port))
> + enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
> +
> + if (!intel_phy_is_tc(dev_priv, phy))
> continue;
>
> /* We'll check the MST primary port */
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index 8f7188d71d08..67603a247e8a 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -297,9 +297,9 @@ static int icl_max_source_rate(struct intel_dp *intel_dp)
> {
> struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
> struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
> - enum port port = dig_port->base.port;
> + enum phy phy = intel_port_to_phy(dev_priv, dig_port->base.port);
>
> - if (intel_port_is_combophy(dev_priv, port) &&
> + if (intel_phy_is_combo(dev_priv, phy) &&
> !IS_ELKHARTLAKE(dev_priv) &&
> !intel_dp_is_edp(intel_dp))
> return 540000;
> @@ -1192,7 +1192,8 @@ intel_dp_aux_xfer(struct intel_dp *intel_dp,
> struct drm_i915_private *i915 =
> to_i915(intel_dig_port->base.base.dev);
> struct intel_uncore *uncore = &i915->uncore;
> - bool is_tc_port = intel_port_is_tc(i915, intel_dig_port->base.port);
> + enum phy phy = intel_port_to_phy(i915, intel_dig_port->base.port);
> + bool is_tc_port = intel_phy_is_tc(i915, phy);
> i915_reg_t ch_ctl, ch_data[5];
> u32 aux_clock_divider;
> enum intel_display_power_domain aux_domain =
> @@ -5211,10 +5212,11 @@ static bool icl_digital_port_connected(struct intel_encoder *encoder)
> {
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
> + enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
>
> - if (intel_port_is_combophy(dev_priv, encoder->port))
> + if (intel_phy_is_combo(dev_priv, phy))
> return icl_combo_port_connected(dev_priv, dig_port);
> - else if (intel_port_is_tc(dev_priv, encoder->port))
> + else if (intel_phy_is_tc(dev_priv, phy))
> return intel_tc_port_connected(dig_port);
> else
> MISSING_CASE(encoder->hpd_pin);
> @@ -7118,6 +7120,7 @@ intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
> struct drm_device *dev = intel_encoder->base.dev;
> struct drm_i915_private *dev_priv = to_i915(dev);
> enum port port = intel_encoder->port;
> + enum phy phy = intel_port_to_phy(dev_priv, port);
> int type;
>
> /* Initialize the work for modeset in case of link train failure */
> @@ -7144,7 +7147,7 @@ intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
> * Currently we don't support eDP on TypeC ports, although in
> * theory it could work on TypeC legacy ports.
> */
> - WARN_ON(intel_port_is_tc(dev_priv, port));
> + WARN_ON(intel_phy_is_tc(dev_priv, phy));
> type = DRM_MODE_CONNECTOR_eDP;
> } else {
> type = DRM_MODE_CONNECTOR_DisplayPort;
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> index f953971e7c3b..f8782c24c447 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> @@ -2580,7 +2580,8 @@ static bool icl_calc_dpll_state(struct intel_crtc_state *crtc_state,
> struct skl_wrpll_params pll_params = { 0 };
> bool ret;
>
> - if (intel_port_is_tc(dev_priv, encoder->port))
> + if (intel_phy_is_tc(dev_priv, intel_port_to_phy(dev_priv,
> + encoder->port)))
> ret = icl_calc_tbt_pll(crtc_state, &pll_params);
> else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) ||
> intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI))
> @@ -2993,14 +2994,14 @@ static bool icl_get_dplls(struct intel_atomic_state *state,
> struct intel_encoder *encoder)
> {
> struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> - enum port port = encoder->port;
> + enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
>
> - if (intel_port_is_combophy(dev_priv, port))
> + if (intel_phy_is_combo(dev_priv, phy))
> return icl_get_combo_phy_dpll(state, crtc, encoder);
> - else if (intel_port_is_tc(dev_priv, port))
> + else if (intel_phy_is_tc(dev_priv, phy))
> return icl_get_tc_phy_dplls(state, crtc, encoder);
>
> - MISSING_CASE(port);
> + MISSING_CASE(phy);
>
> return false;
> }
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index 815c26c0b98c..770f9f6aad84 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -1492,9 +1492,7 @@ void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv);
> void intel_encoder_destroy(struct drm_encoder *encoder);
> struct drm_display_mode *
> intel_encoder_current_mode(struct intel_encoder *encoder);
> -bool intel_port_is_combophy(struct drm_i915_private *dev_priv, enum port port);
> bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy phy);
> -bool intel_port_is_tc(struct drm_i915_private *dev_priv, enum port port);
> bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy);
> enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv,
> enum port port);
> --
> 2.17.2
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: [PATCH v4 1/5] drm/i915/gen11: Start distinguishing 'phy' from 'port'
2019-07-05 10:33 ` Ville Syrjälä
@ 2019-07-08 14:02 ` Lucas De Marchi
2019-07-08 14:12 ` Ville Syrjälä
0 siblings, 1 reply; 33+ messages in thread
From: Lucas De Marchi @ 2019-07-08 14:02 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: Jani Nikula, intel-gfx
On Fri, Jul 05, 2019 at 01:33:10PM +0300, Ville Syrjälä wrote:
>On Thu, Jul 04, 2019 at 08:55:51AM -0700, Lucas De Marchi wrote:
>> On Thu, Jul 04, 2019 at 06:09:04PM +0300, Ville Syrjälä wrote:
>> >On Thu, Jul 04, 2019 at 07:54:26AM -0700, Lucas De Marchi wrote:
>> >> On Thu, Jul 04, 2019 at 12:18:11PM +0300, Ville Syrjälä wrote:
>> >> >On Wed, Jul 03, 2019 at 04:37:32PM -0700, Matt Roper wrote:
>> >> >> Our past DDI-based Intel platforms have had a fixed DDI<->PHY mapping.
>> >> >> Because of this, both the bspec documentation and our i915 code has used
>> >> >> the term "port" when talking about either DDI's or PHY's; it was always
>> >> >> easy to tell what terms like "Port A" were referring to from the
>> >> >> context.
>> >> >>
>> >> >> Unfortunately this is starting to break down now that EHL allows PHY-A
>> >> >> to be driven by either DDI-A or DDI-D. Is a setup with DDI-D driving
>> >> >> PHY-A considered "Port A" or "Port D?" The answer depends on which
>> >> >> register we're working with, and even the bspec doesn't do a great job
>> >> >> of clarifying this.
>> >> >>
>> >> >> Let's try to be more explicit about whether we're talking about the DDI
>> >> >> or the PHY on gen11+ by using 'port' to refer to the DDI and creating a
>> >> >> new 'enum phy' namespace to refer to the PHY in use.
>> >> >>
>> >> >> This patch just adds the new PHY namespace, new phy-based versions of
>> >> >> intel_port_is_*(), and a helper to convert a port to a PHY.
>> >> >> Transitioning various areas of the code over to using the PHY namespace
>> >> >> will be done in subsequent patches to make review easier. We'll remove
>> >> >> the intel_port_is_*() functions at the end of the series when we
>> >> >> transition all callers over to using the PHY-based versions.
>> >> >>
>> >> >> v2:
>> >> >> - Convert a few more 'port' uses to 'phy.' (Sparse)
>> >> >>
>> >> >> v3:
>> >> >> - Switch DDI_CLK_SEL() back to 'port.' (Jose)
>> >> >> - Add a code comment clarifying why DPCLKA_CFGCR0_ICL needs to use PHY
>> >> >> for its bit definitions, even though the register description is
>> >> >> given in terms of DDI.
>> >> >> - To avoid confusion, switch CNL's DPCLKA_CFGCR0 defines back to using
>> >> >> port and create separate ICL+ definitions that work in terms of PHY.
>> >> >>
>> >> >> v4:
>> >> >> - Rebase and resolve conflicts with Imre's TC series.
>> >> >> - This patch now just adds the namespace and a few convenience
>> >> >> functions; the important changes are now split out into separate
>> >> >> patches to make review easier.
>> >> >>
>> >> >> Suggested-by: Ville Syrjala <ville.syrjala@linux.intel.com>
>> >> >> Cc: José Roberto de Souza <jose.souza@intel.com>
>> >> >> Cc: Lucas De Marchi <lucas.demarchi@intel.com>
>> >> >> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
>> >> >> Cc: Imre Deak <imre.deak@intel.com>
>> >> >> Cc: Jani Nikula <jani.nikula@intel.com>
>> >> >> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
>> >> >> ---
>> >> >> drivers/gpu/drm/i915/display/intel_display.c | 32 +++++++++++++++++++-
>> >> >> drivers/gpu/drm/i915/display/intel_display.h | 16 ++++++++++
>> >> >> drivers/gpu/drm/i915/intel_drv.h | 2 ++
>> >> >> 3 files changed, 49 insertions(+), 1 deletion(-)
>> >> >>
>> >> >> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
>> >> >> index 919f5ac844c8..4a85abef93e7 100644
>> >> >> --- a/drivers/gpu/drm/i915/display/intel_display.c
>> >> >> +++ b/drivers/gpu/drm/i915/display/intel_display.c
>> >> >> @@ -6663,6 +6663,20 @@ bool intel_port_is_combophy(struct drm_i915_private *dev_priv, enum port port)
>> >> >> return false;
>> >> >> }
>> >> >>
>> >> >> +bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy phy)
>> >> >> +{
>> >> >> + if (phy == PHY_NONE)
>> >> >> + return false;
>> >> >> +
>> >> >> + if (IS_ELKHARTLAKE(dev_priv))
>> >> >> + return phy <= PHY_C;
>> >> >> +
>> >> >> + if (INTEL_GEN(dev_priv) >= 11)
>> >> >> + return phy <= PHY_B;
>> >> >> +
>> >> >> + return false;
>> >> >> +}
>> >> >> +
>> >> >> bool intel_port_is_tc(struct drm_i915_private *dev_priv, enum port port)
>> >> >> {
>> >> >> if (INTEL_GEN(dev_priv) >= 11 && !IS_ELKHARTLAKE(dev_priv))
>> >> >> @@ -6671,9 +6685,25 @@ bool intel_port_is_tc(struct drm_i915_private *dev_priv, enum port port)
>> >> >> return false;
>> >> >> }
>> >> >>
>> >> >> +bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy)
>> >> >> +{
>> >> >> + if (INTEL_GEN(dev_priv) >= 11 && !IS_ELKHARTLAKE(dev_priv))
>> >> >> + return phy >= PHY_C && phy <= PHY_F;
>> >> >> +
>> >> >> + return false;
>> >> >> +}
>> >> >> +
>> >> >> +enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port)
>> >> >> +{
>> >> >> + if (IS_ELKHARTLAKE(i915) && port == PORT_D)
>> >> >> + return PHY_A;
>> >> >> +
>> >> >> + return (enum phy)port;
>> >> >> +}
>> >> >> +
>> >> >> enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv, enum port port)
>> >> >> {
>> >> >> - if (!intel_port_is_tc(dev_priv, port))
>> >> >> + if (!intel_phy_is_tc(dev_priv, intel_port_to_phy(dev_priv, port)))
>> >> >> return PORT_TC_NONE;
>> >> >>
>> >> >> return port - PORT_C;
>> >> >> diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
>> >> >> index d296556ed82e..d53285fb883f 100644
>> >> >> --- a/drivers/gpu/drm/i915/display/intel_display.h
>> >> >> +++ b/drivers/gpu/drm/i915/display/intel_display.h
>> >> >> @@ -228,6 +228,21 @@ struct intel_link_m_n {
>> >> >> u32 link_n;
>> >> >> };
>> >> >>
>> >> >> +enum phy {
>> >> >> + PHY_NONE = -1,
>> >> >> +
>> >> >> + PHY_A = 0,
>> >> >> + PHY_B,
>> >> >> + PHY_C,
>> >> >> + PHY_D,
>> >> >> + PHY_E,
>> >> >> + PHY_F,
>> >> >> +
>> >> >> + I915_MAX_PHYS
>> >> >> +};
>> >> >
>> >> >I was pondering if we could eventually do something like:
>> >> >
>> >> >enum phy {
>> >> > PHY_COMBO_A = 0,
>> >> > PHY_COMBO_B,
>> >> > ...
>> >> >
>> >> > PHY_TC_1,
>> >> > PHY_TC_2,
>> >> > ...
>> >> >};
>> >> >
>> >> >and probably also add encoder->phy so we can contain
>> >> >that port<->phy mapping logic in the encoder init.
>> >> >I think that should work more or less fine since I
>> >> >don't think PHY_TC_1 needs to have any specific value.
>> >>
>> >> that's not true. All TC registers are based off the TC phy number.
>> >
>> >That's just a trivial (x)-TC1, so I stand by what I said.
>>
>> EHL and TGL have 3 combo phys. ICL has 2. So TC1 would have to be a
>> different value for ICL and the others for this to work.
>
>It would just be an arbitrary number (eg. 8).
One that is propagated to every access to those registers, and we need
to keep this enum updated as well the conversion functions because every
platform has a different port->phy mapping. IMO it should be done during
init like in the pseudo code I posted. And in that case TC1 = 0. Always.
Lucas De Marchi
>
>> I think we should treat the index as just a number we use to compute the
>> right base for the registers in that hw IP.
>>
>> >
>> >> Hence all the conversion we do port_to_tc()... I'd like to remove that
>> >> in future and just stuff the phy index in intel_digital_port, as we
>> >> already do for other tc_phy_* fields (we could add a union there so each
>> >> phy adds its own fields).
>> >>
>> >> And I'd rather not do the single phy namespace - it doesn't
>> >> play well with TGL and the combo/tc.
>> >
>> >I think it would work just fine for that. A single namespace would allow
>> >us to remove all the crazy port->PHY type mapping we have going on
>> >currently. Probably the best alternative would be separate namespaces
>> >for each type with a new enum to identify the type.
>>
>> My proposal is in the lines of that alternative approach. Save the phy
>> type and the phy index in intel_digital_port. And allow each phy to store
>> its fields there. Something along:
>>
>> struct intel_digital_port {
>> ...
>> struct {
>> enum phy_type type;
>> u8 idx;
>> union {
>> struct {
>> struct mutex lock; /* protects the TypeC port mode */
>> intel_wakeref_t lock_wakeref;
>> int link_refcount;
>> char tc_port_name[8];
>> enum tc_port_mode tc_mode;
>> bool legacy_port;
>> u8 fia;
>> } tc;
>> struct {
>> ...
>> } combo;
>> struct {
>> ...
>> } dpio??;
>> };
>> } phy;
>> };
>>
>> >From a quick look I don't think the idx is relevant enough to have its
>> own enum, but I wouldn't mind.
>>
>> then no more port->phy everywhere as we have right now and we only
>> assign idx to the right value during init. The TC rework we had recently
>> makes it nice and I'm starting to do it, but I'd rather merge the TGL
>> patches before. For Modular FIA I'm already stashing the fia index
>> there (since I had to redo the support due to the TC rework),
>> but without the additional struct.
>> See https://patchwork.freedesktop.org/series/63175/
>>
>> Lucas De Marchi
>>
>> >
>> >>
>> >> Lucas De Marchi
>> >>
>> >> >
>> >> >Unfortunaltey I don't have a great idea how to do the
>> >> >same for the DDIs since there the number of combo DDIs
>> >> >changes but we still need the PORT_TC1 (assuming we had
>> >> >one) to be DDI_<last combo DDI> + 1. One random silly
>> >> >idea was to decouple the enum port from the register
>> >> >definitions by having just some kind of
>> >> >encoder->port_index for those. But that doesn't feel
>> >> >entirely great either.
>> >> >
>> >> >Anyways, something to think about in the future perhaps.
>> >> >
>> >> >Patch is
>> >> >Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>> >> >
>> >> >> +
>> >> >> +#define phy_name(a) ((a) + 'A')
>> >> >> +
>> >> >> #define for_each_pipe(__dev_priv, __p) \
>> >> >> for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++)
>> >> >>
>> >> >> @@ -356,5 +371,6 @@ void lpt_disable_clkout_dp(struct drm_i915_private *dev_priv);
>> >> >> u32 intel_plane_fb_max_stride(struct drm_i915_private *dev_priv,
>> >> >> u32 pixel_format, u64 modifier);
>> >> >> bool intel_plane_can_remap(const struct intel_plane_state *plane_state);
>> >> >> +enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port);
>> >> >>
>> >> >> #endif
>> >> >> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
>> >> >> index 24c63ed45c6f..815c26c0b98c 100644
>> >> >> --- a/drivers/gpu/drm/i915/intel_drv.h
>> >> >> +++ b/drivers/gpu/drm/i915/intel_drv.h
>> >> >> @@ -1493,7 +1493,9 @@ void intel_encoder_destroy(struct drm_encoder *encoder);
>> >> >> struct drm_display_mode *
>> >> >> intel_encoder_current_mode(struct intel_encoder *encoder);
>> >> >> bool intel_port_is_combophy(struct drm_i915_private *dev_priv, enum port port);
>> >> >> +bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy phy);
>> >> >> bool intel_port_is_tc(struct drm_i915_private *dev_priv, enum port port);
>> >> >> +bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy);
>> >> >> enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv,
>> >> >> enum port port);
>> >> >> int intel_get_pipe_from_crtc_id_ioctl(struct drm_device *dev, void *data,
>> >> >> --
>> >> >> 2.17.2
>> >> >
>> >> >--
>> >> >Ville Syrjälä
>> >> >Intel
>> >
>> >--
>> >Ville Syrjälä
>> >Intel
>
>--
>Ville Syrjälä
>Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: [PATCH v4 1/5] drm/i915/gen11: Start distinguishing 'phy' from 'port'
2019-07-08 14:02 ` Lucas De Marchi
@ 2019-07-08 14:12 ` Ville Syrjälä
0 siblings, 0 replies; 33+ messages in thread
From: Ville Syrjälä @ 2019-07-08 14:12 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: Jani Nikula, intel-gfx
On Mon, Jul 08, 2019 at 07:02:49AM -0700, Lucas De Marchi wrote:
> On Fri, Jul 05, 2019 at 01:33:10PM +0300, Ville Syrjälä wrote:
> >On Thu, Jul 04, 2019 at 08:55:51AM -0700, Lucas De Marchi wrote:
> >> On Thu, Jul 04, 2019 at 06:09:04PM +0300, Ville Syrjälä wrote:
> >> >On Thu, Jul 04, 2019 at 07:54:26AM -0700, Lucas De Marchi wrote:
> >> >> On Thu, Jul 04, 2019 at 12:18:11PM +0300, Ville Syrjälä wrote:
> >> >> >On Wed, Jul 03, 2019 at 04:37:32PM -0700, Matt Roper wrote:
> >> >> >> Our past DDI-based Intel platforms have had a fixed DDI<->PHY mapping.
> >> >> >> Because of this, both the bspec documentation and our i915 code has used
> >> >> >> the term "port" when talking about either DDI's or PHY's; it was always
> >> >> >> easy to tell what terms like "Port A" were referring to from the
> >> >> >> context.
> >> >> >>
> >> >> >> Unfortunately this is starting to break down now that EHL allows PHY-A
> >> >> >> to be driven by either DDI-A or DDI-D. Is a setup with DDI-D driving
> >> >> >> PHY-A considered "Port A" or "Port D?" The answer depends on which
> >> >> >> register we're working with, and even the bspec doesn't do a great job
> >> >> >> of clarifying this.
> >> >> >>
> >> >> >> Let's try to be more explicit about whether we're talking about the DDI
> >> >> >> or the PHY on gen11+ by using 'port' to refer to the DDI and creating a
> >> >> >> new 'enum phy' namespace to refer to the PHY in use.
> >> >> >>
> >> >> >> This patch just adds the new PHY namespace, new phy-based versions of
> >> >> >> intel_port_is_*(), and a helper to convert a port to a PHY.
> >> >> >> Transitioning various areas of the code over to using the PHY namespace
> >> >> >> will be done in subsequent patches to make review easier. We'll remove
> >> >> >> the intel_port_is_*() functions at the end of the series when we
> >> >> >> transition all callers over to using the PHY-based versions.
> >> >> >>
> >> >> >> v2:
> >> >> >> - Convert a few more 'port' uses to 'phy.' (Sparse)
> >> >> >>
> >> >> >> v3:
> >> >> >> - Switch DDI_CLK_SEL() back to 'port.' (Jose)
> >> >> >> - Add a code comment clarifying why DPCLKA_CFGCR0_ICL needs to use PHY
> >> >> >> for its bit definitions, even though the register description is
> >> >> >> given in terms of DDI.
> >> >> >> - To avoid confusion, switch CNL's DPCLKA_CFGCR0 defines back to using
> >> >> >> port and create separate ICL+ definitions that work in terms of PHY.
> >> >> >>
> >> >> >> v4:
> >> >> >> - Rebase and resolve conflicts with Imre's TC series.
> >> >> >> - This patch now just adds the namespace and a few convenience
> >> >> >> functions; the important changes are now split out into separate
> >> >> >> patches to make review easier.
> >> >> >>
> >> >> >> Suggested-by: Ville Syrjala <ville.syrjala@linux.intel.com>
> >> >> >> Cc: José Roberto de Souza <jose.souza@intel.com>
> >> >> >> Cc: Lucas De Marchi <lucas.demarchi@intel.com>
> >> >> >> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >> >> >> Cc: Imre Deak <imre.deak@intel.com>
> >> >> >> Cc: Jani Nikula <jani.nikula@intel.com>
> >> >> >> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> >> >> >> ---
> >> >> >> drivers/gpu/drm/i915/display/intel_display.c | 32 +++++++++++++++++++-
> >> >> >> drivers/gpu/drm/i915/display/intel_display.h | 16 ++++++++++
> >> >> >> drivers/gpu/drm/i915/intel_drv.h | 2 ++
> >> >> >> 3 files changed, 49 insertions(+), 1 deletion(-)
> >> >> >>
> >> >> >> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> >> >> >> index 919f5ac844c8..4a85abef93e7 100644
> >> >> >> --- a/drivers/gpu/drm/i915/display/intel_display.c
> >> >> >> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> >> >> >> @@ -6663,6 +6663,20 @@ bool intel_port_is_combophy(struct drm_i915_private *dev_priv, enum port port)
> >> >> >> return false;
> >> >> >> }
> >> >> >>
> >> >> >> +bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy phy)
> >> >> >> +{
> >> >> >> + if (phy == PHY_NONE)
> >> >> >> + return false;
> >> >> >> +
> >> >> >> + if (IS_ELKHARTLAKE(dev_priv))
> >> >> >> + return phy <= PHY_C;
> >> >> >> +
> >> >> >> + if (INTEL_GEN(dev_priv) >= 11)
> >> >> >> + return phy <= PHY_B;
> >> >> >> +
> >> >> >> + return false;
> >> >> >> +}
> >> >> >> +
> >> >> >> bool intel_port_is_tc(struct drm_i915_private *dev_priv, enum port port)
> >> >> >> {
> >> >> >> if (INTEL_GEN(dev_priv) >= 11 && !IS_ELKHARTLAKE(dev_priv))
> >> >> >> @@ -6671,9 +6685,25 @@ bool intel_port_is_tc(struct drm_i915_private *dev_priv, enum port port)
> >> >> >> return false;
> >> >> >> }
> >> >> >>
> >> >> >> +bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy)
> >> >> >> +{
> >> >> >> + if (INTEL_GEN(dev_priv) >= 11 && !IS_ELKHARTLAKE(dev_priv))
> >> >> >> + return phy >= PHY_C && phy <= PHY_F;
> >> >> >> +
> >> >> >> + return false;
> >> >> >> +}
> >> >> >> +
> >> >> >> +enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port)
> >> >> >> +{
> >> >> >> + if (IS_ELKHARTLAKE(i915) && port == PORT_D)
> >> >> >> + return PHY_A;
> >> >> >> +
> >> >> >> + return (enum phy)port;
> >> >> >> +}
> >> >> >> +
> >> >> >> enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv, enum port port)
> >> >> >> {
> >> >> >> - if (!intel_port_is_tc(dev_priv, port))
> >> >> >> + if (!intel_phy_is_tc(dev_priv, intel_port_to_phy(dev_priv, port)))
> >> >> >> return PORT_TC_NONE;
> >> >> >>
> >> >> >> return port - PORT_C;
> >> >> >> diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
> >> >> >> index d296556ed82e..d53285fb883f 100644
> >> >> >> --- a/drivers/gpu/drm/i915/display/intel_display.h
> >> >> >> +++ b/drivers/gpu/drm/i915/display/intel_display.h
> >> >> >> @@ -228,6 +228,21 @@ struct intel_link_m_n {
> >> >> >> u32 link_n;
> >> >> >> };
> >> >> >>
> >> >> >> +enum phy {
> >> >> >> + PHY_NONE = -1,
> >> >> >> +
> >> >> >> + PHY_A = 0,
> >> >> >> + PHY_B,
> >> >> >> + PHY_C,
> >> >> >> + PHY_D,
> >> >> >> + PHY_E,
> >> >> >> + PHY_F,
> >> >> >> +
> >> >> >> + I915_MAX_PHYS
> >> >> >> +};
> >> >> >
> >> >> >I was pondering if we could eventually do something like:
> >> >> >
> >> >> >enum phy {
> >> >> > PHY_COMBO_A = 0,
> >> >> > PHY_COMBO_B,
> >> >> > ...
> >> >> >
> >> >> > PHY_TC_1,
> >> >> > PHY_TC_2,
> >> >> > ...
> >> >> >};
> >> >> >
> >> >> >and probably also add encoder->phy so we can contain
> >> >> >that port<->phy mapping logic in the encoder init.
> >> >> >I think that should work more or less fine since I
> >> >> >don't think PHY_TC_1 needs to have any specific value.
> >> >>
> >> >> that's not true. All TC registers are based off the TC phy number.
> >> >
> >> >That's just a trivial (x)-TC1, so I stand by what I said.
> >>
> >> EHL and TGL have 3 combo phys. ICL has 2. So TC1 would have to be a
> >> different value for ICL and the others for this to work.
> >
> >It would just be an arbitrary number (eg. 8).
>
> One that is propagated to every access to those registers, and we need
> to keep this enum updated as well the conversion functions because every
> platform has a different port->phy mapping.
The port->phy mapping doesn't matter. The enum is just about the phy.
And reg macros would be just something like:
#define _TC_PHY_IDX(phy) ((phy)-PHY_TC1)
#define BLAH(phy) _MMIO(..._TC_PHY_IDX(phy)...)
> IMO it should be done during
> init like in the pseudo code I posted. And in that case TC1 = 0. Always.
>
> Lucas De Marchi
>
> >
> >> I think we should treat the index as just a number we use to compute the
> >> right base for the registers in that hw IP.
> >>
> >> >
> >> >> Hence all the conversion we do port_to_tc()... I'd like to remove that
> >> >> in future and just stuff the phy index in intel_digital_port, as we
> >> >> already do for other tc_phy_* fields (we could add a union there so each
> >> >> phy adds its own fields).
> >> >>
> >> >> And I'd rather not do the single phy namespace - it doesn't
> >> >> play well with TGL and the combo/tc.
> >> >
> >> >I think it would work just fine for that. A single namespace would allow
> >> >us to remove all the crazy port->PHY type mapping we have going on
> >> >currently. Probably the best alternative would be separate namespaces
> >> >for each type with a new enum to identify the type.
> >>
> >> My proposal is in the lines of that alternative approach. Save the phy
> >> type and the phy index in intel_digital_port. And allow each phy to store
> >> its fields there. Something along:
> >>
> >> struct intel_digital_port {
> >> ...
> >> struct {
> >> enum phy_type type;
> >> u8 idx;
> >> union {
> >> struct {
> >> struct mutex lock; /* protects the TypeC port mode */
> >> intel_wakeref_t lock_wakeref;
> >> int link_refcount;
> >> char tc_port_name[8];
> >> enum tc_port_mode tc_mode;
> >> bool legacy_port;
> >> u8 fia;
> >> } tc;
> >> struct {
> >> ...
> >> } combo;
> >> struct {
> >> ...
> >> } dpio??;
> >> };
> >> } phy;
> >> };
> >>
> >> >From a quick look I don't think the idx is relevant enough to have its
> >> own enum, but I wouldn't mind.
> >>
> >> then no more port->phy everywhere as we have right now and we only
> >> assign idx to the right value during init. The TC rework we had recently
> >> makes it nice and I'm starting to do it, but I'd rather merge the TGL
> >> patches before. For Modular FIA I'm already stashing the fia index
> >> there (since I had to redo the support due to the TC rework),
> >> but without the additional struct.
> >> See https://patchwork.freedesktop.org/series/63175/
> >>
> >> Lucas De Marchi
> >>
> >> >
> >> >>
> >> >> Lucas De Marchi
> >> >>
> >> >> >
> >> >> >Unfortunaltey I don't have a great idea how to do the
> >> >> >same for the DDIs since there the number of combo DDIs
> >> >> >changes but we still need the PORT_TC1 (assuming we had
> >> >> >one) to be DDI_<last combo DDI> + 1. One random silly
> >> >> >idea was to decouple the enum port from the register
> >> >> >definitions by having just some kind of
> >> >> >encoder->port_index for those. But that doesn't feel
> >> >> >entirely great either.
> >> >> >
> >> >> >Anyways, something to think about in the future perhaps.
> >> >> >
> >> >> >Patch is
> >> >> >Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >> >> >
> >> >> >> +
> >> >> >> +#define phy_name(a) ((a) + 'A')
> >> >> >> +
> >> >> >> #define for_each_pipe(__dev_priv, __p) \
> >> >> >> for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++)
> >> >> >>
> >> >> >> @@ -356,5 +371,6 @@ void lpt_disable_clkout_dp(struct drm_i915_private *dev_priv);
> >> >> >> u32 intel_plane_fb_max_stride(struct drm_i915_private *dev_priv,
> >> >> >> u32 pixel_format, u64 modifier);
> >> >> >> bool intel_plane_can_remap(const struct intel_plane_state *plane_state);
> >> >> >> +enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port);
> >> >> >>
> >> >> >> #endif
> >> >> >> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> >> >> >> index 24c63ed45c6f..815c26c0b98c 100644
> >> >> >> --- a/drivers/gpu/drm/i915/intel_drv.h
> >> >> >> +++ b/drivers/gpu/drm/i915/intel_drv.h
> >> >> >> @@ -1493,7 +1493,9 @@ void intel_encoder_destroy(struct drm_encoder *encoder);
> >> >> >> struct drm_display_mode *
> >> >> >> intel_encoder_current_mode(struct intel_encoder *encoder);
> >> >> >> bool intel_port_is_combophy(struct drm_i915_private *dev_priv, enum port port);
> >> >> >> +bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy phy);
> >> >> >> bool intel_port_is_tc(struct drm_i915_private *dev_priv, enum port port);
> >> >> >> +bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy);
> >> >> >> enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv,
> >> >> >> enum port port);
> >> >> >> int intel_get_pipe_from_crtc_id_ioctl(struct drm_device *dev, void *data,
> >> >> >> --
> >> >> >> 2.17.2
> >> >> >
> >> >> >--
> >> >> >Ville Syrjälä
> >> >> >Intel
> >> >
> >> >--
> >> >Ville Syrjälä
> >> >Intel
> >
> >--
> >Ville Syrjälä
> >Intel
--
Ville Syrjälä
Intel
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: [PATCH v4 1/5] drm/i915/gen11: Start distinguishing 'phy' from 'port'
2019-07-03 23:37 ` [PATCH v4 1/5] drm/i915/gen11: Start distinguishing 'phy' from 'port' Matt Roper
2019-07-04 9:18 ` Ville Syrjälä
@ 2019-07-08 23:59 ` Souza, Jose
2019-07-09 0:45 ` Souza, Jose
1 sibling, 1 reply; 33+ messages in thread
From: Souza, Jose @ 2019-07-08 23:59 UTC (permalink / raw)
To: Roper, Matthew D, intel-gfx; +Cc: Nikula, Jani, De Marchi, Lucas
On Wed, 2019-07-03 at 16:37 -0700, Matt Roper wrote:
> Our past DDI-based Intel platforms have had a fixed DDI<->PHY
> mapping.
> Because of this, both the bspec documentation and our i915 code has
> used
> the term "port" when talking about either DDI's or PHY's; it was
> always
> easy to tell what terms like "Port A" were referring to from the
> context.
>
> Unfortunately this is starting to break down now that EHL allows PHY-
> A
> to be driven by either DDI-A or DDI-D. Is a setup with DDI-D driving
> PHY-A considered "Port A" or "Port D?" The answer depends on which
> register we're working with, and even the bspec doesn't do a great
> job
> of clarifying this.
>
> Let's try to be more explicit about whether we're talking about the
> DDI
> or the PHY on gen11+ by using 'port' to refer to the DDI and creating
> a
> new 'enum phy' namespace to refer to the PHY in use.
>
> This patch just adds the new PHY namespace, new phy-based versions of
> intel_port_is_*(), and a helper to convert a port to a PHY.
> Transitioning various areas of the code over to using the PHY
> namespace
> will be done in subsequent patches to make review easier. We'll
> remove
> the intel_port_is_*() functions at the end of the series when we
> transition all callers over to using the PHY-based versions.
>
> v2:
> - Convert a few more 'port' uses to 'phy.' (Sparse)
>
> v3:
> - Switch DDI_CLK_SEL() back to 'port.' (Jose)
> - Add a code comment clarifying why DPCLKA_CFGCR0_ICL needs to use
> PHY
> for its bit definitions, even though the register description is
> given in terms of DDI.
> - To avoid confusion, switch CNL's DPCLKA_CFGCR0 defines back to
> using
> port and create separate ICL+ definitions that work in terms of
> PHY.
>
> v4:
> - Rebase and resolve conflicts with Imre's TC series.
> - This patch now just adds the namespace and a few convenience
> functions; the important changes are now split out into separate
> patches to make review easier.
>
> Suggested-by: Ville Syrjala <ville.syrjala@linux.intel.com>
> Cc: José Roberto de Souza <jose.souza@intel.com>
> Cc: Lucas De Marchi <lucas.demarchi@intel.com>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Cc: Imre Deak <imre.deak@intel.com>
> Cc: Jani Nikula <jani.nikula@intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 32
> +++++++++++++++++++-
> drivers/gpu/drm/i915/display/intel_display.h | 16 ++++++++++
> drivers/gpu/drm/i915/intel_drv.h | 2 ++
> 3 files changed, 49 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index 919f5ac844c8..4a85abef93e7 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -6663,6 +6663,20 @@ bool intel_port_is_combophy(struct
> drm_i915_private *dev_priv, enum port port)
> return false;
> }
A call to intel_port_is_combophy(PORT_D) would return false on EHL, it
and intel_port_is_tc() should use intel_phy functions, like:
bool intel_port_is_combophy(struct drm_i915_private *dev_priv, enum
port port)
{
return intel_phy_is_combo(dev_priv, intel_port_to_phy(dev_priv,
port));
}
Even better would be check if we can replace those with intel_phy
counterparts.
>
> +bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy
> phy)
> +{
> + if (phy == PHY_NONE)
> + return false;
> +
> + if (IS_ELKHARTLAKE(dev_priv))
> + return phy <= PHY_C;
> +
> + if (INTEL_GEN(dev_priv) >= 11)
> + return phy <= PHY_B;
> +
> + return false;
> +}
> +
> bool intel_port_is_tc(struct drm_i915_private *dev_priv, enum port
> port)
> {
> if (INTEL_GEN(dev_priv) >= 11 && !IS_ELKHARTLAKE(dev_priv))
> @@ -6671,9 +6685,25 @@ bool intel_port_is_tc(struct drm_i915_private
> *dev_priv, enum port port)
> return false;
> }
>
> +bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy
> phy)
> +{
> + if (INTEL_GEN(dev_priv) >= 11 && !IS_ELKHARTLAKE(dev_priv))
> + return phy >= PHY_C && phy <= PHY_F;
> +
> + return false;
> +}
> +
> +enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port
> port)
> +{
> + if (IS_ELKHARTLAKE(i915) && port == PORT_D)
> + return PHY_A;
> +
> + return (enum phy)port;
> +}
> +
> enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv,
> enum port port)
> {
> - if (!intel_port_is_tc(dev_priv, port))
> + if (!intel_phy_is_tc(dev_priv, intel_port_to_phy(dev_priv,
> port)))
> return PORT_TC_NONE;
>
> return port - PORT_C;
> diff --git a/drivers/gpu/drm/i915/display/intel_display.h
> b/drivers/gpu/drm/i915/display/intel_display.h
> index d296556ed82e..d53285fb883f 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.h
> +++ b/drivers/gpu/drm/i915/display/intel_display.h
> @@ -228,6 +228,21 @@ struct intel_link_m_n {
> u32 link_n;
> };
>
> +enum phy {
> + PHY_NONE = -1,
> +
> + PHY_A = 0,
> + PHY_B,
> + PHY_C,
> + PHY_D,
> + PHY_E,
> + PHY_F,
> +
> + I915_MAX_PHYS
> +};
> +
> +#define phy_name(a) ((a) + 'A')
> +
> #define for_each_pipe(__dev_priv, __p) \
> for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes;
> (__p)++)
>
> @@ -356,5 +371,6 @@ void lpt_disable_clkout_dp(struct
> drm_i915_private *dev_priv);
> u32 intel_plane_fb_max_stride(struct drm_i915_private *dev_priv,
> u32 pixel_format, u64 modifier);
> bool intel_plane_can_remap(const struct intel_plane_state
> *plane_state);
> +enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port
> port);
>
> #endif
> diff --git a/drivers/gpu/drm/i915/intel_drv.h
> b/drivers/gpu/drm/i915/intel_drv.h
> index 24c63ed45c6f..815c26c0b98c 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -1493,7 +1493,9 @@ void intel_encoder_destroy(struct drm_encoder
> *encoder);
> struct drm_display_mode *
> intel_encoder_current_mode(struct intel_encoder *encoder);
> bool intel_port_is_combophy(struct drm_i915_private *dev_priv, enum
> port port);
> +bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy
> phy);
> bool intel_port_is_tc(struct drm_i915_private *dev_priv, enum port
> port);
> +bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy
> phy);
> enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv,
> enum port port);
> int intel_get_pipe_from_crtc_id_ioctl(struct drm_device *dev, void
> *data,
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^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: [PATCH v5 2/5] drm/i915/gen11: Program DPCLKA_CFGCR0_ICL according to PHY
2019-07-04 1:06 ` [PATCH v5 " Matt Roper
2019-07-04 9:31 ` Ville Syrjälä
@ 2019-07-09 0:15 ` Souza, Jose
1 sibling, 0 replies; 33+ messages in thread
From: Souza, Jose @ 2019-07-09 0:15 UTC (permalink / raw)
To: Roper, Matthew D, intel-gfx
On Wed, 2019-07-03 at 18:06 -0700, Matt Roper wrote:
> Although the register name implies that it operates on DDI's,
> DPCLKA_CFGCR0_ICL actually needs to be programmed according to the
> PHY
> that's in use. I.e., when using EHL's DDI-D on combo PHY A, the bits
> described as "port A" in the bspec are what we need to set. The
> bspec
> clarifies:
>
> "[For EHL] DDID clock tied to DDIA clock, so DPCLKA_CFGCR0
> DDIA
> Clock Select chooses the PLL for both DDIA and DDID and
> drives
> port A in all cases."
>
> Also, since the CNL DPCLKA_CFGCR0 bit defines are still port-based,
> we
> create separate ICL-specific defines that accept the PHY rather than
> trying to share the same bit definitions between CNL and ICL.
>
Nit: Why not already rename DPCLKA_CFGCR0_ICL to ICL_DPCLKA_CFGCR0? The
bits have the new name, so you are already touching in everyplace that
uses DPCLKA_CFGCR0_ICL.
> v5: Make icl_dpclka_cfgcr0_clk_off() take phy rather than port. When
> splitting the original patch the hunk to handle this wound up too
> late in the series. (Sparse)
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
>
> Bspec: 33148
> Cc: José Roberto de Souza <jose.souza@intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> ---
> drivers/gpu/drm/i915/display/icl_dsi.c | 17 ++++++---
> drivers/gpu/drm/i915/display/intel_ddi.c | 47 +++++++++++++++-------
> --
> drivers/gpu/drm/i915/i915_reg.h | 12 ++++--
> 3 files changed, 50 insertions(+), 26 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c
> b/drivers/gpu/drm/i915/display/icl_dsi.c
> index b8673debf932..f574af62888c 100644
> --- a/drivers/gpu/drm/i915/display/icl_dsi.c
> +++ b/drivers/gpu/drm/i915/display/icl_dsi.c
> @@ -560,11 +560,13 @@ static void gen11_dsi_gate_clocks(struct
> intel_encoder *encoder)
> struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
> u32 tmp;
> enum port port;
> + enum phy phy;
>
> mutex_lock(&dev_priv->dpll_lock);
> tmp = I915_READ(DPCLKA_CFGCR0_ICL);
> for_each_dsi_port(port, intel_dsi->ports) {
> - tmp |= DPCLKA_CFGCR0_DDI_CLK_OFF(port);
> + phy = intel_port_to_phy(dev_priv, port);
> + tmp |= ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
> }
>
> I915_WRITE(DPCLKA_CFGCR0_ICL, tmp);
> @@ -577,11 +579,13 @@ static void gen11_dsi_ungate_clocks(struct
> intel_encoder *encoder)
> struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
> u32 tmp;
> enum port port;
> + enum phy phy;
>
> mutex_lock(&dev_priv->dpll_lock);
> tmp = I915_READ(DPCLKA_CFGCR0_ICL);
> for_each_dsi_port(port, intel_dsi->ports) {
> - tmp &= ~DPCLKA_CFGCR0_DDI_CLK_OFF(port);
> + phy = intel_port_to_phy(dev_priv, port);
> + tmp &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
> }
>
> I915_WRITE(DPCLKA_CFGCR0_ICL, tmp);
> @@ -595,19 +599,22 @@ static void gen11_dsi_map_pll(struct
> intel_encoder *encoder,
> struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
> struct intel_shared_dpll *pll = crtc_state->shared_dpll;
> enum port port;
> + enum phy phy;
> u32 val;
>
> mutex_lock(&dev_priv->dpll_lock);
>
> val = I915_READ(DPCLKA_CFGCR0_ICL);
> for_each_dsi_port(port, intel_dsi->ports) {
> - val &= ~DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
> - val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, port);
> + phy = intel_port_to_phy(dev_priv, port);
> + val &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
> + val |= ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id,
> phy);
> }
> I915_WRITE(DPCLKA_CFGCR0_ICL, val);
>
> for_each_dsi_port(port, intel_dsi->ports) {
> - val &= ~DPCLKA_CFGCR0_DDI_CLK_OFF(port);
> + phy = intel_port_to_phy(dev_priv, port);
> + val &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
> }
> I915_WRITE(DPCLKA_CFGCR0_ICL, val);
>
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> b/drivers/gpu/drm/i915/display/intel_ddi.c
> index a4172595c8d8..065feb917db4 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -2729,12 +2729,13 @@ u32 ddi_signal_levels(struct intel_dp
> *intel_dp)
>
> static inline
> u32 icl_dpclka_cfgcr0_clk_off(struct drm_i915_private *dev_priv,
> - enum port port)
> + enum phy phy)
> {
> - if (intel_port_is_combophy(dev_priv, port)) {
> - return ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(port);
> - } else if (intel_port_is_tc(dev_priv, port)) {
> - enum tc_port tc_port = intel_port_to_tc(dev_priv,
> port);
> + if (intel_phy_is_combo(dev_priv, phy)) {
> + return ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
> + } else if (intel_phy_is_tc(dev_priv, phy)) {
> + enum tc_port tc_port = intel_port_to_tc(dev_priv,
> + (enum
> port)phy);
>
> return ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port);
> }
> @@ -2747,22 +2748,32 @@ static void icl_map_plls_to_ports(struct
> intel_encoder *encoder,
> {
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> struct intel_shared_dpll *pll = crtc_state->shared_dpll;
> - enum port port = encoder->port;
> + enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
> u32 val;
>
> mutex_lock(&dev_priv->dpll_lock);
>
> val = I915_READ(DPCLKA_CFGCR0_ICL);
> - WARN_ON((val & icl_dpclka_cfgcr0_clk_off(dev_priv, port)) ==
> 0);
> + WARN_ON((val & icl_dpclka_cfgcr0_clk_off(dev_priv, phy)) == 0);
>
> - if (intel_port_is_combophy(dev_priv, port)) {
> - val &= ~DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
> - val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, port);
> + if (intel_phy_is_combo(dev_priv, phy)) {
> + /*
> + * Even though this register references DDIs, note that
> we
> + * want to pass the PHY rather than the port
> (DDI). For
> + * ICL, port=phy in all cases so it doesn't matter, but
> for
> + * EHL the bspec notes the following:
> + *
> + * "DDID clock tied to DDIA clock, so DPCLKA_CFGCR0
> DDIA
> + * Clock Select chooses the PLL for both DDIA and
> DDID and
> + * drives port A in all cases."
> + */
> + val &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
> + val |= ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id,
> phy);
> I915_WRITE(DPCLKA_CFGCR0_ICL, val);
> POSTING_READ(DPCLKA_CFGCR0_ICL);
> }
>
> - val &= ~icl_dpclka_cfgcr0_clk_off(dev_priv, port);
> + val &= ~icl_dpclka_cfgcr0_clk_off(dev_priv, phy);
> I915_WRITE(DPCLKA_CFGCR0_ICL, val);
>
> mutex_unlock(&dev_priv->dpll_lock);
> @@ -2771,13 +2782,13 @@ static void icl_map_plls_to_ports(struct
> intel_encoder *encoder,
> static void icl_unmap_plls_to_ports(struct intel_encoder *encoder)
> {
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> - enum port port = encoder->port;
> + enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
> u32 val;
>
> mutex_lock(&dev_priv->dpll_lock);
>
> val = I915_READ(DPCLKA_CFGCR0_ICL);
> - val |= icl_dpclka_cfgcr0_clk_off(dev_priv, port);
> + val |= icl_dpclka_cfgcr0_clk_off(dev_priv, phy);
> I915_WRITE(DPCLKA_CFGCR0_ICL, val);
>
> mutex_unlock(&dev_priv->dpll_lock);
> @@ -2838,9 +2849,11 @@ void icl_sanitize_encoder_pll_mapping(struct
> intel_encoder *encoder)
>
> val = I915_READ(DPCLKA_CFGCR0_ICL);
> for_each_port_masked(port, port_mask) {
> + enum phy phy = intel_port_to_phy(dev_priv, port);
> +
> bool ddi_clk_ungated = !(val &
> icl_dpclka_cfgcr0_clk_off(dev_
> priv,
> - port
> ));
> + phy)
> );
>
> if (ddi_clk_needed == ddi_clk_ungated)
> continue;
> @@ -2852,9 +2865,9 @@ void icl_sanitize_encoder_pll_mapping(struct
> intel_encoder *encoder)
> if (WARN_ON(ddi_clk_needed))
> continue;
>
> - DRM_NOTE("Port %c is disabled/in DSI mode with an
> ungated DDI clock, gate it\n",
> - port_name(port));
> - val |= icl_dpclka_cfgcr0_clk_off(dev_priv, port);
> + DRM_NOTE("PHY %c is disabled/in DSI mode with an
> ungated DDI clock, gate it\n",
> + phy_name(port));
> + val |= icl_dpclka_cfgcr0_clk_off(dev_priv, phy);
> I915_WRITE(DPCLKA_CFGCR0_ICL, val);
> }
> }
> diff --git a/drivers/gpu/drm/i915/i915_reg.h
> b/drivers/gpu/drm/i915/i915_reg.h
> index c814cc1b3ae5..c9e2e09b6f01 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -9680,17 +9680,21 @@ enum skl_power_gate {
> * CNL Clocks
> */
> #define DPCLKA_CFGCR0 _MMIO(0x6C200)
> -#define DPCLKA_CFGCR0_ICL _MMIO(0x164280)
> #define DPCLKA_CFGCR0_DDI_CLK_OFF(port) (1 << ((port)
> == PORT_F ? 23 : \
> (port) + 10))
> -#define ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(port) (1 << ((port) + 10))
> -#define ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port) (1 << ((tc_port) ==
> PORT_TC4 ? \
> - 21 : (tc_port) +
> 12))
> #define DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port) ((port) ==
> PORT_F ? 21 : \
> (port) * 2)
> #define DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port) (3 <<
> DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port))
> #define DPCLKA_CFGCR0_DDI_CLK_SEL(pll, port) ((pll) <<
> DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port))
>
> +#define DPCLKA_CFGCR0_ICL _MMIO(0x164280)
> +#define ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy) (1 << _PICK(phy, 10,
> 11, 24))
> +#define ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port) (1 << ((tc_port) ==
> PORT_TC4 ? \
> + 21 : (tc_port) +
> 12))
> +#define ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy) ((phy) * 2)
> +#define ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy) (3 <<
> ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy))
> +#define ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll, phy) ((pll) <<
> ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy))
> +
> /* CNL PLL */
> #define DPLL0_ENABLE 0x46010
> #define DPLL1_ENABLE 0x46014
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^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: [PATCH v4 3/5] drm/i915/gen11: Convert combo PHY logic to use new 'enum phy' namespace
2019-07-03 23:37 ` [PATCH v4 3/5] drm/i915/gen11: Convert combo PHY logic to use new 'enum phy' namespace Matt Roper
2019-07-04 9:39 ` Ville Syrjälä
@ 2019-07-09 0:41 ` Souza, Jose
1 sibling, 0 replies; 33+ messages in thread
From: Souza, Jose @ 2019-07-09 0:41 UTC (permalink / raw)
To: Roper, Matthew D, intel-gfx
On Wed, 2019-07-03 at 16:37 -0700, Matt Roper wrote:
> Convert the code that operates directly on gen11 combo PHY's to use
> the
> new namespace. Combo PHY registers are those named "ICL_PORT_*" plus
> ICL_DPHY_CHKN.
>
> Note that a lot of the PHY programming happens in the MIPI DSI code.
> For clarity I've added a for_each_dsi_phy() to loop over the phys
> used
> by DSI. Since DSI always uses A & B on gen11, port=phy in all cases
> so
> it doesn't actually matter which form we use in the DSI code. I've
> used
> the phy iterator in code that's explicitly working with the combo
> PHY,
> but left the rest of the DSI code using the port iterator and
> namespace
> to minimize patch deltas. We can switch the rest of the DSI code
> over
> to use phy terminology later if this winds up being too confusing.
>
> Cc: José Roberto de Souza <jose.souza@intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> ---
> drivers/gpu/drm/i915/display/icl_dsi.c | 127 ++++++++--------
> .../gpu/drm/i915/display/intel_combo_phy.c | 143 +++++++++-------
> --
> .../gpu/drm/i915/display/intel_combo_phy.h | 3 +-
> drivers/gpu/drm/i915/display/intel_ddi.c | 45 +++---
> drivers/gpu/drm/i915/display/intel_display.h | 4 +
> .../drm/i915/display/intel_display_power.c | 16 +-
> drivers/gpu/drm/i915/display/intel_dsi.h | 12 +-
> drivers/gpu/drm/i915/i915_reg.h | 74 ++++-----
> 8 files changed, 213 insertions(+), 211 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c
> b/drivers/gpu/drm/i915/display/icl_dsi.c
> index f574af62888c..575196f892c2 100644
> --- a/drivers/gpu/drm/i915/display/icl_dsi.c
> +++ b/drivers/gpu/drm/i915/display/icl_dsi.c
> @@ -202,63 +202,62 @@ static void
> dsi_program_swing_and_deemphasis(struct intel_encoder *encoder)
> {
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
> - enum port port;
> + enum phy phy;
> u32 tmp;
> int lane;
>
> - for_each_dsi_port(port, intel_dsi->ports) {
> -
> + for_each_dsi_phy(phy, intel_dsi->phys) {
> /*
> * Program voltage swing and pre-emphasis level values
> as per
> * table in BSPEC under DDI buffer programing
> */
> - tmp = I915_READ(ICL_PORT_TX_DW5_LN0(port));
> + tmp = I915_READ(ICL_PORT_TX_DW5_LN0(phy));
> tmp &= ~(SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK);
> tmp |= SCALING_MODE_SEL(0x2);
> tmp |= TAP2_DISABLE | TAP3_DISABLE;
> tmp |= RTERM_SELECT(0x6);
> - I915_WRITE(ICL_PORT_TX_DW5_GRP(port), tmp);
> + I915_WRITE(ICL_PORT_TX_DW5_GRP(phy), tmp);
>
> - tmp = I915_READ(ICL_PORT_TX_DW5_AUX(port));
> + tmp = I915_READ(ICL_PORT_TX_DW5_AUX(phy));
> tmp &= ~(SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK);
> tmp |= SCALING_MODE_SEL(0x2);
> tmp |= TAP2_DISABLE | TAP3_DISABLE;
> tmp |= RTERM_SELECT(0x6);
> - I915_WRITE(ICL_PORT_TX_DW5_AUX(port), tmp);
> + I915_WRITE(ICL_PORT_TX_DW5_AUX(phy), tmp);
>
> - tmp = I915_READ(ICL_PORT_TX_DW2_LN0(port));
> + tmp = I915_READ(ICL_PORT_TX_DW2_LN0(phy));
> tmp &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK |
> RCOMP_SCALAR_MASK);
> tmp |= SWING_SEL_UPPER(0x2);
> tmp |= SWING_SEL_LOWER(0x2);
> tmp |= RCOMP_SCALAR(0x98);
> - I915_WRITE(ICL_PORT_TX_DW2_GRP(port), tmp);
> + I915_WRITE(ICL_PORT_TX_DW2_GRP(phy), tmp);
>
> - tmp = I915_READ(ICL_PORT_TX_DW2_AUX(port));
> + tmp = I915_READ(ICL_PORT_TX_DW2_AUX(phy));
> tmp &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK |
> RCOMP_SCALAR_MASK);
> tmp |= SWING_SEL_UPPER(0x2);
> tmp |= SWING_SEL_LOWER(0x2);
> tmp |= RCOMP_SCALAR(0x98);
> - I915_WRITE(ICL_PORT_TX_DW2_AUX(port), tmp);
> + I915_WRITE(ICL_PORT_TX_DW2_AUX(phy), tmp);
>
> - tmp = I915_READ(ICL_PORT_TX_DW4_AUX(port));
> + tmp = I915_READ(ICL_PORT_TX_DW4_AUX(phy));
> tmp &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK |
> CURSOR_COEFF_MASK);
> tmp |= POST_CURSOR_1(0x0);
> tmp |= POST_CURSOR_2(0x0);
> tmp |= CURSOR_COEFF(0x3f);
> - I915_WRITE(ICL_PORT_TX_DW4_AUX(port), tmp);
> + I915_WRITE(ICL_PORT_TX_DW4_AUX(phy), tmp);
>
> for (lane = 0; lane <= 3; lane++) {
> /* Bspec: must not use GRP register for write
> */
> - tmp = I915_READ(ICL_PORT_TX_DW4_LN(lane,
> port));
> + tmp = I915_READ(ICL_PORT_TX_DW4_LN(lane, phy));
> tmp &= ~(POST_CURSOR_1_MASK |
> POST_CURSOR_2_MASK |
> CURSOR_COEFF_MASK);
> tmp |= POST_CURSOR_1(0x0);
> tmp |= POST_CURSOR_2(0x0);
> tmp |= CURSOR_COEFF(0x3f);
> - I915_WRITE(ICL_PORT_TX_DW4_LN(lane, port),
> tmp);
> + I915_WRITE(ICL_PORT_TX_DW4_LN(lane, phy), tmp);
> }
> }
> }
> @@ -364,10 +363,10 @@ static void gen11_dsi_power_up_lanes(struct
> intel_encoder *encoder)
> {
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
> - enum port port;
> + enum phy phy;
>
> - for_each_dsi_port(port, intel_dsi->ports)
> - intel_combo_phy_power_up_lanes(dev_priv, port, true,
> + for_each_dsi_phy(phy, intel_dsi->phys)
> + intel_combo_phy_power_up_lanes(dev_priv, phy, true,
> intel_dsi->lane_count,
> false);
> }
>
> @@ -375,46 +374,46 @@ static void
> gen11_dsi_config_phy_lanes_sequence(struct intel_encoder *encoder)
> {
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
> - enum port port;
> + enum phy phy;
> u32 tmp;
> int lane;
>
> /* Step 4b(i) set loadgen select for transmit and aux lanes */
> - for_each_dsi_port(port, intel_dsi->ports) {
> - tmp = I915_READ(ICL_PORT_TX_DW4_AUX(port));
> + for_each_dsi_phy(phy, intel_dsi->phys) {
> + tmp = I915_READ(ICL_PORT_TX_DW4_AUX(phy));
> tmp &= ~LOADGEN_SELECT;
> - I915_WRITE(ICL_PORT_TX_DW4_AUX(port), tmp);
> + I915_WRITE(ICL_PORT_TX_DW4_AUX(phy), tmp);
> for (lane = 0; lane <= 3; lane++) {
> - tmp = I915_READ(ICL_PORT_TX_DW4_LN(lane,
> port));
> + tmp = I915_READ(ICL_PORT_TX_DW4_LN(lane, phy));
> tmp &= ~LOADGEN_SELECT;
> if (lane != 2)
> tmp |= LOADGEN_SELECT;
> - I915_WRITE(ICL_PORT_TX_DW4_LN(lane, port),
> tmp);
> + I915_WRITE(ICL_PORT_TX_DW4_LN(lane, phy), tmp);
> }
> }
>
> /* Step 4b(ii) set latency optimization for transmit and aux
> lanes */
> - for_each_dsi_port(port, intel_dsi->ports) {
> - tmp = I915_READ(ICL_PORT_TX_DW2_AUX(port));
> + for_each_dsi_phy(phy, intel_dsi->phys) {
> + tmp = I915_READ(ICL_PORT_TX_DW2_AUX(phy));
> tmp &= ~FRC_LATENCY_OPTIM_MASK;
> tmp |= FRC_LATENCY_OPTIM_VAL(0x5);
> - I915_WRITE(ICL_PORT_TX_DW2_AUX(port), tmp);
> - tmp = I915_READ(ICL_PORT_TX_DW2_LN0(port));
> + I915_WRITE(ICL_PORT_TX_DW2_AUX(phy), tmp);
> + tmp = I915_READ(ICL_PORT_TX_DW2_LN0(phy));
> tmp &= ~FRC_LATENCY_OPTIM_MASK;
> tmp |= FRC_LATENCY_OPTIM_VAL(0x5);
> - I915_WRITE(ICL_PORT_TX_DW2_GRP(port), tmp);
> + I915_WRITE(ICL_PORT_TX_DW2_GRP(phy), tmp);
>
> /* For EHL set latency optimization for PCS_DW1 lanes
> */
> if (IS_ELKHARTLAKE(dev_priv)) {
> - tmp = I915_READ(ICL_PORT_PCS_DW1_AUX(port));
> + tmp = I915_READ(ICL_PORT_PCS_DW1_AUX(phy));
> tmp &= ~LATENCY_OPTIM_MASK;
> tmp |= LATENCY_OPTIM_VAL(0);
> - I915_WRITE(ICL_PORT_PCS_DW1_AUX(port), tmp);
> + I915_WRITE(ICL_PORT_PCS_DW1_AUX(phy), tmp);
>
> - tmp = I915_READ(ICL_PORT_PCS_DW1_LN0(port));
> + tmp = I915_READ(ICL_PORT_PCS_DW1_LN0(phy));
> tmp &= ~LATENCY_OPTIM_MASK;
> tmp |= LATENCY_OPTIM_VAL(0x1);
> - I915_WRITE(ICL_PORT_PCS_DW1_GRP(port), tmp);
> + I915_WRITE(ICL_PORT_PCS_DW1_GRP(phy), tmp);
> }
> }
>
> @@ -425,16 +424,16 @@ static void
> gen11_dsi_voltage_swing_program_seq(struct intel_encoder *encoder)
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
> u32 tmp;
> - enum port port;
> + enum phy phy;
>
> /* clear common keeper enable bit */
> - for_each_dsi_port(port, intel_dsi->ports) {
> - tmp = I915_READ(ICL_PORT_PCS_DW1_LN0(port));
> + for_each_dsi_phy(phy, intel_dsi->phys) {
> + tmp = I915_READ(ICL_PORT_PCS_DW1_LN0(phy));
> tmp &= ~COMMON_KEEPER_EN;
> - I915_WRITE(ICL_PORT_PCS_DW1_GRP(port), tmp);
> - tmp = I915_READ(ICL_PORT_PCS_DW1_AUX(port));
> + I915_WRITE(ICL_PORT_PCS_DW1_GRP(phy), tmp);
> + tmp = I915_READ(ICL_PORT_PCS_DW1_AUX(phy));
> tmp &= ~COMMON_KEEPER_EN;
> - I915_WRITE(ICL_PORT_PCS_DW1_AUX(port), tmp);
> + I915_WRITE(ICL_PORT_PCS_DW1_AUX(phy), tmp);
> }
>
> /*
> @@ -442,33 +441,33 @@ static void
> gen11_dsi_voltage_swing_program_seq(struct intel_encoder *encoder)
> * Note: loadgen select program is done
> * as part of lane phy sequence configuration
> */
> - for_each_dsi_port(port, intel_dsi->ports) {
> - tmp = I915_READ(ICL_PORT_CL_DW5(port));
> + for_each_dsi_phy(phy, intel_dsi->phys) {
> + tmp = I915_READ(ICL_PORT_CL_DW5(phy));
> tmp |= SUS_CLOCK_CONFIG;
> - I915_WRITE(ICL_PORT_CL_DW5(port), tmp);
> + I915_WRITE(ICL_PORT_CL_DW5(phy), tmp);
> }
>
> /* Clear training enable to change swing values */
> - for_each_dsi_port(port, intel_dsi->ports) {
> - tmp = I915_READ(ICL_PORT_TX_DW5_LN0(port));
> + for_each_dsi_phy(phy, intel_dsi->phys) {
> + tmp = I915_READ(ICL_PORT_TX_DW5_LN0(phy));
> tmp &= ~TX_TRAINING_EN;
> - I915_WRITE(ICL_PORT_TX_DW5_GRP(port), tmp);
> - tmp = I915_READ(ICL_PORT_TX_DW5_AUX(port));
> + I915_WRITE(ICL_PORT_TX_DW5_GRP(phy), tmp);
> + tmp = I915_READ(ICL_PORT_TX_DW5_AUX(phy));
> tmp &= ~TX_TRAINING_EN;
> - I915_WRITE(ICL_PORT_TX_DW5_AUX(port), tmp);
> + I915_WRITE(ICL_PORT_TX_DW5_AUX(phy), tmp);
> }
>
> /* Program swing and de-emphasis */
> dsi_program_swing_and_deemphasis(encoder);
>
> /* Set training enable to trigger update */
> - for_each_dsi_port(port, intel_dsi->ports) {
> - tmp = I915_READ(ICL_PORT_TX_DW5_LN0(port));
> + for_each_dsi_phy(phy, intel_dsi->phys) {
> + tmp = I915_READ(ICL_PORT_TX_DW5_LN0(phy));
> tmp |= TX_TRAINING_EN;
> - I915_WRITE(ICL_PORT_TX_DW5_GRP(port), tmp);
> - tmp = I915_READ(ICL_PORT_TX_DW5_AUX(port));
> + I915_WRITE(ICL_PORT_TX_DW5_GRP(phy), tmp);
> + tmp = I915_READ(ICL_PORT_TX_DW5_AUX(phy));
> tmp |= TX_TRAINING_EN;
> - I915_WRITE(ICL_PORT_TX_DW5_AUX(port), tmp);
> + I915_WRITE(ICL_PORT_TX_DW5_AUX(phy), tmp);
> }
> }
>
> @@ -497,6 +496,7 @@ static void gen11_dsi_setup_dphy_timings(struct
> intel_encoder *encoder)
> struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
> u32 tmp;
> enum port port;
> + enum phy phy;
>
> /* Program T-INIT master registers */
> for_each_dsi_port(port, intel_dsi->ports) {
> @@ -546,10 +546,10 @@ static void gen11_dsi_setup_dphy_timings(struct
> intel_encoder *encoder)
> }
>
> if (IS_ELKHARTLAKE(dev_priv)) {
> - for_each_dsi_port(port, intel_dsi->ports) {
> - tmp = I915_READ(ICL_DPHY_CHKN(port));
> + for_each_dsi_phy(phy, intel_dsi->phys) {
> + tmp = I915_READ(ICL_DPHY_CHKN(phy));
> tmp |= ICL_DPHY_CHKN_AFE_OVER_PPI_STRAP;
> - I915_WRITE(ICL_DPHY_CHKN(port), tmp);
> + I915_WRITE(ICL_DPHY_CHKN(phy), tmp);
> }
> }
> }
> @@ -559,15 +559,12 @@ static void gen11_dsi_gate_clocks(struct
> intel_encoder *encoder)
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
> u32 tmp;
> - enum port port;
> enum phy phy;
>
> mutex_lock(&dev_priv->dpll_lock);
> tmp = I915_READ(DPCLKA_CFGCR0_ICL);
> - for_each_dsi_port(port, intel_dsi->ports) {
> - phy = intel_port_to_phy(dev_priv, port);
> + for_each_dsi_phy(phy, intel_dsi->phys)
> tmp |= ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
> - }
>
> I915_WRITE(DPCLKA_CFGCR0_ICL, tmp);
> mutex_unlock(&dev_priv->dpll_lock);
> @@ -578,15 +575,12 @@ static void gen11_dsi_ungate_clocks(struct
> intel_encoder *encoder)
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
> u32 tmp;
> - enum port port;
> enum phy phy;
>
> mutex_lock(&dev_priv->dpll_lock);
> tmp = I915_READ(DPCLKA_CFGCR0_ICL);
> - for_each_dsi_port(port, intel_dsi->ports) {
> - phy = intel_port_to_phy(dev_priv, port);
> + for_each_dsi_phy(phy, intel_dsi->phys)
> tmp &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
> - }
>
> I915_WRITE(DPCLKA_CFGCR0_ICL, tmp);
> mutex_unlock(&dev_priv->dpll_lock);
> @@ -598,22 +592,19 @@ static void gen11_dsi_map_pll(struct
> intel_encoder *encoder,
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
> struct intel_shared_dpll *pll = crtc_state->shared_dpll;
> - enum port port;
> enum phy phy;
> u32 val;
>
> mutex_lock(&dev_priv->dpll_lock);
>
> val = I915_READ(DPCLKA_CFGCR0_ICL);
> - for_each_dsi_port(port, intel_dsi->ports) {
> - phy = intel_port_to_phy(dev_priv, port);
> + for_each_dsi_phy(phy, intel_dsi->phys) {
> val &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
> val |= ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id,
> phy);
> }
> I915_WRITE(DPCLKA_CFGCR0_ICL, val);
>
> - for_each_dsi_port(port, intel_dsi->ports) {
> - phy = intel_port_to_phy(dev_priv, port);
> + for_each_dsi_phy(phy, intel_dsi->phys) {
> val &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
> }
> I915_WRITE(DPCLKA_CFGCR0_ICL, val);
> diff --git a/drivers/gpu/drm/i915/display/intel_combo_phy.c
> b/drivers/gpu/drm/i915/display/intel_combo_phy.c
> index d3d5244765e6..ac8218a040ab 100644
> --- a/drivers/gpu/drm/i915/display/intel_combo_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_combo_phy.c
> @@ -6,13 +6,13 @@
> #include "intel_combo_phy.h"
> #include "intel_drv.h"
>
> -#define for_each_combo_port(__dev_priv, __port) \
> - for ((__port) = PORT_A; (__port) < I915_MAX_PORTS; (__port)++)
> \
> - for_each_if(intel_port_is_combophy(__dev_priv, __port))
> +#define for_each_combo_phy(__dev_priv, __phy) \
> + for ((__phy) = PHY_A; (__phy) < I915_MAX_PHYS; (__phy)++) \
> + for_each_if(intel_phy_is_combo(__dev_priv, __phy))
>
> -#define for_each_combo_port_reverse(__dev_priv, __port) \
> - for ((__port) = I915_MAX_PORTS; (__port)-- > PORT_A;) \
> - for_each_if(intel_port_is_combophy(__dev_priv, __port))
> +#define for_each_combo_phy_reverse(__dev_priv, __phy) \
> + for ((__phy) = I915_MAX_PHYS; (__phy)-- > PHY_A;) \
> + for_each_if(intel_phy_is_combo(__dev_priv, __phy))
>
> enum {
> PROCMON_0_85V_DOT_0,
> @@ -38,18 +38,17 @@ static const struct cnl_procmon {
> };
>
> /*
> - * CNL has just one set of registers, while ICL has two sets: one
> for port A and
> - * the other for port B. The CNL registers are equivalent to the ICL
> port A
> - * registers, that's why we call the ICL macros even though the
> function has CNL
> - * on its name.
> + * CNL has just one set of registers, while gen11 has a set for each
> combo PHY.
> + * The CNL registers are equivalent to the gen11 PHY A registers,
> that's why we
> + * call the ICL macros even though the function has CNL on its name.
> */
> static const struct cnl_procmon *
> -cnl_get_procmon_ref_values(struct drm_i915_private *dev_priv, enum
> port port)
> +cnl_get_procmon_ref_values(struct drm_i915_private *dev_priv, enum
> phy phy)
> {
> const struct cnl_procmon *procmon;
> u32 val;
>
> - val = I915_READ(ICL_PORT_COMP_DW3(port));
> + val = I915_READ(ICL_PORT_COMP_DW3(phy));
> switch (val & (PROCESS_INFO_MASK | VOLTAGE_INFO_MASK)) {
> default:
> MISSING_CASE(val);
> @@ -75,32 +74,32 @@ cnl_get_procmon_ref_values(struct
> drm_i915_private *dev_priv, enum port port)
> }
>
> static void cnl_set_procmon_ref_values(struct drm_i915_private
> *dev_priv,
> - enum port port)
> + enum phy phy)
> {
> const struct cnl_procmon *procmon;
> u32 val;
>
> - procmon = cnl_get_procmon_ref_values(dev_priv, port);
> + procmon = cnl_get_procmon_ref_values(dev_priv, phy);
>
> - val = I915_READ(ICL_PORT_COMP_DW1(port));
> + val = I915_READ(ICL_PORT_COMP_DW1(phy));
> val &= ~((0xff << 16) | 0xff);
> val |= procmon->dw1;
> - I915_WRITE(ICL_PORT_COMP_DW1(port), val);
> + I915_WRITE(ICL_PORT_COMP_DW1(phy), val);
>
> - I915_WRITE(ICL_PORT_COMP_DW9(port), procmon->dw9);
> - I915_WRITE(ICL_PORT_COMP_DW10(port), procmon->dw10);
> + I915_WRITE(ICL_PORT_COMP_DW9(phy), procmon->dw9);
> + I915_WRITE(ICL_PORT_COMP_DW10(phy), procmon->dw10);
> }
>
> static bool check_phy_reg(struct drm_i915_private *dev_priv,
> - enum port port, i915_reg_t reg, u32 mask,
> + enum phy phy, i915_reg_t reg, u32 mask,
> u32 expected_val)
> {
> u32 val = I915_READ(reg);
>
> if ((val & mask) != expected_val) {
> - DRM_DEBUG_DRIVER("Port %c combo PHY reg %08x state
> mismatch: "
> + DRM_DEBUG_DRIVER("Combo PHY %c reg %08x state mismatch:
> "
> "current %08x mask %08x expected
> %08x\n",
> - port_name(port),
> + phy_name(phy),
> reg.reg, val, mask, expected_val);
> return false;
> }
> @@ -109,18 +108,18 @@ static bool check_phy_reg(struct
> drm_i915_private *dev_priv,
> }
>
> static bool cnl_verify_procmon_ref_values(struct drm_i915_private
> *dev_priv,
> - enum port port)
> + enum phy phy)
> {
> const struct cnl_procmon *procmon;
> bool ret;
>
> - procmon = cnl_get_procmon_ref_values(dev_priv, port);
> + procmon = cnl_get_procmon_ref_values(dev_priv, phy);
>
> - ret = check_phy_reg(dev_priv, port, ICL_PORT_COMP_DW1(port),
> + ret = check_phy_reg(dev_priv, phy, ICL_PORT_COMP_DW1(phy),
> (0xff << 16) | 0xff, procmon->dw1);
> - ret &= check_phy_reg(dev_priv, port, ICL_PORT_COMP_DW9(port),
> + ret &= check_phy_reg(dev_priv, phy, ICL_PORT_COMP_DW9(phy),
> -1U, procmon->dw9);
> - ret &= check_phy_reg(dev_priv, port, ICL_PORT_COMP_DW10(port),
> + ret &= check_phy_reg(dev_priv, phy, ICL_PORT_COMP_DW10(phy),
> -1U, procmon->dw10);
>
> return ret;
> @@ -134,15 +133,15 @@ static bool cnl_combo_phy_enabled(struct
> drm_i915_private *dev_priv)
>
> static bool cnl_combo_phy_verify_state(struct drm_i915_private
> *dev_priv)
> {
> - enum port port = PORT_A;
> + enum phy phy = PHY_A;
> bool ret;
>
> if (!cnl_combo_phy_enabled(dev_priv))
> return false;
>
> - ret = cnl_verify_procmon_ref_values(dev_priv, port);
> + ret = cnl_verify_procmon_ref_values(dev_priv, phy);
>
> - ret &= check_phy_reg(dev_priv, port, CNL_PORT_CL1CM_DW5,
> + ret &= check_phy_reg(dev_priv, phy, CNL_PORT_CL1CM_DW5,
> CL_POWER_DOWN_ENABLE,
> CL_POWER_DOWN_ENABLE);
>
> return ret;
> @@ -157,7 +156,7 @@ static void cnl_combo_phys_init(struct
> drm_i915_private *dev_priv)
> I915_WRITE(CHICKEN_MISC_2, val);
>
> /* Dummy PORT_A to get the correct CNL register from the ICL
> macro */
> - cnl_set_procmon_ref_values(dev_priv, PORT_A);
> + cnl_set_procmon_ref_values(dev_priv, PHY_A);
>
> val = I915_READ(CNL_PORT_COMP_DW0);
> val |= COMP_INIT;
> @@ -181,39 +180,39 @@ static void cnl_combo_phys_uninit(struct
> drm_i915_private *dev_priv)
> }
>
> static bool icl_combo_phy_enabled(struct drm_i915_private *dev_priv,
> - enum port port)
> + enum phy phy)
> {
> /* The PHY C added by EHL has no PHY_MISC register */
> - if (IS_ELKHARTLAKE(dev_priv) && port == PORT_C)
> - return I915_READ(ICL_PORT_COMP_DW0(port)) & COMP_INIT;
> + if (IS_ELKHARTLAKE(dev_priv) && phy == PHY_C)
> + return I915_READ(ICL_PORT_COMP_DW0(phy)) & COMP_INIT;
> else
> - return !(I915_READ(ICL_PHY_MISC(port)) &
> + return !(I915_READ(ICL_PHY_MISC(phy)) &
> ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN) &&
> - (I915_READ(ICL_PORT_COMP_DW0(port)) &
> COMP_INIT);
> + (I915_READ(ICL_PORT_COMP_DW0(phy)) &
> COMP_INIT);
> }
>
> static bool icl_combo_phy_verify_state(struct drm_i915_private
> *dev_priv,
> - enum port port)
> + enum phy phy)
> {
> bool ret;
>
> - if (!icl_combo_phy_enabled(dev_priv, port))
> + if (!icl_combo_phy_enabled(dev_priv, phy))
> return false;
>
> - ret = cnl_verify_procmon_ref_values(dev_priv, port);
> + ret = cnl_verify_procmon_ref_values(dev_priv, phy);
>
> - if (port == PORT_A)
> - ret &= check_phy_reg(dev_priv, port,
> ICL_PORT_COMP_DW8(port),
> + if (phy == PHY_A)
> + ret &= check_phy_reg(dev_priv, phy,
> ICL_PORT_COMP_DW8(phy),
> IREFGEN, IREFGEN);
>
> - ret &= check_phy_reg(dev_priv, port, ICL_PORT_CL_DW5(port),
> + ret &= check_phy_reg(dev_priv, phy, ICL_PORT_CL_DW5(phy),
> CL_POWER_DOWN_ENABLE,
> CL_POWER_DOWN_ENABLE);
>
> return ret;
> }
>
> void intel_combo_phy_power_up_lanes(struct drm_i915_private
> *dev_priv,
> - enum port port, bool is_dsi,
> + enum phy phy, bool is_dsi,
> int lane_count, bool lane_reversal)
> {
> u8 lane_mask;
> @@ -258,10 +257,10 @@ void intel_combo_phy_power_up_lanes(struct
> drm_i915_private *dev_priv,
> }
> }
>
> - val = I915_READ(ICL_PORT_CL_DW10(port));
> + val = I915_READ(ICL_PORT_CL_DW10(phy));
> val &= ~PWR_DOWN_LN_MASK;
> val |= lane_mask << PWR_DOWN_LN_SHIFT;
> - I915_WRITE(ICL_PORT_CL_DW10(port), val);
> + I915_WRITE(ICL_PORT_CL_DW10(phy), val);
> }
>
> static u32 ehl_combo_phy_a_mux(struct drm_i915_private *i915, u32
> val)
> @@ -292,14 +291,14 @@ static u32 ehl_combo_phy_a_mux(struct
> drm_i915_private *i915, u32 val)
>
> static void icl_combo_phys_init(struct drm_i915_private *dev_priv)
> {
> - enum port port;
> + enum phy phy;
>
> - for_each_combo_port(dev_priv, port) {
> + for_each_combo_phy(dev_priv, phy) {
> u32 val;
>
> - if (icl_combo_phy_verify_state(dev_priv, port)) {
> - DRM_DEBUG_DRIVER("Port %c combo PHY already
> enabled, won't reprogram it.\n",
> - port_name(port));
> + if (icl_combo_phy_verify_state(dev_priv, phy)) {
> + DRM_DEBUG_DRIVER("Combo PHY %c already enabled,
> won't reprogram it.\n",
> + phy_name(phy));
> continue;
> }
>
> @@ -308,7 +307,7 @@ static void icl_combo_phys_init(struct
> drm_i915_private *dev_priv)
> * register for it and no need to program the
> * DE_IO_COMP_PWR_DOWN setting on PHY C.
> */
> - if (IS_ELKHARTLAKE(dev_priv) && port == PORT_C)
> + if (IS_ELKHARTLAKE(dev_priv) && phy == PHY_C)
> goto skip_phy_misc;
>
> /*
> @@ -319,59 +318,59 @@ static void icl_combo_phys_init(struct
> drm_i915_private *dev_priv)
> * based on whether our VBT indicates the presence of
> any
> * "internal" child devices.
> */
> - val = I915_READ(ICL_PHY_MISC(port));
> - if (IS_ELKHARTLAKE(dev_priv) && port == PORT_A)
> + val = I915_READ(ICL_PHY_MISC(phy));
> + if (IS_ELKHARTLAKE(dev_priv) && phy == PHY_A)
> val = ehl_combo_phy_a_mux(dev_priv, val);
> val &= ~ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN;
> - I915_WRITE(ICL_PHY_MISC(port), val);
> + I915_WRITE(ICL_PHY_MISC(phy), val);
>
> skip_phy_misc:
> - cnl_set_procmon_ref_values(dev_priv, port);
> + cnl_set_procmon_ref_values(dev_priv, phy);
>
> - if (port == PORT_A) {
> - val = I915_READ(ICL_PORT_COMP_DW8(port));
> + if (phy == PHY_A) {
> + val = I915_READ(ICL_PORT_COMP_DW8(phy));
> val |= IREFGEN;
> - I915_WRITE(ICL_PORT_COMP_DW8(port), val);
> + I915_WRITE(ICL_PORT_COMP_DW8(phy), val);
> }
>
> - val = I915_READ(ICL_PORT_COMP_DW0(port));
> + val = I915_READ(ICL_PORT_COMP_DW0(phy));
> val |= COMP_INIT;
> - I915_WRITE(ICL_PORT_COMP_DW0(port), val);
> + I915_WRITE(ICL_PORT_COMP_DW0(phy), val);
>
> - val = I915_READ(ICL_PORT_CL_DW5(port));
> + val = I915_READ(ICL_PORT_CL_DW5(phy));
> val |= CL_POWER_DOWN_ENABLE;
> - I915_WRITE(ICL_PORT_CL_DW5(port), val);
> + I915_WRITE(ICL_PORT_CL_DW5(phy), val);
> }
> }
>
> static void icl_combo_phys_uninit(struct drm_i915_private *dev_priv)
> {
> - enum port port;
> + enum phy phy;
>
> - for_each_combo_port_reverse(dev_priv, port) {
> + for_each_combo_phy_reverse(dev_priv, phy) {
> u32 val;
>
> - if (port == PORT_A &&
> - !icl_combo_phy_verify_state(dev_priv, port))
> - DRM_WARN("Port %c combo PHY HW state changed
> unexpectedly\n",
> - port_name(port));
> + if (phy == PHY_A &&
> + !icl_combo_phy_verify_state(dev_priv, phy))
> + DRM_WARN("Combo PHY %c HW state changed
> unexpectedly\n",
> + phy_name(phy));
>
> /*
> * Although EHL adds a combo PHY C, there's no PHY_MISC
> * register for it and no need to program the
> * DE_IO_COMP_PWR_DOWN setting on PHY C.
> */
> - if (IS_ELKHARTLAKE(dev_priv) && port == PORT_C)
> + if (IS_ELKHARTLAKE(dev_priv) && phy == PHY_C)
> goto skip_phy_misc;
>
> - val = I915_READ(ICL_PHY_MISC(port));
> + val = I915_READ(ICL_PHY_MISC(phy));
> val |= ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN;
> - I915_WRITE(ICL_PHY_MISC(port), val);
> + I915_WRITE(ICL_PHY_MISC(phy), val);
>
> skip_phy_misc:
> - val = I915_READ(ICL_PORT_COMP_DW0(port));
> + val = I915_READ(ICL_PORT_COMP_DW0(phy));
> val &= ~COMP_INIT;
> - I915_WRITE(ICL_PORT_COMP_DW0(port), val);
> + I915_WRITE(ICL_PORT_COMP_DW0(phy), val);
> }
> }
>
> diff --git a/drivers/gpu/drm/i915/display/intel_combo_phy.h
> b/drivers/gpu/drm/i915/display/intel_combo_phy.h
> index e6e195a83b19..80a1386b4c87 100644
> --- a/drivers/gpu/drm/i915/display/intel_combo_phy.h
> +++ b/drivers/gpu/drm/i915/display/intel_combo_phy.h
> @@ -10,11 +10,12 @@
> #include <drm/i915_drm.h>
Nit: This include can be removed as it was here only to get the
definition of enum port.
Other than that look good, I did not found any other register missing
conversion.
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
>
> struct drm_i915_private;
> +enum phy;
>
> void intel_combo_phy_init(struct drm_i915_private *dev_priv);
> void intel_combo_phy_uninit(struct drm_i915_private *dev_priv);
> void intel_combo_phy_power_up_lanes(struct drm_i915_private
> *dev_priv,
> - enum port port, bool is_dsi,
> + enum phy phy, bool is_dsi,
> int lane_count, bool
> lane_reversal);
>
> #endif /* __INTEL_COMBO_PHY_H__ */
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> b/drivers/gpu/drm/i915/display/intel_ddi.c
> index a40a53527d99..50dd9d731456 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -2414,7 +2414,7 @@ static void cnl_ddi_vswing_sequence(struct
> intel_encoder *encoder,
> }
>
> static void icl_ddi_combo_vswing_program(struct drm_i915_private
> *dev_priv,
> - u32 level, enum port port, int
> type,
> + u32 level, enum phy phy, int
> type,
> int rate)
> {
> const struct cnl_ddi_buf_trans *ddi_translations = NULL;
> @@ -2432,41 +2432,41 @@ static void
> icl_ddi_combo_vswing_program(struct drm_i915_private *dev_priv,
> }
>
> /* Set PORT_TX_DW5 */
> - val = I915_READ(ICL_PORT_TX_DW5_LN0(port));
> + val = I915_READ(ICL_PORT_TX_DW5_LN0(phy));
> val &= ~(SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK |
> TAP2_DISABLE | TAP3_DISABLE);
> val |= SCALING_MODE_SEL(0x2);
> val |= RTERM_SELECT(0x6);
> val |= TAP3_DISABLE;
> - I915_WRITE(ICL_PORT_TX_DW5_GRP(port), val);
> + I915_WRITE(ICL_PORT_TX_DW5_GRP(phy), val);
>
> /* Program PORT_TX_DW2 */
> - val = I915_READ(ICL_PORT_TX_DW2_LN0(port));
> + val = I915_READ(ICL_PORT_TX_DW2_LN0(phy));
> val &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK |
> RCOMP_SCALAR_MASK);
> val |= SWING_SEL_UPPER(ddi_translations[level].dw2_swing_sel);
> val |= SWING_SEL_LOWER(ddi_translations[level].dw2_swing_sel);
> /* Program Rcomp scalar for every table entry */
> val |= RCOMP_SCALAR(0x98);
> - I915_WRITE(ICL_PORT_TX_DW2_GRP(port), val);
> + I915_WRITE(ICL_PORT_TX_DW2_GRP(phy), val);
>
> /* Program PORT_TX_DW4 */
> /* We cannot write to GRP. It would overwrite individual
> loadgen. */
> for (ln = 0; ln <= 3; ln++) {
> - val = I915_READ(ICL_PORT_TX_DW4_LN(ln, port));
> + val = I915_READ(ICL_PORT_TX_DW4_LN(ln, phy));
> val &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK |
> CURSOR_COEFF_MASK);
> val |=
> POST_CURSOR_1(ddi_translations[level].dw4_post_cursor_1);
> val |=
> POST_CURSOR_2(ddi_translations[level].dw4_post_cursor_2);
> val |=
> CURSOR_COEFF(ddi_translations[level].dw4_cursor_coeff);
> - I915_WRITE(ICL_PORT_TX_DW4_LN(ln, port), val);
> + I915_WRITE(ICL_PORT_TX_DW4_LN(ln, phy), val);
> }
>
> /* Program PORT_TX_DW7 */
> - val = I915_READ(ICL_PORT_TX_DW7_LN0(port));
> + val = I915_READ(ICL_PORT_TX_DW7_LN0(phy));
> val &= ~N_SCALAR_MASK;
> val |= N_SCALAR(ddi_translations[level].dw7_n_scalar);
> - I915_WRITE(ICL_PORT_TX_DW7_GRP(port), val);
> + I915_WRITE(ICL_PORT_TX_DW7_GRP(phy), val);
> }
>
> static void icl_combo_phy_ddi_vswing_sequence(struct intel_encoder
> *encoder,
> @@ -2474,7 +2474,7 @@ static void
> icl_combo_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
> enum intel_output_type
> type)
> {
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> - enum port port = encoder->port;
> + enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
> int width = 0;
> int rate = 0;
> u32 val;
> @@ -2495,12 +2495,12 @@ static void
> icl_combo_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
> * set PORT_PCS_DW1 cmnkeeper_enable to 1b,
> * else clear to 0b.
> */
> - val = I915_READ(ICL_PORT_PCS_DW1_LN0(port));
> + val = I915_READ(ICL_PORT_PCS_DW1_LN0(phy));
> if (type == INTEL_OUTPUT_HDMI)
> val &= ~COMMON_KEEPER_EN;
> else
> val |= COMMON_KEEPER_EN;
> - I915_WRITE(ICL_PORT_PCS_DW1_GRP(port), val);
> + I915_WRITE(ICL_PORT_PCS_DW1_GRP(phy), val);
>
> /* 2. Program loadgen select */
> /*
> @@ -2510,33 +2510,33 @@ static void
> icl_combo_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
> * > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0)
> */
> for (ln = 0; ln <= 3; ln++) {
> - val = I915_READ(ICL_PORT_TX_DW4_LN(ln, port));
> + val = I915_READ(ICL_PORT_TX_DW4_LN(ln, phy));
> val &= ~LOADGEN_SELECT;
>
> if ((rate <= 600000 && width == 4 && ln >= 1) ||
> (rate <= 600000 && width < 4 && (ln == 1 || ln ==
> 2))) {
> val |= LOADGEN_SELECT;
> }
> - I915_WRITE(ICL_PORT_TX_DW4_LN(ln, port), val);
> + I915_WRITE(ICL_PORT_TX_DW4_LN(ln, phy), val);
> }
>
> /* 3. Set PORT_CL_DW5 SUS Clock Config to 11b */
> - val = I915_READ(ICL_PORT_CL_DW5(port));
> + val = I915_READ(ICL_PORT_CL_DW5(phy));
> val |= SUS_CLOCK_CONFIG;
> - I915_WRITE(ICL_PORT_CL_DW5(port), val);
> + I915_WRITE(ICL_PORT_CL_DW5(phy), val);
>
> /* 4. Clear training enable to change swing values */
> - val = I915_READ(ICL_PORT_TX_DW5_LN0(port));
> + val = I915_READ(ICL_PORT_TX_DW5_LN0(phy));
> val &= ~TX_TRAINING_EN;
> - I915_WRITE(ICL_PORT_TX_DW5_GRP(port), val);
> + I915_WRITE(ICL_PORT_TX_DW5_GRP(phy), val);
>
> /* 5. Program swing and de-emphasis */
> - icl_ddi_combo_vswing_program(dev_priv, level, port, type,
> rate);
> + icl_ddi_combo_vswing_program(dev_priv, level, phy, type, rate);
>
> /* 6. Set training enable to trigger update */
> - val = I915_READ(ICL_PORT_TX_DW5_LN0(port));
> + val = I915_READ(ICL_PORT_TX_DW5_LN0(phy));
> val |= TX_TRAINING_EN;
> - I915_WRITE(ICL_PORT_TX_DW5_GRP(port), val);
> + I915_WRITE(ICL_PORT_TX_DW5_GRP(phy), val);
> }
>
> static void icl_mg_phy_ddi_vswing_sequence(struct intel_encoder
> *encoder,
> @@ -3120,6 +3120,7 @@ static void intel_ddi_pre_enable_dp(struct
> intel_encoder *encoder,
> struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> enum port port = encoder->port;
> + enum phy phy = intel_port_to_phy(dev_priv, port);
> struct intel_digital_port *dig_port = enc_to_dig_port(&encoder-
> >base);
> bool is_mst = intel_crtc_has_type(crtc_state,
> INTEL_OUTPUT_DP_MST);
> int level = intel_ddi_dp_level(intel_dp);
> @@ -3155,7 +3156,7 @@ static void intel_ddi_pre_enable_dp(struct
> intel_encoder *encoder,
> bool lane_reversal =
> dig_port->saved_port_bits &
> DDI_BUF_PORT_REVERSAL;
>
> - intel_combo_phy_power_up_lanes(dev_priv, port, false,
> + intel_combo_phy_power_up_lanes(dev_priv, phy, false,
> crtc_state->lane_count,
> lane_reversal);
> }
> diff --git a/drivers/gpu/drm/i915/display/intel_display.h
> b/drivers/gpu/drm/i915/display/intel_display.h
> index d53285fb883f..8a4a57ef82a2 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.h
> +++ b/drivers/gpu/drm/i915/display/intel_display.h
> @@ -268,6 +268,10 @@ enum phy {
> for ((__port) = PORT_A; (__port) < I915_MAX_PORTS; (__port)++)
> \
> for_each_if((__ports_mask) & BIT(__port))
>
> +#define for_each_phy_masked(__phy, __phys_mask) \
> + for ((__phy) = PHY_A; (__phy) < I915_MAX_PHYS; (__phy)++) \
> + for_each_if((__phys_mask) & BIT(__phy))
> +
> #define for_each_crtc(dev, crtc) \
> list_for_each_entry(crtc, &(dev)->mode_config.crtc_list, head)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
> b/drivers/gpu/drm/i915/display/intel_display_power.c
> index c19b958461ca..64627c117c31 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> @@ -395,7 +395,7 @@ static void hsw_power_well_disable(struct
> drm_i915_private *dev_priv,
> hsw_wait_for_power_well_disable(dev_priv, power_well);
> }
>
> -#define ICL_AUX_PW_TO_PORT(pw_idx) ((pw_idx) -
> ICL_PW_CTL_IDX_AUX_A)
> +#define ICL_AUX_PW_TO_PHY(pw_idx) ((pw_idx) -
> ICL_PW_CTL_IDX_AUX_A)
>
> static void
> icl_combo_phy_aux_power_well_enable(struct drm_i915_private
> *dev_priv,
> @@ -403,21 +403,21 @@ icl_combo_phy_aux_power_well_enable(struct
> drm_i915_private *dev_priv,
> {
> const struct i915_power_well_regs *regs = power_well->desc-
> >hsw.regs;
> int pw_idx = power_well->desc->hsw.idx;
> - enum port port = ICL_AUX_PW_TO_PORT(pw_idx);
> + enum phy phy = ICL_AUX_PW_TO_PHY(pw_idx);
> u32 val;
>
> val = I915_READ(regs->driver);
> I915_WRITE(regs->driver, val | HSW_PWR_WELL_CTL_REQ(pw_idx));
>
> - val = I915_READ(ICL_PORT_CL_DW12(port));
> - I915_WRITE(ICL_PORT_CL_DW12(port), val | ICL_LANE_ENABLE_AUX);
> + val = I915_READ(ICL_PORT_CL_DW12(phy));
> + I915_WRITE(ICL_PORT_CL_DW12(phy), val | ICL_LANE_ENABLE_AUX);
>
> hsw_wait_for_power_well_enable(dev_priv, power_well);
>
> /* Display WA #1178: icl */
> if (IS_ICELAKE(dev_priv) &&
> pw_idx >= ICL_PW_CTL_IDX_AUX_A && pw_idx <=
> ICL_PW_CTL_IDX_AUX_B &&
> - !intel_bios_is_port_edp(dev_priv, port)) {
> + !intel_bios_is_port_edp(dev_priv, (enum port)phy)) {
> val = I915_READ(ICL_AUX_ANAOVRD1(pw_idx));
> val |= ICL_AUX_ANAOVRD1_ENABLE |
> ICL_AUX_ANAOVRD1_LDO_BYPASS;
> I915_WRITE(ICL_AUX_ANAOVRD1(pw_idx), val);
> @@ -430,11 +430,11 @@ icl_combo_phy_aux_power_well_disable(struct
> drm_i915_private *dev_priv,
> {
> const struct i915_power_well_regs *regs = power_well->desc-
> >hsw.regs;
> int pw_idx = power_well->desc->hsw.idx;
> - enum port port = ICL_AUX_PW_TO_PORT(pw_idx);
> + enum phy phy = ICL_AUX_PW_TO_PHY(pw_idx);
> u32 val;
>
> - val = I915_READ(ICL_PORT_CL_DW12(port));
> - I915_WRITE(ICL_PORT_CL_DW12(port), val & ~ICL_LANE_ENABLE_AUX);
> + val = I915_READ(ICL_PORT_CL_DW12(phy));
> + I915_WRITE(ICL_PORT_CL_DW12(phy), val & ~ICL_LANE_ENABLE_AUX);
>
> val = I915_READ(regs->driver);
> I915_WRITE(regs->driver, val & ~HSW_PWR_WELL_CTL_REQ(pw_idx));
> diff --git a/drivers/gpu/drm/i915/display/intel_dsi.h
> b/drivers/gpu/drm/i915/display/intel_dsi.h
> index 6d20434636cd..1cd24bd46518 100644
> --- a/drivers/gpu/drm/i915/display/intel_dsi.h
> +++ b/drivers/gpu/drm/i915/display/intel_dsi.h
> @@ -49,8 +49,11 @@ struct intel_dsi {
>
> struct intel_connector *attached_connector;
>
> - /* bit mask of ports being driven */
> - u16 ports;
> + /* bit mask of ports (vlv dsi) or phys (icl dsi) being driven
> */
> + union {
> + u16 ports; /* VLV DSI */
> + u16 phys; /* ICL DSI */
> + };
>
> /* if true, use HS mode, otherwise LP */
> bool hs;
> @@ -132,7 +135,10 @@ static inline struct intel_dsi_host
> *to_intel_dsi_host(struct mipi_dsi_host *h)
> return container_of(h, struct intel_dsi_host, base);
> }
>
> -#define for_each_dsi_port(__port, __ports_mask)
> for_each_port_masked(__port, __ports_mask)
> +#define for_each_dsi_port(__port, __ports_mask) \
> + for_each_port_masked(__port, __ports_mask)
> +#define for_each_dsi_phy(__phy, __phys_mask) \
> + for_each_phy_masked(__phy, __phys_mask)
>
> static inline struct intel_dsi *enc_to_intel_dsi(struct drm_encoder
> *encoder)
> {
> diff --git a/drivers/gpu/drm/i915/i915_reg.h
> b/drivers/gpu/drm/i915/i915_reg.h
> index c9e2e09b6f01..b766ba22045b 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1794,20 +1794,20 @@ enum i915_power_well_id {
> #define _ICL_COMBOPHY_A 0x162000
> #define _ICL_COMBOPHY_B 0x6C000
> #define _EHL_COMBOPHY_C 0x160000
> -#define _ICL_COMBOPHY(port) _PICK(port, _ICL_COMBOPHY_A, \
> +#define _ICL_COMBOPHY(phy) _PICK(phy, _ICL_COMBOPHY_A, \
> _ICL_COMBOPHY_B, \
> _EHL_COMBOPHY_C)
>
> /* CNL/ICL Port CL_DW registers */
> -#define _ICL_PORT_CL_DW(dw, port) (_ICL_COMBOPHY(port) + \
> +#define _ICL_PORT_CL_DW(dw, phy) (_ICL_COMBOPHY(phy) + \
> 4 * (dw))
>
> #define CNL_PORT_CL1CM_DW5 _MMIO(0x162014)
> -#define ICL_PORT_CL_DW5(port) _MMIO(_ICL_PORT_CL_DW(5
> , port))
> +#define ICL_PORT_CL_DW5(phy) _MMIO(_ICL_PORT_CL_DW(5, phy))
> #define CL_POWER_DOWN_ENABLE (1 << 4)
> #define SUS_CLOCK_CONFIG (3 << 0)
>
> -#define ICL_PORT_CL_DW10(port) _MMIO(_ICL_PORT_CL_DW(1
> 0, port))
> +#define ICL_PORT_CL_DW10(phy) _MMIO(_ICL_PORT_CL_DW(1
> 0, phy))
> #define PG_SEQ_DELAY_OVERRIDE_MASK (3 << 25)
> #define PG_SEQ_DELAY_OVERRIDE_SHIFT 25
> #define PG_SEQ_DELAY_OVERRIDE_ENABLE (1 << 24)
> @@ -1822,23 +1822,23 @@ enum i915_power_well_id {
> #define PWR_DOWN_LN_MASK (0xf << 4)
> #define PWR_DOWN_LN_SHIFT 4
>
> -#define ICL_PORT_CL_DW12(port) _MMIO(_ICL_PORT_CL_DW(1
> 2, port))
> +#define ICL_PORT_CL_DW12(phy) _MMIO(_ICL_PORT_CL_DW(1
> 2, phy))
> #define ICL_LANE_ENABLE_AUX (1 << 0)
>
> /* CNL/ICL Port COMP_DW registers */
> #define _ICL_PORT_COMP 0x100
> -#define _ICL_PORT_COMP_DW(dw, port) (_ICL_COMBOPHY(port) + \
> +#define _ICL_PORT_COMP_DW(dw, phy) (_ICL_COMBOPHY(phy) + \
> _ICL_PORT_COMP + 4 * (dw))
>
> #define CNL_PORT_COMP_DW0 _MMIO(0x162100)
> -#define ICL_PORT_COMP_DW0(port) _MMIO(_ICL_PORT_COMP_DW
> (0, port))
> +#define ICL_PORT_COMP_DW0(phy) _MMIO(_ICL_PORT_COMP_DW
> (0, phy))
> #define COMP_INIT (1 << 31)
>
> #define CNL_PORT_COMP_DW1 _MMIO(0x162104)
> -#define ICL_PORT_COMP_DW1(port) _MMIO(_ICL_PORT_COMP_DW
> (1, port))
> +#define ICL_PORT_COMP_DW1(phy) _MMIO(_ICL_PORT_COMP_DW
> (1, phy))
>
> #define CNL_PORT_COMP_DW3 _MMIO(0x16210c)
> -#define ICL_PORT_COMP_DW3(port) _MMIO(_ICL_PORT_COMP_DW
> (3, port))
> +#define ICL_PORT_COMP_DW3(phy) _MMIO(_ICL_PORT_COMP_DW
> (3, phy))
> #define PROCESS_INFO_DOT_0 (0 << 26)
> #define PROCESS_INFO_DOT_1 (1 << 26)
> #define PROCESS_INFO_DOT_4 (2 << 26)
> @@ -1850,14 +1850,14 @@ enum i915_power_well_id {
> #define VOLTAGE_INFO_MASK (3 << 24)
> #define VOLTAGE_INFO_SHIFT 24
>
> -#define ICL_PORT_COMP_DW8(port) _MMIO(_ICL_PORT_COMP_DW
> (8, port))
> +#define ICL_PORT_COMP_DW8(phy) _MMIO(_ICL_PORT_COMP_DW
> (8, phy))
> #define IREFGEN (1 << 24)
>
> #define CNL_PORT_COMP_DW9 _MMIO(0x162124)
> -#define ICL_PORT_COMP_DW9(port) _MMIO(_ICL_PORT_COMP_DW
> (9, port))
> +#define ICL_PORT_COMP_DW9(phy) _MMIO(_ICL_PORT_COMP_DW
> (9, phy))
>
> #define CNL_PORT_COMP_DW10 _MMIO(0x162128)
> -#define ICL_PORT_COMP_DW10(port) _MMIO(_ICL_PORT_COMP_DW(10,
> port))
> +#define ICL_PORT_COMP_DW10(phy) _MMIO(_ICL_PORT_COMP_DW
> (10, phy))
>
> /* CNL/ICL Port PCS registers */
> #define _CNL_PORT_PCS_DW1_GRP_AE 0x162304
> @@ -1870,14 +1870,14 @@ enum i915_power_well_id {
> #define _CNL_PORT_PCS_DW1_LN0_C 0x162C04
> #define _CNL_PORT_PCS_DW1_LN0_D 0x162E04
> #define _CNL_PORT_PCS_DW1_LN0_F 0x162804
> -#define CNL_PORT_PCS_DW1_GRP(port) _MMIO(_PICK(port, \
> +#define CNL_PORT_PCS_DW1_GRP(phy) _MMIO(_PICK(phy, \
> _CNL_PORT_PCS_DW1_G
> RP_AE, \
> _CNL_PORT_PCS_DW1_G
> RP_B, \
> _CNL_PORT_PCS_DW1_G
> RP_C, \
> _CNL_PORT_PCS_DW1_G
> RP_D, \
> _CNL_PORT_PCS_DW1_G
> RP_AE, \
> _CNL_PORT_PCS_DW1_G
> RP_F))
> -#define CNL_PORT_PCS_DW1_LN0(port) _MMIO(_PICK(port, \
> +#define CNL_PORT_PCS_DW1_LN0(phy) _MMIO(_PICK(phy, \
> _CNL_PORT_PCS_DW1_L
> N0_AE, \
> _CNL_PORT_PCS_DW1_L
> N0_B, \
> _CNL_PORT_PCS_DW1_L
> N0_C, \
> @@ -1888,15 +1888,15 @@ enum i915_power_well_id {
> #define _ICL_PORT_PCS_AUX 0x300
> #define _ICL_PORT_PCS_GRP 0x600
> #define _ICL_PORT_PCS_LN(ln) (0x800 + (ln) * 0x100)
> -#define _ICL_PORT_PCS_DW_AUX(dw, port) (_ICL_COMBOPHY(port) +
> \
> +#define _ICL_PORT_PCS_DW_AUX(dw, phy) (_ICL_COMBOPHY(phy) + \
> _ICL_PORT_PCS_AUX + 4 * (dw))
> -#define _ICL_PORT_PCS_DW_GRP(dw, port) (_ICL_COMBOPHY(port) +
> \
> +#define _ICL_PORT_PCS_DW_GRP(dw, phy) (_ICL_COMBOPHY(phy) + \
> _ICL_PORT_PCS_GRP + 4 * (dw))
> -#define _ICL_PORT_PCS_DW_LN(dw, ln, port) (_ICL_COMBOPHY(port) + \
> +#define _ICL_PORT_PCS_DW_LN(dw, ln, phy) (_ICL_COMBOPHY(phy) + \
> _ICL_PORT_PCS_LN(ln) + 4 *
> (dw))
> -#define ICL_PORT_PCS_DW1_AUX(port) _MMIO(_ICL_PORT_PCS_DW_AUX(1,
> port))
> -#define ICL_PORT_PCS_DW1_GRP(port) _MMIO(_ICL_PORT_PCS_DW_GRP(1,
> port))
> -#define ICL_PORT_PCS_DW1_LN0(port) _MMIO(_ICL_PORT_PCS_DW_LN(1, 0,
> port))
> +#define ICL_PORT_PCS_DW1_AUX(phy) _MMIO(_ICL_PORT_PCS_DW_AUX(1,
> phy))
> +#define ICL_PORT_PCS_DW1_GRP(phy) _MMIO(_ICL_PORT_PCS_DW_GRP(1,
> phy))
> +#define ICL_PORT_PCS_DW1_LN0(phy) _MMIO(_ICL_PORT_PCS_DW_LN(1, 0,
> phy))
> #define COMMON_KEEPER_EN (1 << 26)
> #define LATENCY_OPTIM_MASK (0x3 << 2)
> #define LATENCY_OPTIM_VAL(x) ((x) << 2)
> @@ -1933,18 +1933,18 @@ enum i915_power_well_id {
> #define _ICL_PORT_TX_GRP 0x680
> #define _ICL_PORT_TX_LN(ln) (0x880 + (ln) * 0x100)
>
> -#define _ICL_PORT_TX_DW_AUX(dw, port) (_ICL_COMBOPHY(port) +
> \
> +#define _ICL_PORT_TX_DW_AUX(dw, phy) (_ICL_COMBOPHY(phy) + \
> _ICL_PORT_TX_AUX + 4 * (dw))
> -#define _ICL_PORT_TX_DW_GRP(dw, port) (_ICL_COMBOPHY(port) +
> \
> +#define _ICL_PORT_TX_DW_GRP(dw, phy) (_ICL_COMBOPHY(phy) + \
> _ICL_PORT_TX_GRP + 4 * (dw))
> -#define _ICL_PORT_TX_DW_LN(dw, ln, port) (_ICL_COMBOPHY(port) + \
> +#define _ICL_PORT_TX_DW_LN(dw, ln, phy) (_ICL_COMBOPHY(phy) + \
> _ICL_PORT_TX_LN(ln) + 4 *
> (dw))
>
> #define CNL_PORT_TX_DW2_GRP(port) _MMIO(_CNL_PORT_TX_DW_GRP(2,
> port))
> #define CNL_PORT_TX_DW2_LN0(port) _MMIO(_CNL_PORT_TX_DW_LN0(2,
> port))
> -#define ICL_PORT_TX_DW2_AUX(port) _MMIO(_ICL_PORT_TX_DW_AUX(2,
> port))
> -#define ICL_PORT_TX_DW2_GRP(port) _MMIO(_ICL_PORT_TX_DW_GRP(2,
> port))
> -#define ICL_PORT_TX_DW2_LN0(port) _MMIO(_ICL_PORT_TX_DW_LN(2, 0,
> port))
> +#define ICL_PORT_TX_DW2_AUX(phy) _MMIO(_ICL_PORT_TX_DW_AUX(2,
> phy))
> +#define ICL_PORT_TX_DW2_GRP(phy) _MMIO(_ICL_PORT_TX_DW_GRP(2,
> phy))
> +#define ICL_PORT_TX_DW2_LN0(phy) _MMIO(_ICL_PORT_TX_DW_LN(2, 0,
> phy))
> #define SWING_SEL_UPPER(x) (((x) >> 3) << 15)
> #define SWING_SEL_UPPER_MASK (1 << 15)
> #define SWING_SEL_LOWER(x) (((x) & 0x7) << 11)
> @@ -1961,10 +1961,10 @@ enum i915_power_well_id {
> #define CNL_PORT_TX_DW4_LN(ln, port) _MMIO(_CNL_PORT_TX_DW_LN0(4,
> (port)) + \
> ((ln) *
> (_CNL_PORT_TX_DW4_LN1_AE - \
> _CNL_PORT_TX_DW4_LN
> 0_AE)))
> -#define ICL_PORT_TX_DW4_AUX(port) _MMIO(_ICL_PORT_TX_DW_AUX(4,
> port))
> -#define ICL_PORT_TX_DW4_GRP(port) _MMIO(_ICL_PORT_TX_DW_GRP(4,
> port))
> -#define ICL_PORT_TX_DW4_LN0(port) _MMIO(_ICL_PORT_TX_DW_LN(4, 0,
> port))
> -#define ICL_PORT_TX_DW4_LN(ln, port) _MMIO(_ICL_PORT_TX_DW_LN(4, ln,
> port))
> +#define ICL_PORT_TX_DW4_AUX(phy) _MMIO(_ICL_PORT_TX_DW_AUX(4,
> phy))
> +#define ICL_PORT_TX_DW4_GRP(phy) _MMIO(_ICL_PORT_TX_DW_GRP(4,
> phy))
> +#define ICL_PORT_TX_DW4_LN0(phy) _MMIO(_ICL_PORT_TX_DW_LN(4, 0,
> phy))
> +#define ICL_PORT_TX_DW4_LN(ln, phy) _MMIO(_ICL_PORT_TX_DW_LN(4, ln,
> phy))
> #define LOADGEN_SELECT (1 << 31)
> #define POST_CURSOR_1(x) ((x) << 12)
> #define POST_CURSOR_1_MASK (0x3F << 12)
> @@ -1975,9 +1975,9 @@ enum i915_power_well_id {
>
> #define CNL_PORT_TX_DW5_GRP(port) _MMIO(_CNL_PORT_TX_DW_GRP(5,
> port))
> #define CNL_PORT_TX_DW5_LN0(port) _MMIO(_CNL_PORT_TX_DW_LN0(5,
> port))
> -#define ICL_PORT_TX_DW5_AUX(port) _MMIO(_ICL_PORT_TX_DW_AUX(5,
> port))
> -#define ICL_PORT_TX_DW5_GRP(port) _MMIO(_ICL_PORT_TX_DW_GRP(5,
> port))
> -#define ICL_PORT_TX_DW5_LN0(port) _MMIO(_ICL_PORT_TX_DW_LN(5, 0,
> port))
> +#define ICL_PORT_TX_DW5_AUX(phy) _MMIO(_ICL_PORT_TX_DW_AUX(5,
> phy))
> +#define ICL_PORT_TX_DW5_GRP(phy) _MMIO(_ICL_PORT_TX_DW_GRP(5,
> phy))
> +#define ICL_PORT_TX_DW5_LN0(phy) _MMIO(_ICL_PORT_TX_DW_LN(5, 0,
> phy))
> #define TX_TRAINING_EN (1 << 31)
> #define TAP2_DISABLE (1 << 30)
> #define TAP3_DISABLE (1 << 29)
> @@ -1988,10 +1988,10 @@ enum i915_power_well_id {
>
> #define CNL_PORT_TX_DW7_GRP(port) _MMIO(_CNL_PORT_TX_DW_GRP(7,
> (port)))
> #define CNL_PORT_TX_DW7_LN0(port) _MMIO(_CNL_PORT_TX_DW_LN0(7,
> (port)))
> -#define ICL_PORT_TX_DW7_AUX(port) _MMIO(_ICL_PORT_TX_DW_AUX(7,
> port))
> -#define ICL_PORT_TX_DW7_GRP(port) _MMIO(_ICL_PORT_TX_DW_GRP(7,
> port))
> -#define ICL_PORT_TX_DW7_LN0(port) _MMIO(_ICL_PORT_TX_DW_LN(7, 0,
> port))
> -#define ICL_PORT_TX_DW7_LN(ln, port) _MMIO(_ICL_PORT_TX_DW_LN(7, ln,
> port))
> +#define ICL_PORT_TX_DW7_AUX(phy) _MMIO(_ICL_PORT_TX_DW_AUX(7,
> phy))
> +#define ICL_PORT_TX_DW7_GRP(phy) _MMIO(_ICL_PORT_TX_DW_GRP(7,
> phy))
> +#define ICL_PORT_TX_DW7_LN0(phy) _MMIO(_ICL_PORT_TX_DW_LN(7, 0,
> phy))
> +#define ICL_PORT_TX_DW7_LN(ln, phy) _MMIO(_ICL_PORT_TX_DW_LN(7, ln,
> phy))
> #define N_SCALAR(x) ((x) << 24)
> #define N_SCALAR_MASK (0x7F << 24)
>
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^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: [PATCH v4 1/5] drm/i915/gen11: Start distinguishing 'phy' from 'port'
2019-07-08 23:59 ` Souza, Jose
@ 2019-07-09 0:45 ` Souza, Jose
0 siblings, 0 replies; 33+ messages in thread
From: Souza, Jose @ 2019-07-09 0:45 UTC (permalink / raw)
To: Roper, Matthew D, intel-gfx; +Cc: Nikula, Jani, De Marchi, Lucas
On Mon, 2019-07-08 at 23:59 +0000, Souza, Jose wrote:
> On Wed, 2019-07-03 at 16:37 -0700, Matt Roper wrote:
> > Our past DDI-based Intel platforms have had a fixed DDI<->PHY
> > mapping.
> > Because of this, both the bspec documentation and our i915 code has
> > used
> > the term "port" when talking about either DDI's or PHY's; it was
> > always
> > easy to tell what terms like "Port A" were referring to from the
> > context.
> >
> > Unfortunately this is starting to break down now that EHL allows
> > PHY-
> > A
> > to be driven by either DDI-A or DDI-D. Is a setup with DDI-D
> > driving
> > PHY-A considered "Port A" or "Port D?" The answer depends on which
> > register we're working with, and even the bspec doesn't do a great
> > job
> > of clarifying this.
> >
> > Let's try to be more explicit about whether we're talking about the
> > DDI
> > or the PHY on gen11+ by using 'port' to refer to the DDI and
> > creating
> > a
> > new 'enum phy' namespace to refer to the PHY in use.
> >
> > This patch just adds the new PHY namespace, new phy-based versions
> > of
> > intel_port_is_*(), and a helper to convert a port to a PHY.
> > Transitioning various areas of the code over to using the PHY
> > namespace
> > will be done in subsequent patches to make review easier. We'll
> > remove
> > the intel_port_is_*() functions at the end of the series when we
> > transition all callers over to using the PHY-based versions.
> >
> > v2:
> > - Convert a few more 'port' uses to 'phy.' (Sparse)
> >
> > v3:
> > - Switch DDI_CLK_SEL() back to 'port.' (Jose)
> > - Add a code comment clarifying why DPCLKA_CFGCR0_ICL needs to use
> > PHY
> > for its bit definitions, even though the register description is
> > given in terms of DDI.
> > - To avoid confusion, switch CNL's DPCLKA_CFGCR0 defines back to
> > using
> > port and create separate ICL+ definitions that work in terms of
> > PHY.
> >
> > v4:
> > - Rebase and resolve conflicts with Imre's TC series.
> > - This patch now just adds the namespace and a few convenience
> > functions; the important changes are now split out into separate
> > patches to make review easier.
> >
> > Suggested-by: Ville Syrjala <ville.syrjala@linux.intel.com>
> > Cc: José Roberto de Souza <jose.souza@intel.com>
> > Cc: Lucas De Marchi <lucas.demarchi@intel.com>
> > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > Cc: Imre Deak <imre.deak@intel.com>
> > Cc: Jani Nikula <jani.nikula@intel.com>
> > Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> > ---
> > drivers/gpu/drm/i915/display/intel_display.c | 32
> > +++++++++++++++++++-
> > drivers/gpu/drm/i915/display/intel_display.h | 16 ++++++++++
> > drivers/gpu/drm/i915/intel_drv.h | 2 ++
> > 3 files changed, 49 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> > b/drivers/gpu/drm/i915/display/intel_display.c
> > index 919f5ac844c8..4a85abef93e7 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > @@ -6663,6 +6663,20 @@ bool intel_port_is_combophy(struct
> > drm_i915_private *dev_priv, enum port port)
> > return false;
> > }
>
> A call to intel_port_is_combophy(PORT_D) would return false on EHL,
> it
> and intel_port_is_tc() should use intel_phy functions, like:
>
> bool intel_port_is_combophy(struct drm_i915_private *dev_priv, enum
> port port)
> {
> return intel_phy_is_combo(dev_priv, intel_port_to_phy(dev_priv,
> port));
> }
>
> Even better would be check if we can replace those with intel_phy
> counterparts.
You did that on patch 4, so I guess you can disconsider this comments.
>
> >
> > +bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum
> > phy
> > phy)
> > +{
> > + if (phy == PHY_NONE)
> > + return false;
> > +
> > + if (IS_ELKHARTLAKE(dev_priv))
> > + return phy <= PHY_C;
> > +
> > + if (INTEL_GEN(dev_priv) >= 11)
> > + return phy <= PHY_B;
> > +
> > + return false;
> > +}
> > +
> > bool intel_port_is_tc(struct drm_i915_private *dev_priv, enum port
> > port)
> > {
> > if (INTEL_GEN(dev_priv) >= 11 && !IS_ELKHARTLAKE(dev_priv))
> > @@ -6671,9 +6685,25 @@ bool intel_port_is_tc(struct
> > drm_i915_private
> > *dev_priv, enum port port)
> > return false;
> > }
> >
> > +bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy
> > phy)
> > +{
> > + if (INTEL_GEN(dev_priv) >= 11 && !IS_ELKHARTLAKE(dev_priv))
> > + return phy >= PHY_C && phy <= PHY_F;
> > +
> > + return false;
> > +}
> > +
> > +enum phy intel_port_to_phy(struct drm_i915_private *i915, enum
> > port
> > port)
> > +{
> > + if (IS_ELKHARTLAKE(i915) && port == PORT_D)
> > + return PHY_A;
> > +
> > + return (enum phy)port;
> > +}
> > +
> > enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv,
> > enum port port)
> > {
> > - if (!intel_port_is_tc(dev_priv, port))
> > + if (!intel_phy_is_tc(dev_priv, intel_port_to_phy(dev_priv,
> > port)))
> > return PORT_TC_NONE;
> >
> > return port - PORT_C;
> > diff --git a/drivers/gpu/drm/i915/display/intel_display.h
> > b/drivers/gpu/drm/i915/display/intel_display.h
> > index d296556ed82e..d53285fb883f 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display.h
> > +++ b/drivers/gpu/drm/i915/display/intel_display.h
> > @@ -228,6 +228,21 @@ struct intel_link_m_n {
> > u32 link_n;
> > };
> >
> > +enum phy {
> > + PHY_NONE = -1,
> > +
> > + PHY_A = 0,
> > + PHY_B,
> > + PHY_C,
> > + PHY_D,
> > + PHY_E,
> > + PHY_F,
> > +
> > + I915_MAX_PHYS
> > +};
> > +
> > +#define phy_name(a) ((a) + 'A')
> > +
> > #define for_each_pipe(__dev_priv, __p) \
> > for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes;
> > (__p)++)
> >
> > @@ -356,5 +371,6 @@ void lpt_disable_clkout_dp(struct
> > drm_i915_private *dev_priv);
> > u32 intel_plane_fb_max_stride(struct drm_i915_private *dev_priv,
> > u32 pixel_format, u64 modifier);
> > bool intel_plane_can_remap(const struct intel_plane_state
> > *plane_state);
> > +enum phy intel_port_to_phy(struct drm_i915_private *i915, enum
> > port
> > port);
> >
> > #endif
> > diff --git a/drivers/gpu/drm/i915/intel_drv.h
> > b/drivers/gpu/drm/i915/intel_drv.h
> > index 24c63ed45c6f..815c26c0b98c 100644
> > --- a/drivers/gpu/drm/i915/intel_drv.h
> > +++ b/drivers/gpu/drm/i915/intel_drv.h
> > @@ -1493,7 +1493,9 @@ void intel_encoder_destroy(struct drm_encoder
> > *encoder);
> > struct drm_display_mode *
> > intel_encoder_current_mode(struct intel_encoder *encoder);
> > bool intel_port_is_combophy(struct drm_i915_private *dev_priv,
> > enum
> > port port);
> > +bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum
> > phy
> > phy);
> > bool intel_port_is_tc(struct drm_i915_private *dev_priv, enum port
> > port);
> > +bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy
> > phy);
> > enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv,
> > enum port port);
> > int intel_get_pipe_from_crtc_id_ioctl(struct drm_device *dev, void
> > *data,
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: [PATCH v4 4/5] drm/i915: Transition port type checks to phy checks
2019-07-03 23:37 ` [PATCH v4 4/5] drm/i915: Transition port type checks to phy checks Matt Roper
2019-07-04 0:02 ` [PATCH v5 " Matt Roper
2019-07-04 16:07 ` [PATCH v4 " kbuild test robot
@ 2019-07-09 1:00 ` Souza, Jose
2 siblings, 0 replies; 33+ messages in thread
From: Souza, Jose @ 2019-07-09 1:00 UTC (permalink / raw)
To: Roper, Matthew D, intel-gfx
On Wed, 2019-07-03 at 16:37 -0700, Matt Roper wrote:
> Transition the remaining uses of intel_port_is_* over to the
> equivalent
> intel_phy_is_* functions and drop the port functions.
Awesome
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
>
> Cc: José Roberto de Souza <jose.souza@intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> ---
> We might want to hold off on merging this one until after TGL lands
> to
> avoid unnecessary conflicts there.
>
> drivers/gpu/drm/i915/display/intel_bios.c | 4 +-
> drivers/gpu/drm/i915/display/intel_ddi.c | 49 ++++++++++++-----
> --
> drivers/gpu/drm/i915/display/intel_display.c | 38 ++++----------
> .../drm/i915/display/intel_display_power.c | 4 +-
> drivers/gpu/drm/i915/display/intel_dp.c | 15 +++---
> drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 11 +++--
> drivers/gpu/drm/i915/intel_drv.h | 2 -
> 7 files changed, 61 insertions(+), 62 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_bios.c
> b/drivers/gpu/drm/i915/display/intel_bios.c
> index 0c9808132d67..4fdbb5c35d87 100644
> --- a/drivers/gpu/drm/i915/display/intel_bios.c
> +++ b/drivers/gpu/drm/i915/display/intel_bios.c
> @@ -28,6 +28,7 @@
> #include <drm/drm_dp_helper.h>
> #include <drm/i915_drm.h>
>
> +#include "display/intel_display.h"
> #include "display/intel_gmbus.h"
>
> #include "i915_drv.h"
> @@ -1733,12 +1734,13 @@ init_vbt_missing_defaults(struct
> drm_i915_private *dev_priv)
> for (port = PORT_A; port < I915_MAX_PORTS; port++) {
> struct ddi_vbt_port_info *info =
> &dev_priv->vbt.ddi_port_info[port];
> + enum phy phy = intel_port_to_phy(dev_priv, port);
>
> /*
> * VBT has the TypeC mode (native,TBT/USB) and we don't
> want
> * to detect it.
> */
> - if (intel_port_is_tc(dev_priv, port))
> + if (intel_phy_is_tc(dev_priv, phy))
> continue;
>
> info->supports_dvi = (port != PORT_A && port !=
> PORT_E);
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 50dd9d731456..37c8cecb9a6a 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -868,11 +868,12 @@ icl_get_combo_buf_trans(struct drm_i915_private
> *dev_priv, int type, int rate,
> static int intel_ddi_hdmi_level(struct drm_i915_private *dev_priv,
> enum port port)
> {
> int n_entries, level, default_entry;
> + enum phy phy = intel_port_to_phy(dev_priv, port);
>
> level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift;
>
> if (INTEL_GEN(dev_priv) >= 11) {
> - if (intel_port_is_combophy(dev_priv, port))
> + if (intel_phy_is_combo(dev_priv, phy))
> icl_get_combo_buf_trans(dev_priv,
> INTEL_OUTPUT_HDMI,
> 0, &n_entries);
> else
> @@ -1487,9 +1488,10 @@ static void icl_ddi_clock_get(struct
> intel_encoder *encoder,
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> struct intel_dpll_hw_state *pll_state = &pipe_config-
> >dpll_hw_state;
> enum port port = encoder->port;
> + enum phy phy = intel_port_to_phy(dev_priv, port);
> int link_clock;
>
> - if (intel_port_is_combophy(dev_priv, port)) {
> + if (intel_phy_is_combo(dev_priv, phy)) {
> link_clock = cnl_calc_wrpll_link(dev_priv, pll_state);
> } else {
> enum intel_dpll_id pll_id =
> intel_get_shared_dpll_id(dev_priv,
> @@ -2086,6 +2088,7 @@ static void intel_ddi_get_power_domains(struct
> intel_encoder *encoder,
> {
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> struct intel_digital_port *dig_port;
> + enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
>
> /*
> * TODO: Add support for MST encoders. Atm, the following
> should never
> @@ -2103,7 +2106,7 @@ static void intel_ddi_get_power_domains(struct
> intel_encoder *encoder,
> * ports.
> */
> if (intel_crtc_has_dp_encoder(crtc_state) ||
> - intel_port_is_tc(dev_priv, encoder->port))
> + intel_phy_is_tc(dev_priv, phy))
> intel_display_power_get(dev_priv,
> intel_ddi_main_link_aux_domain(
> dig_port));
>
> @@ -2228,10 +2231,11 @@ u8 intel_ddi_dp_voltage_max(struct
> intel_encoder *encoder)
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
> enum port port = encoder->port;
> + enum phy phy = intel_port_to_phy(dev_priv, port);
> int n_entries;
>
> if (INTEL_GEN(dev_priv) >= 11) {
> - if (intel_port_is_combophy(dev_priv, port))
> + if (intel_phy_is_combo(dev_priv, phy))
> icl_get_combo_buf_trans(dev_priv, encoder-
> >type,
> intel_dp->link_rate,
> &n_entries);
> else
> @@ -2664,9 +2668,9 @@ static void icl_ddi_vswing_sequence(struct
> intel_encoder *encoder,
> enum intel_output_type type)
> {
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> - enum port port = encoder->port;
> + enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
>
> - if (intel_port_is_combophy(dev_priv, port))
> + if (intel_phy_is_combo(dev_priv, phy))
> icl_combo_phy_ddi_vswing_sequence(encoder, level,
> type);
> else
> icl_mg_phy_ddi_vswing_sequence(encoder, link_clock,
> level);
> @@ -2729,12 +2733,13 @@ u32 ddi_signal_levels(struct intel_dp
> *intel_dp)
>
> static inline
> u32 icl_dpclka_cfgcr0_clk_off(struct drm_i915_private *dev_priv,
> - enum port port)
> + enum phy phy)
> {
> - if (intel_port_is_combophy(dev_priv, port)) {
> - return ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(port);
> - } else if (intel_port_is_tc(dev_priv, port)) {
> - enum tc_port tc_port = intel_port_to_tc(dev_priv,
> port);
> + if (intel_phy_is_combo(dev_priv, phy)) {
> + return ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
> + } else if (intel_phy_is_tc(dev_priv, phy)) {
> + enum tc_port tc_port = intel_port_to_tc(dev_priv,
> + (enum
> port)phy);
>
> return ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port);
> }
> @@ -2876,6 +2881,7 @@ static void intel_ddi_clk_select(struct
> intel_encoder *encoder,
> {
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> enum port port = encoder->port;
> + enum phy phy = intel_port_to_phy(dev_priv, port);
> u32 val;
> const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
>
> @@ -2885,7 +2891,7 @@ static void intel_ddi_clk_select(struct
> intel_encoder *encoder,
> mutex_lock(&dev_priv->dpll_lock);
>
> if (INTEL_GEN(dev_priv) >= 11) {
> - if (!intel_port_is_combophy(dev_priv, port))
> + if (!intel_phy_is_combo(dev_priv, phy))
> I915_WRITE(DDI_CLK_SEL(port),
> icl_pll_to_ddi_clk_sel(encoder,
> crtc_state));
> } else if (IS_CANNONLAKE(dev_priv)) {
> @@ -2925,9 +2931,10 @@ static void intel_ddi_clk_disable(struct
> intel_encoder *encoder)
> {
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> enum port port = encoder->port;
> + enum phy phy = intel_port_to_phy(dev_priv, port);
>
> if (INTEL_GEN(dev_priv) >= 11) {
> - if (!intel_port_is_combophy(dev_priv, port))
> + if (!intel_phy_is_combo(dev_priv, phy))
> I915_WRITE(DDI_CLK_SEL(port),
> DDI_CLK_SEL_NONE);
> } else if (IS_CANNONLAKE(dev_priv)) {
> I915_WRITE(DPCLKA_CFGCR0, I915_READ(DPCLKA_CFGCR0) |
> @@ -3134,7 +3141,7 @@ static void intel_ddi_pre_enable_dp(struct
> intel_encoder *encoder,
>
> intel_ddi_clk_select(encoder, crtc_state);
>
> - if (!intel_port_is_tc(dev_priv, port) ||
> + if (!intel_phy_is_tc(dev_priv, phy) ||
> dig_port->tc_mode != TC_PORT_TBT_ALT)
> intel_display_power_get(dev_priv,
> dig_port->ddi_io_power_domain);
> @@ -3152,7 +3159,7 @@ static void intel_ddi_pre_enable_dp(struct
> intel_encoder *encoder,
> else
> intel_prepare_dp_ddi_buffers(encoder, crtc_state);
>
> - if (intel_port_is_combophy(dev_priv, port)) {
> + if (intel_phy_is_combo(dev_priv, phy)) {
> bool lane_reversal =
> dig_port->saved_port_bits &
> DDI_BUF_PORT_REVERSAL;
>
> @@ -3304,6 +3311,7 @@ static void intel_ddi_post_disable_dp(struct
> intel_encoder *encoder,
> struct intel_dp *intel_dp = &dig_port->dp;
> bool is_mst = intel_crtc_has_type(old_crtc_state,
> INTEL_OUTPUT_DP_MST);
> + enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
>
> if (!is_mst) {
> intel_ddi_disable_pipe_clock(old_crtc_state);
> @@ -3319,7 +3327,7 @@ static void intel_ddi_post_disable_dp(struct
> intel_encoder *encoder,
> intel_edp_panel_vdd_on(intel_dp);
> intel_edp_panel_off(intel_dp);
>
> - if (!intel_port_is_tc(dev_priv, encoder->port) ||
> + if (!intel_phy_is_tc(dev_priv, phy) ||
> dig_port->tc_mode != TC_PORT_TBT_ALT)
> intel_display_power_put_unchecked(dev_priv,
> dig_port-
> >ddi_io_power_domain);
> @@ -3669,8 +3677,9 @@ intel_ddi_pre_pll_enable(struct intel_encoder
> *encoder,
> {
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> struct intel_digital_port *dig_port = enc_to_dig_port(&encoder-
> >base);
> - bool is_tc_port = intel_port_is_tc(dev_priv, encoder->port);
> enum port port = encoder->port;
> + enum phy phy = intel_port_to_phy(dev_priv, port);
> + bool is_tc_port = intel_phy_is_tc(dev_priv, phy);
>
> if (is_tc_port)
> intel_tc_port_get_link(dig_port, crtc_state-
> >lane_count);
> @@ -3700,7 +3709,8 @@ intel_ddi_post_pll_disable(struct intel_encoder
> *encoder,
> {
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> struct intel_digital_port *dig_port = enc_to_dig_port(&encoder-
> >base);
> - bool is_tc_port = intel_port_is_tc(dev_priv, encoder->port);
> + enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
> + bool is_tc_port = intel_phy_is_tc(dev_priv, phy);
>
> if (intel_crtc_has_dp_encoder(crtc_state) || is_tc_port)
> intel_display_power_put_unchecked(dev_priv,
> @@ -4214,6 +4224,7 @@ void intel_ddi_init(struct drm_i915_private
> *dev_priv, enum port port)
> struct drm_encoder *encoder;
> bool init_hdmi, init_dp, init_lspcon = false;
> enum pipe pipe;
> + enum phy phy = intel_port_to_phy(dev_priv, port);
>
> init_hdmi = port_info->supports_dvi || port_info-
> >supports_hdmi;
> init_dp = port_info->supports_dp;
> @@ -4277,7 +4288,7 @@ void intel_ddi_init(struct drm_i915_private
> *dev_priv, enum port port)
> intel_dig_port->max_lanes =
> intel_ddi_max_lanes(intel_dig_port);
> intel_dig_port->aux_ch = intel_bios_port_aux_ch(dev_priv,
> port);
>
> - if (intel_port_is_tc(dev_priv, port)) {
> + if (intel_phy_is_tc(dev_priv, phy)) {
> bool is_legacy = !port_info->supports_typec_usb &&
> !port_info->supports_tbt;
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index 4a85abef93e7..550530cc2d24 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -6649,20 +6649,6 @@ static void i9xx_pfit_enable(const struct
> intel_crtc_state *crtc_state)
> I915_WRITE(BCLRPAT(crtc->pipe), 0);
> }
>
> -bool intel_port_is_combophy(struct drm_i915_private *dev_priv, enum
> port port)
> -{
> - if (port == PORT_NONE)
> - return false;
> -
> - if (IS_ELKHARTLAKE(dev_priv))
> - return port <= PORT_C;
> -
> - if (INTEL_GEN(dev_priv) >= 11)
> - return port <= PORT_B;
> -
> - return false;
> -}
> -
> bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy
> phy)
> {
> if (phy == PHY_NONE)
> @@ -6677,14 +6663,6 @@ bool intel_phy_is_combo(struct
> drm_i915_private *dev_priv, enum phy phy)
> return false;
> }
>
> -bool intel_port_is_tc(struct drm_i915_private *dev_priv, enum port
> port)
> -{
> - if (INTEL_GEN(dev_priv) >= 11 && !IS_ELKHARTLAKE(dev_priv))
> - return port >= PORT_C && port <= PORT_F;
> -
> - return false;
> -}
> -
> bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy
> phy)
> {
> if (INTEL_GEN(dev_priv) >= 11 && !IS_ELKHARTLAKE(dev_priv))
> @@ -6734,8 +6712,9 @@ enum intel_display_power_domain
> intel_aux_power_domain(struct intel_digital_port *dig_port)
> {
> struct drm_i915_private *dev_priv = to_i915(dig_port-
> >base.base.dev);
> + enum phy phy = intel_port_to_phy(dev_priv, dig_port-
> >base.port);
>
> - if (intel_port_is_tc(dev_priv, dig_port->base.port) &&
> + if (intel_phy_is_tc(dev_priv, phy) &&
> dig_port->tc_mode == TC_PORT_TBT_ALT) {
> switch (dig_port->aux_ch) {
> case AUX_CH_C:
> @@ -10069,16 +10048,17 @@ static void icelake_get_ddi_pll(struct
> drm_i915_private *dev_priv,
> enum port port,
> struct intel_crtc_state *pipe_config)
> {
> + enum phy phy = intel_port_to_phy(dev_priv, port);
> enum icl_port_dpll_id port_dpll_id;
> enum intel_dpll_id id;
> u32 temp;
>
> - if (intel_port_is_combophy(dev_priv, port)) {
> + if (intel_phy_is_combo(dev_priv, phy)) {
> temp = I915_READ(DPCLKA_CFGCR0_ICL) &
> - DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
> - id = temp >> DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port);
> + ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
> + id = temp >> ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy);
> port_dpll_id = ICL_PORT_DPLL_DEFAULT;
> - } else if (intel_port_is_tc(dev_priv, port)) {
> + } else if (intel_phy_is_tc(dev_priv, phy)) {
> u32 clk_sel = I915_READ(DDI_CLK_SEL(port)) &
> DDI_CLK_SEL_MASK;
>
> if (clk_sel == DDI_CLK_SEL_MG) {
> @@ -16935,9 +16915,11 @@ intel_modeset_setup_hw_state(struct
> drm_device *dev,
>
> /* Sanitize the TypeC port mode upfront, encoders depend on
> this */
> for_each_intel_encoder(dev, encoder) {
> + enum phy phy = intel_port_to_phy(dev_priv, encoder-
> >port);
> +
> /* We need to sanitize only the MST primary port. */
> if (encoder->type != INTEL_OUTPUT_DP_MST &&
> - intel_port_is_tc(dev_priv, encoder->port))
> + intel_phy_is_tc(dev_priv, phy))
> intel_tc_port_sanitize(enc_to_dig_port(&encoder
> ->base));
> }
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
> b/drivers/gpu/drm/i915/display/intel_display_power.c
> index 64627c117c31..0f6ea4d6d1ef 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> @@ -487,7 +487,9 @@ static void icl_tc_port_assert_ref_held(struct
> drm_i915_private *dev_priv,
> aux_ch = icl_tc_phy_aux_ch(dev_priv, power_well);
>
> for_each_intel_encoder(&dev_priv->drm, encoder) {
> - if (!intel_port_is_tc(dev_priv, encoder->port))
> + enum phy phy = intel_port_to_phy(encoder->port);
> +
> + if (!intel_phy_is_tc(dev_priv, phy))
> continue;
>
> /* We'll check the MST primary port */
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index 8f7188d71d08..67603a247e8a 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -297,9 +297,9 @@ static int icl_max_source_rate(struct intel_dp
> *intel_dp)
> {
> struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
> struct drm_i915_private *dev_priv = to_i915(dig_port-
> >base.base.dev);
> - enum port port = dig_port->base.port;
> + enum phy phy = intel_port_to_phy(dev_priv, dig_port-
> >base.port);
>
> - if (intel_port_is_combophy(dev_priv, port) &&
> + if (intel_phy_is_combo(dev_priv, phy) &&
> !IS_ELKHARTLAKE(dev_priv) &&
> !intel_dp_is_edp(intel_dp))
> return 540000;
> @@ -1192,7 +1192,8 @@ intel_dp_aux_xfer(struct intel_dp *intel_dp,
> struct drm_i915_private *i915 =
> to_i915(intel_dig_port->base.base.dev);
> struct intel_uncore *uncore = &i915->uncore;
> - bool is_tc_port = intel_port_is_tc(i915, intel_dig_port-
> >base.port);
> + enum phy phy = intel_port_to_phy(i915, intel_dig_port-
> >base.port);
> + bool is_tc_port = intel_phy_is_tc(i915, phy);
> i915_reg_t ch_ctl, ch_data[5];
> u32 aux_clock_divider;
> enum intel_display_power_domain aux_domain =
> @@ -5211,10 +5212,11 @@ static bool icl_digital_port_connected(struct
> intel_encoder *encoder)
> {
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> struct intel_digital_port *dig_port = enc_to_dig_port(&encoder-
> >base);
> + enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
>
> - if (intel_port_is_combophy(dev_priv, encoder->port))
> + if (intel_phy_is_combo(dev_priv, phy))
> return icl_combo_port_connected(dev_priv, dig_port);
> - else if (intel_port_is_tc(dev_priv, encoder->port))
> + else if (intel_phy_is_tc(dev_priv, phy))
> return intel_tc_port_connected(dig_port);
> else
> MISSING_CASE(encoder->hpd_pin);
> @@ -7118,6 +7120,7 @@ intel_dp_init_connector(struct
> intel_digital_port *intel_dig_port,
> struct drm_device *dev = intel_encoder->base.dev;
> struct drm_i915_private *dev_priv = to_i915(dev);
> enum port port = intel_encoder->port;
> + enum phy phy = intel_port_to_phy(dev_priv, port);
> int type;
>
> /* Initialize the work for modeset in case of link train
> failure */
> @@ -7144,7 +7147,7 @@ intel_dp_init_connector(struct
> intel_digital_port *intel_dig_port,
> * Currently we don't support eDP on TypeC ports,
> although in
> * theory it could work on TypeC legacy ports.
> */
> - WARN_ON(intel_port_is_tc(dev_priv, port));
> + WARN_ON(intel_phy_is_tc(dev_priv, phy));
> type = DRM_MODE_CONNECTOR_eDP;
> } else {
> type = DRM_MODE_CONNECTOR_DisplayPort;
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> index f953971e7c3b..f8782c24c447 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> @@ -2580,7 +2580,8 @@ static bool icl_calc_dpll_state(struct
> intel_crtc_state *crtc_state,
> struct skl_wrpll_params pll_params = { 0 };
> bool ret;
>
> - if (intel_port_is_tc(dev_priv, encoder->port))
> + if (intel_phy_is_tc(dev_priv, intel_port_to_phy(dev_priv,
> + encoder-
> >port)))
> ret = icl_calc_tbt_pll(crtc_state, &pll_params);
> else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) ||
> intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI))
> @@ -2993,14 +2994,14 @@ static bool icl_get_dplls(struct
> intel_atomic_state *state,
> struct intel_encoder *encoder)
> {
> struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> - enum port port = encoder->port;
> + enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
>
> - if (intel_port_is_combophy(dev_priv, port))
> + if (intel_phy_is_combo(dev_priv, phy))
> return icl_get_combo_phy_dpll(state, crtc, encoder);
> - else if (intel_port_is_tc(dev_priv, port))
> + else if (intel_phy_is_tc(dev_priv, phy))
> return icl_get_tc_phy_dplls(state, crtc, encoder);
>
> - MISSING_CASE(port);
> + MISSING_CASE(phy);
>
> return false;
> }
> diff --git a/drivers/gpu/drm/i915/intel_drv.h
> b/drivers/gpu/drm/i915/intel_drv.h
> index 815c26c0b98c..770f9f6aad84 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -1492,9 +1492,7 @@ void intel_pps_unlock_regs_wa(struct
> drm_i915_private *dev_priv);
> void intel_encoder_destroy(struct drm_encoder *encoder);
> struct drm_display_mode *
> intel_encoder_current_mode(struct intel_encoder *encoder);
> -bool intel_port_is_combophy(struct drm_i915_private *dev_priv, enum
> port port);
> bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy
> phy);
> -bool intel_port_is_tc(struct drm_i915_private *dev_priv, enum port
> port);
> bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy
> phy);
> enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv,
> enum port port);
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 33+ messages in thread
end of thread, other threads:[~2019-07-09 1:00 UTC | newest]
Thread overview: 33+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-07-03 23:37 [PATCH v4 0/5] EHL port programming Matt Roper
2019-07-03 23:37 ` [PATCH v4 1/5] drm/i915/gen11: Start distinguishing 'phy' from 'port' Matt Roper
2019-07-04 9:18 ` Ville Syrjälä
2019-07-04 9:24 ` Ville Syrjälä
2019-07-04 14:54 ` Lucas De Marchi
2019-07-04 15:09 ` Ville Syrjälä
2019-07-04 15:55 ` Lucas De Marchi
2019-07-05 10:33 ` Ville Syrjälä
2019-07-08 14:02 ` Lucas De Marchi
2019-07-08 14:12 ` Ville Syrjälä
2019-07-08 23:59 ` Souza, Jose
2019-07-09 0:45 ` Souza, Jose
2019-07-03 23:37 ` [PATCH v4 2/5] drm/i915/gen11: Program DPCLKA_CFGCR0_ICL according to PHY Matt Roper
2019-07-04 1:06 ` [PATCH v5 " Matt Roper
2019-07-04 9:31 ` Ville Syrjälä
2019-07-09 0:15 ` Souza, Jose
2019-07-03 23:37 ` [PATCH v4 3/5] drm/i915/gen11: Convert combo PHY logic to use new 'enum phy' namespace Matt Roper
2019-07-04 9:39 ` Ville Syrjälä
2019-07-09 0:41 ` Souza, Jose
2019-07-03 23:37 ` [PATCH v4 4/5] drm/i915: Transition port type checks to phy checks Matt Roper
2019-07-04 0:02 ` [PATCH v5 " Matt Roper
2019-07-08 13:13 ` Ville Syrjälä
2019-07-04 16:07 ` [PATCH v4 " kbuild test robot
2019-07-09 1:00 ` Souza, Jose
2019-07-03 23:37 ` [PATCH v4 5/5] drm/i915/ehl: Enable DDI-D Matt Roper
2019-07-03 23:51 ` ✗ Fi.CI.BAT: failure for EHL port programming (rev4) Patchwork
2019-07-03 23:56 ` [PATCH v4 0/5] EHL port programming Souza, Jose
2019-07-04 0:40 ` ✗ Fi.CI.CHECKPATCH: warning for EHL port programming (rev5) Patchwork
2019-07-04 0:43 ` ✗ Fi.CI.SPARSE: " Patchwork
2019-07-04 1:18 ` ✓ Fi.CI.BAT: success " Patchwork
2019-07-04 1:55 ` ✗ Fi.CI.CHECKPATCH: warning for EHL port programming (rev6) Patchwork
2019-07-04 2:16 ` ✓ Fi.CI.BAT: success " Patchwork
2019-07-05 6:44 ` ✓ Fi.CI.IGT: " Patchwork
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