From mboxrd@z Thu Jan 1 00:00:00 1970 From: Andes Date: Tue, 9 Jul 2019 17:28:11 +0800 Subject: [U-Boot] [PATCH v2 4/7] riscv: ax25: add imply v5l2 cache controller In-Reply-To: <20190709092814.21363-1-uboot@andestech.com> References: <20190709092814.21363-1-uboot@andestech.com> Message-ID: <20190709092814.21363-5-uboot@andestech.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de From: Rick Chen Select the v5l2 UCLASS_CACHE driver for ax25. Signed-off-by: Rick Chen Cc: Greentime Hu Cc: KC Lin --- arch/riscv/cpu/ax25/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/riscv/cpu/ax25/Kconfig b/arch/riscv/cpu/ax25/Kconfig index 6b4b92e..49be775 100644 --- a/arch/riscv/cpu/ax25/Kconfig +++ b/arch/riscv/cpu/ax25/Kconfig @@ -4,6 +4,7 @@ config RISCV_NDS imply CPU imply CPU_RISCV imply RISCV_TIMER + imply V5L2_CACHE imply ANDES_PLIC if RISCV_MMODE imply ANDES_PLMT if RISCV_MMODE help -- 2.7.4