From mboxrd@z Thu Jan 1 00:00:00 1970 From: Andes Date: Tue, 9 Jul 2019 17:28:12 +0800 Subject: [U-Boot] [PATCH v2 5/7] riscv: cache: Flush L2 cache before jump to linux In-Reply-To: <20190709092814.21363-1-uboot@andestech.com> References: <20190709092814.21363-1-uboot@andestech.com> Message-ID: <20190709092814.21363-6-uboot@andestech.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de From: Rick Chen Flush and disable cache in cleanup_before_linux() which will be called before jump to linux. The sequence will be preferred as below: L1 flush -> L1 disable -> L2 flush -> L2 disable Signed-off-by: Rick Chen Cc: Greentime Hu Cc: KC Lin --- arch/riscv/cpu/ax25/cpu.c | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/arch/riscv/cpu/ax25/cpu.c b/arch/riscv/cpu/ax25/cpu.c index 76689b2..31a714e 100644 --- a/arch/riscv/cpu/ax25/cpu.c +++ b/arch/riscv/cpu/ax25/cpu.c @@ -7,6 +7,29 @@ /* CPU specific code */ #include #include +#include +#include +#include + +void enable_v5l2(void) +{ + struct udevice *dev = NULL; + + uclass_find_first_device(UCLASS_CACHE, &dev); + + if (dev) + cache_enable(dev); +} + +void disable_v5l2(void) +{ + struct udevice *dev = NULL; + + uclass_find_first_device(UCLASS_CACHE, &dev); + + if (dev) + cache_disable(dev); +} /* * cleanup_before_linux() is called just before we call linux @@ -22,6 +45,9 @@ int cleanup_before_linux(void) cache_flush(); icache_disable(); dcache_disable(); +#ifdef CONFIG_RISCV_NDS_CACHE + disable_v5l2(); +#endif return 0; } -- 2.7.4