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[79.178.2.209]) by smtp.gmail.com with ESMTPSA id c1sm141207wrh.1.2019.07.09.14.37.06 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 09 Jul 2019 14:37:06 -0700 (PDT) From: Michael Rolnik To: qemu-devel@nongnu.org Date: Wed, 10 Jul 2019 00:36:51 +0300 Message-Id: <20190709213651.77315-8-mrolnik@gmail.com> X-Mailer: git-send-email 2.17.2 (Apple Git-113) In-Reply-To: <20190709213651.77315-1-mrolnik@gmail.com> References: <20190709213651.77315-1-mrolnik@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::343 Subject: [Qemu-devel] [PATCH v25 7/7] target/avr: Register AVR support with the rest of QEMU, the build system, and the MAINTAINERS file X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: imammedo@redhat.com, Sarah Harris , richard.henderson@linaro.org, Michael Rolnik Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" From: Sarah Harris Signed-off-by: Michael Rolnik --- MAINTAINERS | 6 ++++++ arch_init.c | 2 ++ configure | 7 +++++++ default-configs/avr-softmmu.mak | 5 +++++ hw/avr/sample.c | 2 +- include/disas/dis-asm.h | 6 ++++++ include/sysemu/arch_init.h | 1 + qapi/common.json | 3 ++- target/avr/Makefile.objs | 33 +++++++++++++++++++++++++++++++++ target/avr/cpu.c | 13 ++++--------- target/avr/cpu.h | 3 --- tests/machine-none-test.c | 1 + 12 files changed, 68 insertions(+), 14 deletions(-) create mode 100644 default-configs/avr-softmmu.mak create mode 100644 target/avr/Makefile.objs diff --git a/MAINTAINERS b/MAINTAINERS index cc9636b43a..934ad5739b 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -163,6 +163,12 @@ S: Maintained F: hw/arm/smmu* F: include/hw/arm/smmu* +AVR TCG CPUs +M: Michael Rolnik +S: Maintained +F: target/avr/ +F: hw/avr/ + CRIS TCG CPUs M: Edgar E. Iglesias S: Maintained diff --git a/arch_init.c b/arch_init.c index 74b0708634..413ad7acfd 100644 --- a/arch_init.c +++ b/arch_init.c @@ -85,6 +85,8 @@ int graphic_depth = 32; #define QEMU_ARCH QEMU_ARCH_UNICORE32 #elif defined(TARGET_XTENSA) #define QEMU_ARCH QEMU_ARCH_XTENSA +#elif defined(TARGET_AVR) +#define QEMU_ARCH QEMU_ARCH_AVR #endif const uint32_t arch_type = QEMU_ARCH; diff --git a/configure b/configure index 4983c8b533..ab8ebba100 100755 --- a/configure +++ b/configure @@ -7503,6 +7503,10 @@ case "$target_name" in target_compiler=$cross_cc_aarch64 eval "target_compiler_cflags=\$cross_cc_cflags_${target_name}" ;; + avr) + gdb_xml_files="avr-cpu.xml" + target_compiler=$cross_cc_avr + ;; cris) target_compiler=$cross_cc_cris ;; @@ -7780,6 +7784,9 @@ for i in $ARCH $TARGET_BASE_ARCH ; do disas_config "ARM_A64" fi ;; + avr) + disas_config "AVR" + ;; cris) disas_config "CRIS" ;; diff --git a/default-configs/avr-softmmu.mak b/default-configs/avr-softmmu.mak new file mode 100644 index 0000000000..d1e1c28118 --- /dev/null +++ b/default-configs/avr-softmmu.mak @@ -0,0 +1,5 @@ +# Default configuration for avr-softmmu + +# Boards: +# +CONFIG_AVR_SAMPLE=y diff --git a/hw/avr/sample.c b/hw/avr/sample.c index e4cb548a33..de97fe4ae7 100644 --- a/hw/avr/sample.c +++ b/hw/avr/sample.c @@ -197,7 +197,7 @@ static void sample_class_init(ObjectClass *oc, void *data) mc->default_cpus = 1; mc->min_cpus = mc->default_cpus; mc->max_cpus = mc->default_cpus; - mc->default_cpu_type = AVR_CPU_TYPE_NAME("avr6"); /* ATmega2560. */ + mc->default_cpu_type = "avr6-avr-cpu"; /* ATmega2560. */ mc->is_default = 1; } diff --git a/include/disas/dis-asm.h b/include/disas/dis-asm.h index e9c7dd8eb4..8bedce17ac 100644 --- a/include/disas/dis-asm.h +++ b/include/disas/dis-asm.h @@ -211,6 +211,12 @@ enum bfd_architecture #define bfd_mach_m32r 0 /* backwards compatibility */ bfd_arch_mn10200, /* Matsushita MN10200 */ bfd_arch_mn10300, /* Matsushita MN10300 */ + bfd_arch_avr, /* Atmel AVR microcontrollers. */ +#define bfd_mach_avr1 1 +#define bfd_mach_avr2 2 +#define bfd_mach_avr3 3 +#define bfd_mach_avr4 4 +#define bfd_mach_avr5 5 bfd_arch_cris, /* Axis CRIS */ #define bfd_mach_cris_v0_v10 255 #define bfd_mach_cris_v32 32 diff --git a/include/sysemu/arch_init.h b/include/sysemu/arch_init.h index 10cbafe970..aff57bfe61 100644 --- a/include/sysemu/arch_init.h +++ b/include/sysemu/arch_init.h @@ -25,6 +25,7 @@ enum { QEMU_ARCH_NIOS2 = (1 << 17), QEMU_ARCH_HPPA = (1 << 18), QEMU_ARCH_RISCV = (1 << 19), + QEMU_ARCH_AVR = (1 << 20), }; extern const uint32_t arch_type; diff --git a/qapi/common.json b/qapi/common.json index 99d313ef3b..6866c3e81d 100644 --- a/qapi/common.json +++ b/qapi/common.json @@ -183,11 +183,12 @@ # is true even for "qemu-system-x86_64". # # ppcemb: dropped in 3.1 +# avr: added in 4.1 # # Since: 3.0 ## { 'enum' : 'SysEmuTarget', - 'data' : [ 'aarch64', 'alpha', 'arm', 'cris', 'hppa', 'i386', 'lm32', + 'data' : [ 'aarch64', 'alpha', 'arm', 'avr', 'cris', 'hppa', 'i386', 'lm32', 'm68k', 'microblaze', 'microblazeel', 'mips', 'mips64', 'mips64el', 'mipsel', 'moxie', 'nios2', 'or1k', 'ppc', 'ppc64', 'riscv32', 'riscv64', 's390x', 'sh4', diff --git a/target/avr/Makefile.objs b/target/avr/Makefile.objs new file mode 100644 index 0000000000..1034d87525 --- /dev/null +++ b/target/avr/Makefile.objs @@ -0,0 +1,33 @@ +# +# QEMU AVR CPU +# +# Copyright (c) 2016 Michael Rolnik +# +# This library is free software; you can redistribute it and/or +# modify it under the terms of the GNU Lesser General Public +# License as published by the Free Software Foundation; either +# version 2.1 of the License, or (at your option) any later version. +# +# This library is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +# Lesser General Public License for more details. +# +# You should have received a copy of the GNU Lesser General Public +# License along with this library; if not, see +# +# + +DECODETREE = $(SRC_PATH)/scripts/decodetree.py +decode-y = $(SRC_PATH)/target/avr/insn.decode + +target/avr/decode_insn.inc.c: $(decode-y) $(DECODETREE) + $(call quiet-command, \ + $(PYTHON) $(DECODETREE) -o $@ --decode decode_insn --insnwidth 16 $<, \ + "GEN", $(TARGET_DIR)$@) + +target/avr/translate.o: target/avr/decode_insn.inc.c + +obj-y += translate.o cpu.o helper.o +obj-y += gdbstub.o +obj-$(CONFIG_SOFTMMU) += machine.o diff --git a/target/avr/cpu.c b/target/avr/cpu.c index ac85508156..f4e3b1956f 100644 --- a/target/avr/cpu.c +++ b/target/avr/cpu.c @@ -136,11 +136,6 @@ static void avr_cpu_initfn(Object *obj) #endif } -static char *avr_cpu_type_name(const char *cpu_model) -{ - return g_strdup_printf(AVR_CPU_TYPE_NAME("%s"), cpu_model); -} - static ObjectClass *avr_cpu_class_by_name(const char *cpu_model) { ObjectClass *oc; @@ -548,10 +543,10 @@ void avr_cpu_list(void) } #define DEFINE_AVR_CPU_TYPE(model, initfn) \ - { \ - .parent = TYPE_AVR_CPU, \ - .instance_init = initfn, \ - .name = AVR_CPU_TYPE_NAME(model), \ + { \ + .parent = TYPE_AVR_CPU, \ + .instance_init = initfn, \ + .name = model "-avr-cpu", \ } static const TypeInfo avr_cpu_type_info[] = { diff --git a/target/avr/cpu.h b/target/avr/cpu.h index 3f9a803193..bda810c23e 100644 --- a/target/avr/cpu.h +++ b/target/avr/cpu.h @@ -29,9 +29,6 @@ #define TCG_GUEST_DEFAULT_MO 0 #define TYPE_AVR_CPU "avr-cpu" - -#define AVR_CPU_TYPE_SUFFIX "-" TYPE_AVR_CPU -#define AVR_CPU_TYPE_NAME(name) (name AVR_CPU_TYPE_SUFFIX) #define CPU_RESOLVING_TYPE TYPE_AVR_CPU /* diff --git a/tests/machine-none-test.c b/tests/machine-none-test.c index 5953d31755..3e5c74e73e 100644 --- a/tests/machine-none-test.c +++ b/tests/machine-none-test.c @@ -27,6 +27,7 @@ static struct arch2cpu cpus_map[] = { /* tested targets list */ { "arm", "cortex-a15" }, { "aarch64", "cortex-a57" }, + { "avr", "avr6-avr-cpu" }, { "x86_64", "qemu64,apic-id=0" }, { "i386", "qemu32,apic-id=0" }, { "alpha", "ev67" }, -- 2.17.2 (Apple Git-113)