* [PATCH 00/12] GT-fy the uc code
@ 2019-07-10 0:54 Daniele Ceraolo Spurio
2019-07-10 0:54 ` [PATCH 01/12] drm/i915/guc: Remove preemption support for current fw Daniele Ceraolo Spurio
` (15 more replies)
0 siblings, 16 replies; 28+ messages in thread
From: Daniele Ceraolo Spurio @ 2019-07-10 0:54 UTC (permalink / raw)
To: intel-gfx
GuC and HuC are a subunits of the GT HW, so it makes sense for the
relevant structures to be inside intel_gt. This series introduces a new
intel_uc structure under intel_gt and moves the GuC/HuC structures in
there. All the general uc code is then encapsulated, working on intel_uc
instead of i915.
Note that a bit of ugliness is inroduced with the move because we have a
lot of layers (i915->gt.uc.guc.fw). Most of these "deep" accesses are
removed by the later patches in the series, but some of them remain,
mainly in debugfs functions. Follow up updates to make the code more
encapsulated should help cleaning up.
Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
Chris Wilson (1):
drm/i915/guc: Remove preemption support for current fw
Daniele Ceraolo Spurio (11):
drm/i915/guc: simplify guc client
drm/i915/uc: replace uc init/fini misc
drm/i915/uc: introduce intel_uc_fw_supported
drm/i915/guc: move guc irq functions to intel_guc parameter
drm/i915/guc: unify guc irq handling
drm/i915/uc: move GuC and HuC files under gt/uc/
drm/i915/uc: move GuC/HuC inside intel_gt under a new intel_uc
drm/i915/uc: Move intel functions to intel_uc
drm/i915/uc: prefer intel_gt over i915 in GuC/HuC paths
drm/i915/guc: prefer intel_gt in guc interrupt functions
drm/i915/uc: kill <g,h>uc_to_i915
drivers/gpu/drm/i915/Makefile | 21 +-
drivers/gpu/drm/i915/Makefile.header-test | 4 -
drivers/gpu/drm/i915/gem/i915_gem_context.c | 17 -
drivers/gpu/drm/i915/gem/i915_gem_pm.c | 6 +-
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 13 -
drivers/gpu/drm/i915/gt/intel_engine_types.h | 1 -
drivers/gpu/drm/i915/gt/intel_gt.h | 15 +
drivers/gpu/drm/i915/gt/intel_gt_pm.c | 4 -
drivers/gpu/drm/i915/gt/intel_gt_types.h | 6 +
drivers/gpu/drm/i915/gt/intel_reset.c | 10 +-
drivers/gpu/drm/i915/gt/uc/Makefile | 5 +
.../gpu/drm/i915/gt/uc/Makefile.header-test | 16 +
drivers/gpu/drm/i915/{ => gt/uc}/intel_guc.c | 144 ++-----
drivers/gpu/drm/i915/{ => gt/uc}/intel_guc.h | 17 +-
.../gpu/drm/i915/{ => gt/uc}/intel_guc_ads.c | 3 +-
.../gpu/drm/i915/{ => gt/uc}/intel_guc_ads.h | 0
.../gpu/drm/i915/{ => gt/uc}/intel_guc_ct.c | 0
.../gpu/drm/i915/{ => gt/uc}/intel_guc_ct.h | 0
.../gpu/drm/i915/{ => gt/uc}/intel_guc_fw.c | 89 +++--
.../gpu/drm/i915/{ => gt/uc}/intel_guc_fw.h | 0
.../gpu/drm/i915/{ => gt/uc}/intel_guc_fwif.h | 0
.../gpu/drm/i915/{ => gt/uc}/intel_guc_log.c | 44 ++-
.../gpu/drm/i915/{ => gt/uc}/intel_guc_log.h | 0
.../gpu/drm/i915/{ => gt/uc}/intel_guc_reg.h | 32 +-
.../i915/{ => gt/uc}/intel_guc_submission.c | 358 ++----------------
.../i915/{ => gt/uc}/intel_guc_submission.h | 2 -
drivers/gpu/drm/i915/{ => gt/uc}/intel_huc.c | 32 +-
drivers/gpu/drm/i915/{ => gt/uc}/intel_huc.h | 6 -
.../gpu/drm/i915/{ => gt/uc}/intel_huc_fw.c | 12 +-
.../gpu/drm/i915/{ => gt/uc}/intel_huc_fw.h | 0
drivers/gpu/drm/i915/{ => gt/uc}/intel_uc.c | 237 ++++++------
drivers/gpu/drm/i915/{ => gt/uc}/intel_uc.h | 39 +-
.../gpu/drm/i915/{ => gt/uc}/intel_uc_fw.c | 4 +-
.../gpu/drm/i915/{ => gt/uc}/intel_uc_fw.h | 30 +-
.../intel_guc.c => gt/uc/selftest_guc.c} | 45 +--
drivers/gpu/drm/i915/i915_debugfs.c | 36 +-
drivers/gpu/drm/i915/i915_drv.c | 18 +-
drivers/gpu/drm/i915/i915_drv.h | 24 +-
drivers/gpu/drm/i915/i915_gem.c | 24 +-
drivers/gpu/drm/i915/i915_gem_gtt.c | 8 +-
drivers/gpu/drm/i915/i915_gem_gtt.h | 4 +-
drivers/gpu/drm/i915/i915_gpu_error.c | 11 +-
drivers/gpu/drm/i915/i915_gpu_error.h | 2 +-
drivers/gpu/drm/i915/i915_irq.c | 127 ++++---
drivers/gpu/drm/i915/i915_irq.h | 13 +-
drivers/gpu/drm/i915/i915_reg.h | 10 -
drivers/gpu/drm/i915/intel_wopcm.c | 4 +-
47 files changed, 556 insertions(+), 937 deletions(-)
create mode 100644 drivers/gpu/drm/i915/gt/uc/Makefile
create mode 100644 drivers/gpu/drm/i915/gt/uc/Makefile.header-test
rename drivers/gpu/drm/i915/{ => gt/uc}/intel_guc.c (78%)
rename drivers/gpu/drm/i915/{ => gt/uc}/intel_guc.h (92%)
rename drivers/gpu/drm/i915/{ => gt/uc}/intel_guc_ads.c (98%)
rename drivers/gpu/drm/i915/{ => gt/uc}/intel_guc_ads.h (100%)
rename drivers/gpu/drm/i915/{ => gt/uc}/intel_guc_ct.c (100%)
rename drivers/gpu/drm/i915/{ => gt/uc}/intel_guc_ct.h (100%)
rename drivers/gpu/drm/i915/{ => gt/uc}/intel_guc_fw.c (78%)
rename drivers/gpu/drm/i915/{ => gt/uc}/intel_guc_fw.h (100%)
rename drivers/gpu/drm/i915/{ => gt/uc}/intel_guc_fwif.h (100%)
rename drivers/gpu/drm/i915/{ => gt/uc}/intel_guc_log.c (92%)
rename drivers/gpu/drm/i915/{ => gt/uc}/intel_guc_log.h (100%)
rename drivers/gpu/drm/i915/{ => gt/uc}/intel_guc_reg.h (88%)
rename drivers/gpu/drm/i915/{ => gt/uc}/intel_guc_submission.c (74%)
rename drivers/gpu/drm/i915/{ => gt/uc}/intel_guc_submission.h (98%)
rename drivers/gpu/drm/i915/{ => gt/uc}/intel_huc.c (86%)
rename drivers/gpu/drm/i915/{ => gt/uc}/intel_huc.h (92%)
rename drivers/gpu/drm/i915/{ => gt/uc}/intel_huc_fw.c (95%)
rename drivers/gpu/drm/i915/{ => gt/uc}/intel_huc_fw.h (100%)
rename drivers/gpu/drm/i915/{ => gt/uc}/intel_uc.c (72%)
rename drivers/gpu/drm/i915/{ => gt/uc}/intel_uc.h (60%)
rename drivers/gpu/drm/i915/{ => gt/uc}/intel_uc_fw.c (99%)
rename drivers/gpu/drm/i915/{ => gt/uc}/intel_uc_fw.h (81%)
rename drivers/gpu/drm/i915/{selftests/intel_guc.c => gt/uc/selftest_guc.c} (86%)
--
2.20.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 28+ messages in thread
* [PATCH 01/12] drm/i915/guc: Remove preemption support for current fw
2019-07-10 0:54 [PATCH 00/12] GT-fy the uc code Daniele Ceraolo Spurio
@ 2019-07-10 0:54 ` Daniele Ceraolo Spurio
2019-07-10 15:45 ` Michał Winiarski
2019-07-10 0:54 ` [PATCH 02/12] drm/i915/guc: simplify guc client Daniele Ceraolo Spurio
` (14 subsequent siblings)
15 siblings, 1 reply; 28+ messages in thread
From: Daniele Ceraolo Spurio @ 2019-07-10 0:54 UTC (permalink / raw)
To: intel-gfx
From: Chris Wilson <chris@chris-wilson.co.uk>
Preemption via GuC submission is not being supported with its current
legacy incarnation. The current FW does support a similar pre-emption
flow via H2G, but it is class-based instead of being instance-based,
which doesn't fit well with the i915 tracking. To fix this, the
firmware is being updated to better support our needs with a new flow,
so we can safely remove the old code.
v2 (Daniele): resurrect & rebase, reword commit message, remove
preempt_context as well
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
Cc: Matthew Brost <matthew.brost@intel.com>
Cc: John Harrison <John.C.Harrison@Intel.com>
Acked-by: Matthew Brost <matthew.brost@intel.com>
---
drivers/gpu/drm/i915/gem/i915_gem_context.c | 17 --
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 13 --
drivers/gpu/drm/i915/gt/intel_engine_types.h | 1 -
drivers/gpu/drm/i915/gt/intel_gt_pm.c | 4 -
drivers/gpu/drm/i915/i915_debugfs.c | 5 -
drivers/gpu/drm/i915/i915_drv.h | 2 -
drivers/gpu/drm/i915/intel_guc.c | 31 ---
drivers/gpu/drm/i915/intel_guc.h | 9 -
drivers/gpu/drm/i915/intel_guc_submission.c | 231 +------------------
drivers/gpu/drm/i915/selftests/intel_guc.c | 31 +--
10 files changed, 14 insertions(+), 330 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c b/drivers/gpu/drm/i915/gem/i915_gem_context.c
index e367dce2a696..078592912d97 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
@@ -644,18 +644,12 @@ static void init_contexts(struct drm_i915_private *i915)
init_llist_head(&i915->contexts.free_list);
}
-static bool needs_preempt_context(struct drm_i915_private *i915)
-{
- return USES_GUC_SUBMISSION(i915);
-}
-
int i915_gem_contexts_init(struct drm_i915_private *dev_priv)
{
struct i915_gem_context *ctx;
/* Reassure ourselves we are only called once */
GEM_BUG_ON(dev_priv->kernel_context);
- GEM_BUG_ON(dev_priv->preempt_context);
init_contexts(dev_priv);
@@ -676,15 +670,6 @@ int i915_gem_contexts_init(struct drm_i915_private *dev_priv)
GEM_BUG_ON(!atomic_read(&ctx->hw_id_pin_count));
dev_priv->kernel_context = ctx;
- /* highest priority; preempting task */
- if (needs_preempt_context(dev_priv)) {
- ctx = i915_gem_context_create_kernel(dev_priv, INT_MAX);
- if (!IS_ERR(ctx))
- dev_priv->preempt_context = ctx;
- else
- DRM_ERROR("Failed to create preempt context; disabling preemption\n");
- }
-
DRM_DEBUG_DRIVER("%s context support initialized\n",
DRIVER_CAPS(dev_priv)->has_logical_contexts ?
"logical" : "fake");
@@ -695,8 +680,6 @@ void i915_gem_contexts_fini(struct drm_i915_private *i915)
{
lockdep_assert_held(&i915->drm.struct_mutex);
- if (i915->preempt_context)
- destroy_kernel_context(&i915->preempt_context);
destroy_kernel_context(&i915->kernel_context);
/* Must free all deferred contexts (via flush_workqueue) first */
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index bdf279fa3b2e..76b5c068a26d 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -841,15 +841,6 @@ int intel_engine_init_common(struct intel_engine_cs *engine)
if (ret)
return ret;
- /*
- * Similarly the preempt context must always be available so that
- * we can interrupt the engine at any time. However, as preemption
- * is optional, we allow it to fail.
- */
- if (i915->preempt_context)
- pin_context(i915->preempt_context, engine,
- &engine->preempt_context);
-
ret = measure_breadcrumb_dw(engine);
if (ret < 0)
goto err_unpin;
@@ -861,8 +852,6 @@ int intel_engine_init_common(struct intel_engine_cs *engine)
return 0;
err_unpin:
- if (engine->preempt_context)
- intel_context_unpin(engine->preempt_context);
intel_context_unpin(engine->kernel_context);
return ret;
}
@@ -887,8 +876,6 @@ void intel_engine_cleanup_common(struct intel_engine_cs *engine)
if (engine->default_state)
i915_gem_object_put(engine->default_state);
- if (engine->preempt_context)
- intel_context_unpin(engine->preempt_context);
intel_context_unpin(engine->kernel_context);
GEM_BUG_ON(!llist_empty(&engine->barrier_tasks));
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h b/drivers/gpu/drm/i915/gt/intel_engine_types.h
index 7e056114344e..8be63019d707 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h
@@ -288,7 +288,6 @@ struct intel_engine_cs {
struct llist_head barrier_tasks;
struct intel_context *kernel_context; /* pinned */
- struct intel_context *preempt_context; /* pinned; optional */
intel_engine_mask_t saturated; /* submitting semaphores too late? */
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm.c b/drivers/gpu/drm/i915/gt/intel_gt_pm.c
index 36ba80e6a0b7..da81b3a92d16 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_pm.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_pm.c
@@ -145,10 +145,6 @@ int intel_gt_resume(struct intel_gt *gt)
if (ce)
ce->ops->reset(ce);
- ce = engine->preempt_context;
- if (ce)
- ce->ops->reset(ce);
-
engine->serial++; /* kernel context lost */
err = engine->resume(engine);
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 3e4f58f19362..b4d195677877 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2010,11 +2010,6 @@ static int i915_guc_info(struct seq_file *m, void *data)
seq_printf(m, "\nGuC execbuf client @ %p:\n", guc->execbuf_client);
i915_guc_client_info(m, dev_priv, guc->execbuf_client);
- if (guc->preempt_client) {
- seq_printf(m, "\nGuC preempt client @ %p:\n",
- guc->preempt_client);
- i915_guc_client_info(m, dev_priv, guc->preempt_client);
- }
/* Add more as required ... */
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index f9878cbef4d9..76116e44b7e1 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1378,8 +1378,6 @@ struct drm_i915_private {
struct intel_engine_cs *engine[I915_NUM_ENGINES];
/* Context used internally to idle the GPU and setup initial state */
struct i915_gem_context *kernel_context;
- /* Context only to be used for injecting preemption commands */
- struct i915_gem_context *preempt_context;
struct intel_engine_cs *engine_class[MAX_ENGINE_CLASS + 1]
[MAX_ENGINE_INSTANCE + 1];
diff --git a/drivers/gpu/drm/i915/intel_guc.c b/drivers/gpu/drm/i915/intel_guc.c
index c40a6efdd33a..501b74f44374 100644
--- a/drivers/gpu/drm/i915/intel_guc.c
+++ b/drivers/gpu/drm/i915/intel_guc.c
@@ -101,8 +101,6 @@ void intel_guc_init_early(struct intel_guc *guc)
static int guc_init_wq(struct intel_guc *guc)
{
- struct drm_i915_private *dev_priv = guc_to_i915(guc);
-
/*
* GuC log buffer flush work item has to do register access to
* send the ack to GuC and this work item, if not synced before
@@ -122,31 +120,6 @@ static int guc_init_wq(struct intel_guc *guc)
return -ENOMEM;
}
- /*
- * Even though both sending GuC action, and adding a new workitem to
- * GuC workqueue are serialized (each with its own locking), since
- * we're using mutliple engines, it's possible that we're going to
- * issue a preempt request with two (or more - each for different
- * engine) workitems in GuC queue. In this situation, GuC may submit
- * all of them, which will make us very confused.
- * Our preemption contexts may even already be complete - before we
- * even had the chance to sent the preempt action to GuC!. Rather
- * than introducing yet another lock, we can just use ordered workqueue
- * to make sure we're always sending a single preemption request with a
- * single workitem.
- */
- if (HAS_LOGICAL_RING_PREEMPTION(dev_priv) &&
- USES_GUC_SUBMISSION(dev_priv)) {
- guc->preempt_wq = alloc_ordered_workqueue("i915-guc_preempt",
- WQ_HIGHPRI);
- if (!guc->preempt_wq) {
- destroy_workqueue(guc->log.relay.flush_wq);
- DRM_ERROR("Couldn't allocate workqueue for GuC "
- "preemption\n");
- return -ENOMEM;
- }
- }
-
return 0;
}
@@ -154,10 +127,6 @@ static void guc_fini_wq(struct intel_guc *guc)
{
struct workqueue_struct *wq;
- wq = fetch_and_zero(&guc->preempt_wq);
- if (wq)
- destroy_workqueue(wq);
-
wq = fetch_and_zero(&guc->log.relay.flush_wq);
if (wq)
destroy_workqueue(wq);
diff --git a/drivers/gpu/drm/i915/intel_guc.h b/drivers/gpu/drm/i915/intel_guc.h
index d91c96679dbb..ec1038c1f50e 100644
--- a/drivers/gpu/drm/i915/intel_guc.h
+++ b/drivers/gpu/drm/i915/intel_guc.h
@@ -37,11 +37,6 @@
struct __guc_ads_blob;
-struct guc_preempt_work {
- struct work_struct work;
- struct intel_engine_cs *engine;
-};
-
/*
* Top level structure of GuC. It handles firmware loading and manages client
* pool and doorbells. intel_guc owns a intel_guc_client to replace the legacy
@@ -76,10 +71,6 @@ struct intel_guc {
void *shared_data_vaddr;
struct intel_guc_client *execbuf_client;
- struct intel_guc_client *preempt_client;
-
- struct guc_preempt_work preempt_work[I915_NUM_ENGINES];
- struct workqueue_struct *preempt_wq;
DECLARE_BITMAP(doorbell_bitmap, GUC_NUM_DOORBELLS);
/* Cyclic counter mod pagesize */
diff --git a/drivers/gpu/drm/i915/intel_guc_submission.c b/drivers/gpu/drm/i915/intel_guc_submission.c
index f104b94c14ef..8520bb224175 100644
--- a/drivers/gpu/drm/i915/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/intel_guc_submission.c
@@ -46,11 +46,10 @@ enum {
*
* GuC client:
* A intel_guc_client refers to a submission path through GuC. Currently, there
- * are two clients. One of them (the execbuf_client) is charged with all
- * submissions to the GuC, the other one (preempt_client) is responsible for
- * preempting the execbuf_client. This struct is the owner of a doorbell, a
- * process descriptor and a workqueue (all of them inside a single gem object
- * that contains all required pages for these elements).
+ * is only one client, which is charged with all submissions to the GuC. This
+ * struct is the owner of a doorbell, a process descriptor and a workqueue (all
+ * of them inside a single gem object that contains all required pages for these
+ * elements).
*
* GuC stage descriptor:
* During initialization, the driver allocates a static pool of 1024 such
@@ -88,12 +87,6 @@ enum {
*
*/
-static inline u32 intel_hws_preempt_done_address(struct intel_engine_cs *engine)
-{
- return (i915_ggtt_offset(engine->status_page.vma) +
- I915_GEM_HWS_PREEMPT_ADDR);
-}
-
static inline struct i915_priolist *to_priolist(struct rb_node *rb)
{
return rb_entry(rb, struct i915_priolist, node);
@@ -563,126 +556,6 @@ static void flush_ggtt_writes(struct i915_vma *vma)
intel_uncore_posting_read_fw(&i915->uncore, GUC_STATUS);
}
-static void inject_preempt_context(struct work_struct *work)
-{
- struct guc_preempt_work *preempt_work =
- container_of(work, typeof(*preempt_work), work);
- struct intel_engine_cs *engine = preempt_work->engine;
- struct intel_guc *guc = container_of(preempt_work, typeof(*guc),
- preempt_work[engine->id]);
- struct intel_guc_client *client = guc->preempt_client;
- struct guc_stage_desc *stage_desc = __get_stage_desc(client);
- struct intel_context *ce = engine->preempt_context;
- u32 data[7];
-
- if (!ce->ring->emit) { /* recreate upon load/resume */
- u32 addr = intel_hws_preempt_done_address(engine);
- u32 *cs;
-
- cs = ce->ring->vaddr;
- if (engine->class == RENDER_CLASS) {
- cs = gen8_emit_ggtt_write_rcs(cs,
- GUC_PREEMPT_FINISHED,
- addr,
- PIPE_CONTROL_CS_STALL);
- } else {
- cs = gen8_emit_ggtt_write(cs,
- GUC_PREEMPT_FINISHED,
- addr,
- 0);
- *cs++ = MI_NOOP;
- *cs++ = MI_NOOP;
- }
- *cs++ = MI_USER_INTERRUPT;
- *cs++ = MI_NOOP;
-
- ce->ring->emit = GUC_PREEMPT_BREADCRUMB_BYTES;
- GEM_BUG_ON((void *)cs - ce->ring->vaddr != ce->ring->emit);
-
- flush_ggtt_writes(ce->ring->vma);
- }
-
- spin_lock_irq(&client->wq_lock);
- guc_wq_item_append(client, engine->guc_id, lower_32_bits(ce->lrc_desc),
- GUC_PREEMPT_BREADCRUMB_BYTES / sizeof(u64), 0);
- spin_unlock_irq(&client->wq_lock);
-
- /*
- * If GuC firmware performs an engine reset while that engine had
- * a preemption pending, it will set the terminated attribute bit
- * on our preemption stage descriptor. GuC firmware retains all
- * pending work items for a high-priority GuC client, unlike the
- * normal-priority GuC client where work items are dropped. It
- * wants to make sure the preempt-to-idle work doesn't run when
- * scheduling resumes, and uses this bit to inform its scheduler
- * and presumably us as well. Our job is to clear it for the next
- * preemption after reset, otherwise that and future preemptions
- * will never complete. We'll just clear it every time.
- */
- stage_desc->attribute &= ~GUC_STAGE_DESC_ATTR_TERMINATED;
-
- data[0] = INTEL_GUC_ACTION_REQUEST_PREEMPTION;
- data[1] = client->stage_id;
- data[2] = INTEL_GUC_PREEMPT_OPTION_DROP_WORK_Q |
- INTEL_GUC_PREEMPT_OPTION_DROP_SUBMIT_Q;
- data[3] = engine->guc_id;
- data[4] = guc->execbuf_client->priority;
- data[5] = guc->execbuf_client->stage_id;
- data[6] = intel_guc_ggtt_offset(guc, guc->shared_data);
-
- if (WARN_ON(intel_guc_send(guc, data, ARRAY_SIZE(data)))) {
- intel_write_status_page(engine,
- I915_GEM_HWS_PREEMPT,
- GUC_PREEMPT_NONE);
- tasklet_schedule(&engine->execlists.tasklet);
- }
-
- (void)I915_SELFTEST_ONLY(engine->execlists.preempt_hang.count++);
-}
-
-/*
- * We're using user interrupt and HWSP value to mark that preemption has
- * finished and GPU is idle. Normally, we could unwind and continue similar to
- * execlists submission path. Unfortunately, with GuC we also need to wait for
- * it to finish its own postprocessing, before attempting to submit. Otherwise
- * GuC may silently ignore our submissions, and thus we risk losing request at
- * best, executing out-of-order and causing kernel panic at worst.
- */
-#define GUC_PREEMPT_POSTPROCESS_DELAY_MS 10
-static void wait_for_guc_preempt_report(struct intel_engine_cs *engine)
-{
- struct intel_guc *guc = &engine->i915->guc;
- struct guc_shared_ctx_data *data = guc->shared_data_vaddr;
- struct guc_ctx_report *report =
- &data->preempt_ctx_report[engine->guc_id];
-
- if (wait_for_atomic(report->report_return_status ==
- INTEL_GUC_REPORT_STATUS_COMPLETE,
- GUC_PREEMPT_POSTPROCESS_DELAY_MS))
- DRM_ERROR("Timed out waiting for GuC preemption report\n");
- /*
- * GuC is expecting that we're also going to clear the affected context
- * counter, let's also reset the return status to not depend on GuC
- * resetting it after recieving another preempt action
- */
- report->affected_count = 0;
- report->report_return_status = INTEL_GUC_REPORT_STATUS_UNKNOWN;
-}
-
-static void complete_preempt_context(struct intel_engine_cs *engine)
-{
- struct intel_engine_execlists *execlists = &engine->execlists;
-
- if (inject_preempt_hang(execlists))
- return;
-
- execlists_cancel_port_requests(execlists);
- execlists_unwind_incomplete_requests(execlists);
-
- wait_for_guc_preempt_report(engine);
- intel_write_status_page(engine, I915_GEM_HWS_PREEMPT, GUC_PREEMPT_NONE);
-}
-
static void guc_submit(struct intel_engine_cs *engine,
struct i915_request **out,
struct i915_request **end)
@@ -707,16 +580,6 @@ static inline int rq_prio(const struct i915_request *rq)
return rq->sched.attr.priority | __NO_PREEMPTION;
}
-static inline int effective_prio(const struct i915_request *rq)
-{
- int prio = rq_prio(rq);
-
- if (i915_request_has_nopreempt(rq))
- prio = I915_PRIORITY_UNPREEMPTABLE;
-
- return prio;
-}
-
static struct i915_request *schedule_in(struct i915_request *rq, int idx)
{
trace_i915_request_in(rq, idx);
@@ -752,22 +615,6 @@ static void __guc_dequeue(struct intel_engine_cs *engine)
lockdep_assert_held(&engine->active.lock);
if (last) {
- if (intel_engine_has_preemption(engine)) {
- struct guc_preempt_work *preempt_work =
- &engine->i915->guc.preempt_work[engine->id];
- int prio = execlists->queue_priority_hint;
-
- if (i915_scheduler_need_preempt(prio,
- effective_prio(last))) {
- intel_write_status_page(engine,
- I915_GEM_HWS_PREEMPT,
- GUC_PREEMPT_INPROGRESS);
- queue_work(engine->i915->guc.preempt_wq,
- &preempt_work->work);
- return;
- }
- }
-
if (*++first)
return;
@@ -831,12 +678,7 @@ static void guc_submission_tasklet(unsigned long data)
memmove(execlists->inflight, port, rem * sizeof(*port));
}
- if (intel_read_status_page(engine, I915_GEM_HWS_PREEMPT) ==
- GUC_PREEMPT_FINISHED)
- complete_preempt_context(engine);
-
- if (!intel_read_status_page(engine, I915_GEM_HWS_PREEMPT))
- __guc_dequeue(engine);
+ __guc_dequeue(engine);
spin_unlock_irqrestore(&engine->active.lock, flags);
}
@@ -857,16 +699,6 @@ static void guc_reset_prepare(struct intel_engine_cs *engine)
* prevents the race.
*/
__tasklet_disable_sync_once(&execlists->tasklet);
-
- /*
- * We're using worker to queue preemption requests from the tasklet in
- * GuC submission mode.
- * Even though tasklet was disabled, we may still have a worker queued.
- * Let's make sure that all workers scheduled before disabling the
- * tasklet are completed before continuing with the reset.
- */
- if (engine->i915->guc.preempt_wq)
- flush_workqueue(engine->i915->guc.preempt_wq);
}
static void guc_reset(struct intel_engine_cs *engine, bool stalled)
@@ -1123,7 +955,6 @@ static int guc_clients_create(struct intel_guc *guc)
struct intel_guc_client *client;
GEM_BUG_ON(guc->execbuf_client);
- GEM_BUG_ON(guc->preempt_client);
client = guc_client_alloc(dev_priv,
INTEL_INFO(dev_priv)->engine_mask,
@@ -1135,20 +966,6 @@ static int guc_clients_create(struct intel_guc *guc)
}
guc->execbuf_client = client;
- if (dev_priv->preempt_context) {
- client = guc_client_alloc(dev_priv,
- INTEL_INFO(dev_priv)->engine_mask,
- GUC_CLIENT_PRIORITY_KMD_HIGH,
- dev_priv->preempt_context);
- if (IS_ERR(client)) {
- DRM_ERROR("Failed to create GuC client for preemption!\n");
- guc_client_free(guc->execbuf_client);
- guc->execbuf_client = NULL;
- return PTR_ERR(client);
- }
- guc->preempt_client = client;
- }
-
return 0;
}
@@ -1156,10 +973,6 @@ static void guc_clients_destroy(struct intel_guc *guc)
{
struct intel_guc_client *client;
- client = fetch_and_zero(&guc->preempt_client);
- if (client)
- guc_client_free(client);
-
client = fetch_and_zero(&guc->execbuf_client);
if (client)
guc_client_free(client);
@@ -1202,28 +1015,11 @@ static void __guc_client_disable(struct intel_guc_client *client)
static int guc_clients_enable(struct intel_guc *guc)
{
- int ret;
-
- ret = __guc_client_enable(guc->execbuf_client);
- if (ret)
- return ret;
-
- if (guc->preempt_client) {
- ret = __guc_client_enable(guc->preempt_client);
- if (ret) {
- __guc_client_disable(guc->execbuf_client);
- return ret;
- }
- }
-
- return 0;
+ return __guc_client_enable(guc->execbuf_client);
}
static void guc_clients_disable(struct intel_guc *guc)
{
- if (guc->preempt_client)
- __guc_client_disable(guc->preempt_client);
-
if (guc->execbuf_client)
__guc_client_disable(guc->execbuf_client);
}
@@ -1234,9 +1030,6 @@ static void guc_clients_disable(struct intel_guc *guc)
*/
int intel_guc_submission_init(struct intel_guc *guc)
{
- struct drm_i915_private *dev_priv = guc_to_i915(guc);
- struct intel_engine_cs *engine;
- enum intel_engine_id id;
int ret;
if (guc->stage_desc_pool)
@@ -1256,11 +1049,6 @@ int intel_guc_submission_init(struct intel_guc *guc)
if (ret)
goto err_pool;
- for_each_engine(engine, dev_priv, id) {
- guc->preempt_work[id].engine = engine;
- INIT_WORK(&guc->preempt_work[id].work, inject_preempt_context);
- }
-
return 0;
err_pool:
@@ -1270,13 +1058,6 @@ int intel_guc_submission_init(struct intel_guc *guc)
void intel_guc_submission_fini(struct intel_guc *guc)
{
- struct drm_i915_private *dev_priv = guc_to_i915(guc);
- struct intel_engine_cs *engine;
- enum intel_engine_id id;
-
- for_each_engine(engine, dev_priv, id)
- cancel_work_sync(&guc->preempt_work[id].work);
-
guc_clients_destroy(guc);
WARN_ON(!guc_verify_doorbells(guc));
diff --git a/drivers/gpu/drm/i915/selftests/intel_guc.c b/drivers/gpu/drm/i915/selftests/intel_guc.c
index 6ca8584cd64c..1a1915e44f6b 100644
--- a/drivers/gpu/drm/i915/selftests/intel_guc.c
+++ b/drivers/gpu/drm/i915/selftests/intel_guc.c
@@ -103,13 +103,10 @@ static int ring_doorbell_nop(struct intel_guc_client *client)
/*
* Basic client sanity check, handy to validate create_clients.
*/
-static int validate_client(struct intel_guc_client *client,
- int client_priority,
- bool is_preempt_client)
+static int validate_client(struct intel_guc_client *client, int client_priority)
{
struct drm_i915_private *dev_priv = guc_to_i915(client->guc);
- struct i915_gem_context *ctx_owner = is_preempt_client ?
- dev_priv->preempt_context : dev_priv->kernel_context;
+ struct i915_gem_context *ctx_owner = dev_priv->kernel_context;
if (client->owner != ctx_owner ||
client->engines != INTEL_INFO(dev_priv)->engine_mask ||
@@ -163,7 +160,7 @@ static int igt_guc_clients(void *args)
*/
guc_clients_disable(guc);
guc_clients_destroy(guc);
- if (guc->execbuf_client || guc->preempt_client) {
+ if (guc->execbuf_client) {
pr_err("guc_clients_destroy lied!\n");
err = -EINVAL;
goto unlock;
@@ -177,24 +174,14 @@ static int igt_guc_clients(void *args)
GEM_BUG_ON(!guc->execbuf_client);
err = validate_client(guc->execbuf_client,
- GUC_CLIENT_PRIORITY_KMD_NORMAL, false);
+ GUC_CLIENT_PRIORITY_KMD_NORMAL);
if (err) {
pr_err("execbug client validation failed\n");
goto out;
}
- if (guc->preempt_client) {
- err = validate_client(guc->preempt_client,
- GUC_CLIENT_PRIORITY_KMD_HIGH, true);
- if (err) {
- pr_err("preempt client validation failed\n");
- goto out;
- }
- }
-
- /* each client should now have reserved a doorbell */
- if (!has_doorbell(guc->execbuf_client) ||
- (guc->preempt_client && !has_doorbell(guc->preempt_client))) {
+ /* the client should now have reserved a doorbell */
+ if (!has_doorbell(guc->execbuf_client)) {
pr_err("guc_clients_create didn't reserve doorbells\n");
err = -EINVAL;
goto out;
@@ -204,8 +191,7 @@ static int igt_guc_clients(void *args)
guc_clients_enable(guc);
/* each client should now have received a doorbell */
- if (!client_doorbell_in_sync(guc->execbuf_client) ||
- !client_doorbell_in_sync(guc->preempt_client)) {
+ if (!client_doorbell_in_sync(guc->execbuf_client)) {
pr_err("failed to initialize the doorbells\n");
err = -EINVAL;
goto out;
@@ -300,8 +286,7 @@ static int igt_guc_doorbells(void *arg)
goto out;
}
- err = validate_client(clients[i],
- i % GUC_CLIENT_PRIORITY_NUM, false);
+ err = validate_client(clients[i], i % GUC_CLIENT_PRIORITY_NUM);
if (err) {
pr_err("[%d] client_alloc sanity check failed!\n", i);
err = -EINVAL;
--
2.20.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH 02/12] drm/i915/guc: simplify guc client
2019-07-10 0:54 [PATCH 00/12] GT-fy the uc code Daniele Ceraolo Spurio
2019-07-10 0:54 ` [PATCH 01/12] drm/i915/guc: Remove preemption support for current fw Daniele Ceraolo Spurio
@ 2019-07-10 0:54 ` Daniele Ceraolo Spurio
2019-07-10 15:52 ` Michał Winiarski
2019-07-10 0:54 ` [PATCH 03/12] drm/i915/uc: replace uc init/fini misc Daniele Ceraolo Spurio
` (13 subsequent siblings)
15 siblings, 1 reply; 28+ messages in thread
From: Daniele Ceraolo Spurio @ 2019-07-10 0:54 UTC (permalink / raw)
To: intel-gfx; +Cc: Matthew Brost
We originally added support, in some cases partial, for different modes
of operations via guc clients:
- proxy vs direct submission;
- variable engine mask per-client.
We only ever used one flow (all submissions via a single proxy), so the
other code paths haven't been exercised and are most likely
non-functional. The guc firmware interface is also in the process of
being updated to better fit the i915 flow and our client abstraction
will need to change accordingly (or possibly go away entirely), so these
old unused paths can be considered dead and removed.
Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
Cc: Matthew Brost <matthew.brost@intel.com>
Cc: John Harrison <John.C.Harrison@Intel.com>
Acked-by: Matthew Brost <Matthew Brost <matthew.brost@intel.com>
---
drivers/gpu/drm/i915/i915_debugfs.c | 3 +-
drivers/gpu/drm/i915/intel_guc_submission.c | 73 ++-------------------
drivers/gpu/drm/i915/intel_guc_submission.h | 2 -
drivers/gpu/drm/i915/selftests/intel_guc.c | 12 +---
4 files changed, 8 insertions(+), 82 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index b4d195677877..dc65a6131a5b 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2021,7 +2021,6 @@ static int i915_guc_stage_pool(struct seq_file *m, void *data)
struct drm_i915_private *dev_priv = node_to_i915(m->private);
const struct intel_guc *guc = &dev_priv->guc;
struct guc_stage_desc *desc = guc->stage_desc_pool_vaddr;
- struct intel_guc_client *client = guc->execbuf_client;
intel_engine_mask_t tmp;
int index;
@@ -2051,7 +2050,7 @@ static int i915_guc_stage_pool(struct seq_file *m, void *data)
desc->wq_addr, desc->wq_size);
seq_putc(m, '\n');
- for_each_engine_masked(engine, dev_priv, client->engines, tmp) {
+ for_each_engine(engine, dev_priv, tmp) {
u32 guc_engine_id = engine->guc_id;
struct guc_execlist_context *lrc =
&desc->lrc[guc_engine_id];
diff --git a/drivers/gpu/drm/i915/intel_guc_submission.c b/drivers/gpu/drm/i915/intel_guc_submission.c
index 8520bb224175..30692f8289bd 100644
--- a/drivers/gpu/drm/i915/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/intel_guc_submission.c
@@ -363,10 +363,7 @@ static void guc_stage_desc_pool_destroy(struct intel_guc *guc)
static void guc_stage_desc_init(struct intel_guc_client *client)
{
struct intel_guc *guc = client->guc;
- struct i915_gem_context *ctx = client->owner;
- struct i915_gem_engines_iter it;
struct guc_stage_desc *desc;
- struct intel_context *ce;
u32 gfx_addr;
desc = __get_stage_desc(client);
@@ -380,55 +377,6 @@ static void guc_stage_desc_init(struct intel_guc_client *client)
desc->priority = client->priority;
desc->db_id = client->doorbell_id;
- for_each_gem_engine(ce, i915_gem_context_lock_engines(ctx), it) {
- struct guc_execlist_context *lrc;
-
- if (!(ce->engine->mask & client->engines))
- continue;
-
- /* TODO: We have a design issue to be solved here. Only when we
- * receive the first batch, we know which engine is used by the
- * user. But here GuC expects the lrc and ring to be pinned. It
- * is not an issue for default context, which is the only one
- * for now who owns a GuC client. But for future owner of GuC
- * client, need to make sure lrc is pinned prior to enter here.
- */
- if (!ce->state)
- break; /* XXX: continue? */
-
- /*
- * XXX: When this is a GUC_STAGE_DESC_ATTR_KERNEL client (proxy
- * submission or, in other words, not using a direct submission
- * model) the KMD's LRCA is not used for any work submission.
- * Instead, the GuC uses the LRCA of the user mode context (see
- * guc_add_request below).
- */
- lrc = &desc->lrc[ce->engine->guc_id];
- lrc->context_desc = lower_32_bits(ce->lrc_desc);
-
- /* The state page is after PPHWSP */
- lrc->ring_lrca = intel_guc_ggtt_offset(guc, ce->state) +
- LRC_STATE_PN * PAGE_SIZE;
-
- /* XXX: In direct submission, the GuC wants the HW context id
- * here. In proxy submission, it wants the stage id
- */
- lrc->context_id = (client->stage_id << GUC_ELC_CTXID_OFFSET) |
- (ce->engine->guc_id << GUC_ELC_ENGINE_OFFSET);
-
- lrc->ring_begin = intel_guc_ggtt_offset(guc, ce->ring->vma);
- lrc->ring_end = lrc->ring_begin + ce->ring->size - 1;
- lrc->ring_next_free_location = lrc->ring_begin;
- lrc->ring_current_tail_pointer_value = 0;
-
- desc->engines_used |= BIT(ce->engine->guc_id);
- }
- i915_gem_context_unlock_engines(ctx);
-
- DRM_DEBUG_DRIVER("Host engines 0x%x => GuC engines used 0x%x\n",
- client->engines, desc->engines_used);
- WARN_ON(desc->engines_used == 0);
-
/*
* The doorbell, process descriptor, and workqueue are all parts
* of the client object, which the GuC will reference via the GGTT
@@ -836,8 +784,7 @@ static bool guc_verify_doorbells(struct intel_guc *guc)
/**
* guc_client_alloc() - Allocate an intel_guc_client
- * @dev_priv: driver private data structure
- * @engines: The set of engines to enable for this client
+ * @guc: the intel_guc structure
* @priority: four levels priority _CRITICAL, _HIGH, _NORMAL and _LOW
* The kernel client to replace ExecList submission is created with
* NORMAL priority. Priority of a client for scheduler can be HIGH,
@@ -848,13 +795,9 @@ static bool guc_verify_doorbells(struct intel_guc *guc)
* Return: An intel_guc_client object if success, else NULL.
*/
static struct intel_guc_client *
-guc_client_alloc(struct drm_i915_private *dev_priv,
- u32 engines,
- u32 priority,
- struct i915_gem_context *ctx)
+guc_client_alloc(struct intel_guc *guc, u32 priority)
{
struct intel_guc_client *client;
- struct intel_guc *guc = &dev_priv->guc;
struct i915_vma *vma;
void *vaddr;
int ret;
@@ -864,8 +807,6 @@ guc_client_alloc(struct drm_i915_private *dev_priv,
return ERR_PTR(-ENOMEM);
client->guc = guc;
- client->owner = ctx;
- client->engines = engines;
client->priority = priority;
client->doorbell_id = GUC_DOORBELL_INVALID;
spin_lock_init(&client->wq_lock);
@@ -910,8 +851,8 @@ guc_client_alloc(struct drm_i915_private *dev_priv,
else
client->proc_desc_offset = (GUC_DB_SIZE / 2);
- DRM_DEBUG_DRIVER("new priority %u client %p for engine(s) 0x%x: stage_id %u\n",
- priority, client, client->engines, client->stage_id);
+ DRM_DEBUG_DRIVER("new priority %u client %p: stage_id %u\n",
+ priority, client, client->stage_id);
DRM_DEBUG_DRIVER("doorbell id %u, cacheline offset 0x%lx\n",
client->doorbell_id, client->doorbell_offset);
@@ -951,15 +892,11 @@ static inline bool ctx_save_restore_disabled(struct intel_context *ce)
static int guc_clients_create(struct intel_guc *guc)
{
- struct drm_i915_private *dev_priv = guc_to_i915(guc);
struct intel_guc_client *client;
GEM_BUG_ON(guc->execbuf_client);
- client = guc_client_alloc(dev_priv,
- INTEL_INFO(dev_priv)->engine_mask,
- GUC_CLIENT_PRIORITY_KMD_NORMAL,
- dev_priv->kernel_context);
+ client = guc_client_alloc(guc, GUC_CLIENT_PRIORITY_KMD_NORMAL);
if (IS_ERR(client)) {
DRM_ERROR("Failed to create GuC client for submission!\n");
return PTR_ERR(client);
diff --git a/drivers/gpu/drm/i915/intel_guc_submission.h b/drivers/gpu/drm/i915/intel_guc_submission.h
index 7d823a513b9c..87a38cb6faf3 100644
--- a/drivers/gpu/drm/i915/intel_guc_submission.h
+++ b/drivers/gpu/drm/i915/intel_guc_submission.h
@@ -58,11 +58,9 @@ struct drm_i915_private;
struct intel_guc_client {
struct i915_vma *vma;
void *vaddr;
- struct i915_gem_context *owner;
struct intel_guc *guc;
/* bitmap of (host) engine ids */
- u32 engines;
u32 priority;
u32 stage_id;
u32 proc_desc_offset;
diff --git a/drivers/gpu/drm/i915/selftests/intel_guc.c b/drivers/gpu/drm/i915/selftests/intel_guc.c
index 1a1915e44f6b..6ca76f5a98d4 100644
--- a/drivers/gpu/drm/i915/selftests/intel_guc.c
+++ b/drivers/gpu/drm/i915/selftests/intel_guc.c
@@ -105,12 +105,7 @@ static int ring_doorbell_nop(struct intel_guc_client *client)
*/
static int validate_client(struct intel_guc_client *client, int client_priority)
{
- struct drm_i915_private *dev_priv = guc_to_i915(client->guc);
- struct i915_gem_context *ctx_owner = dev_priv->kernel_context;
-
- if (client->owner != ctx_owner ||
- client->engines != INTEL_INFO(dev_priv)->engine_mask ||
- client->priority != client_priority ||
+ if (client->priority != client_priority ||
client->doorbell_id == GUC_DOORBELL_INVALID)
return -EINVAL;
else
@@ -247,10 +242,7 @@ static int igt_guc_doorbells(void *arg)
goto unlock;
for (i = 0; i < ATTEMPTS; i++) {
- clients[i] = guc_client_alloc(dev_priv,
- INTEL_INFO(dev_priv)->engine_mask,
- i % GUC_CLIENT_PRIORITY_NUM,
- dev_priv->kernel_context);
+ clients[i] = guc_client_alloc(guc, i % GUC_CLIENT_PRIORITY_NUM);
if (!clients[i]) {
pr_err("[%d] No guc client\n", i);
--
2.20.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH 03/12] drm/i915/uc: replace uc init/fini misc
2019-07-10 0:54 [PATCH 00/12] GT-fy the uc code Daniele Ceraolo Spurio
2019-07-10 0:54 ` [PATCH 01/12] drm/i915/guc: Remove preemption support for current fw Daniele Ceraolo Spurio
2019-07-10 0:54 ` [PATCH 02/12] drm/i915/guc: simplify guc client Daniele Ceraolo Spurio
@ 2019-07-10 0:54 ` Daniele Ceraolo Spurio
2019-07-10 0:54 ` [PATCH 04/12] drm/i915/uc: introduce intel_uc_fw_supported Daniele Ceraolo Spurio
` (12 subsequent siblings)
15 siblings, 0 replies; 28+ messages in thread
From: Daniele Ceraolo Spurio @ 2019-07-10 0:54 UTC (permalink / raw)
To: intel-gfx
The "misc" terminology doesn't clearly explain what we intend to cover
in this phase. The only thing we do in there apart from FW fetch is
initializing the log workqueue, with the latter being required only in
the very rare case where we enable the log relay. To clean this up, we
can move the wq init to when the relay is enabled and rename the
function to clarify that they only fetch/release the blobs.
v2: only create log wq when needed (Michal), reword commit msg
accordingly
Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
---
drivers/gpu/drm/i915/i915_gem.c | 12 +++----
drivers/gpu/drm/i915/intel_guc.c | 53 ----------------------------
drivers/gpu/drm/i915/intel_guc.h | 2 --
drivers/gpu/drm/i915/intel_guc_log.c | 31 +++++++++++++++-
drivers/gpu/drm/i915/intel_huc.c | 8 -----
drivers/gpu/drm/i915/intel_huc.h | 6 ----
drivers/gpu/drm/i915/intel_uc.c | 34 +++++-------------
drivers/gpu/drm/i915/intel_uc.h | 4 +--
8 files changed, 45 insertions(+), 105 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 7ade42b8ec99..e6e8e4d5ebb1 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -1433,13 +1433,11 @@ int i915_gem_init(struct drm_i915_private *dev_priv)
if (ret)
return ret;
- ret = intel_uc_init_misc(dev_priv);
- if (ret)
- return ret;
+ intel_uc_fetch_firmwares(dev_priv);
ret = intel_wopcm_init(&dev_priv->wopcm);
if (ret)
- goto err_uc_misc;
+ goto err_uc_fw;
/* This is just a security blanket to placate dragons.
* On some systems, we very sporadically observe that the first TLBs
@@ -1565,8 +1563,8 @@ int i915_gem_init(struct drm_i915_private *dev_priv)
intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL);
mutex_unlock(&dev_priv->drm.struct_mutex);
-err_uc_misc:
- intel_uc_fini_misc(dev_priv);
+err_uc_fw:
+ intel_uc_cleanup_firmwares(dev_priv);
if (ret != -EIO) {
i915_gem_cleanup_userptr(dev_priv);
@@ -1632,7 +1630,7 @@ void i915_gem_fini(struct drm_i915_private *dev_priv)
intel_cleanup_gt_powersave(dev_priv);
- intel_uc_fini_misc(dev_priv);
+ intel_uc_cleanup_firmwares(dev_priv);
i915_gem_cleanup_userptr(dev_priv);
intel_timelines_fini(dev_priv);
diff --git a/drivers/gpu/drm/i915/intel_guc.c b/drivers/gpu/drm/i915/intel_guc.c
index 501b74f44374..4173b35bf104 100644
--- a/drivers/gpu/drm/i915/intel_guc.c
+++ b/drivers/gpu/drm/i915/intel_guc.c
@@ -99,59 +99,6 @@ void intel_guc_init_early(struct intel_guc *guc)
}
}
-static int guc_init_wq(struct intel_guc *guc)
-{
- /*
- * GuC log buffer flush work item has to do register access to
- * send the ack to GuC and this work item, if not synced before
- * suspend, can potentially get executed after the GFX device is
- * suspended.
- * By marking the WQ as freezable, we don't have to bother about
- * flushing of this work item from the suspend hooks, the pending
- * work item if any will be either executed before the suspend
- * or scheduled later on resume. This way the handling of work
- * item can be kept same between system suspend & rpm suspend.
- */
- guc->log.relay.flush_wq =
- alloc_ordered_workqueue("i915-guc_log",
- WQ_HIGHPRI | WQ_FREEZABLE);
- if (!guc->log.relay.flush_wq) {
- DRM_ERROR("Couldn't allocate workqueue for GuC log\n");
- return -ENOMEM;
- }
-
- return 0;
-}
-
-static void guc_fini_wq(struct intel_guc *guc)
-{
- struct workqueue_struct *wq;
-
- wq = fetch_and_zero(&guc->log.relay.flush_wq);
- if (wq)
- destroy_workqueue(wq);
-}
-
-int intel_guc_init_misc(struct intel_guc *guc)
-{
- struct drm_i915_private *i915 = guc_to_i915(guc);
- int ret;
-
- ret = guc_init_wq(guc);
- if (ret)
- return ret;
-
- intel_uc_fw_fetch(i915, &guc->fw);
-
- return 0;
-}
-
-void intel_guc_fini_misc(struct intel_guc *guc)
-{
- intel_uc_fw_cleanup_fetch(&guc->fw);
- guc_fini_wq(guc);
-}
-
static int guc_shared_data_create(struct intel_guc *guc)
{
struct i915_vma *vma;
diff --git a/drivers/gpu/drm/i915/intel_guc.h b/drivers/gpu/drm/i915/intel_guc.h
index ec1038c1f50e..91d538fd5f65 100644
--- a/drivers/gpu/drm/i915/intel_guc.h
+++ b/drivers/gpu/drm/i915/intel_guc.h
@@ -153,10 +153,8 @@ static inline u32 intel_guc_ggtt_offset(struct intel_guc *guc,
void intel_guc_init_early(struct intel_guc *guc);
void intel_guc_init_send_regs(struct intel_guc *guc);
void intel_guc_init_params(struct intel_guc *guc);
-int intel_guc_init_misc(struct intel_guc *guc);
int intel_guc_init(struct intel_guc *guc);
void intel_guc_fini(struct intel_guc *guc);
-void intel_guc_fini_misc(struct intel_guc *guc);
int intel_guc_send_nop(struct intel_guc *guc, const u32 *action, u32 len,
u32 *response_buf, u32 response_buf_size);
int intel_guc_send_mmio(struct intel_guc *guc, const u32 *action, u32 len,
diff --git a/drivers/gpu/drm/i915/intel_guc_log.c b/drivers/gpu/drm/i915/intel_guc_log.c
index 06c09ac52c74..0355724ee997 100644
--- a/drivers/gpu/drm/i915/intel_guc_log.c
+++ b/drivers/gpu/drm/i915/intel_guc_log.c
@@ -79,6 +79,9 @@ static inline struct intel_guc *log_to_guc(struct intel_guc_log *log)
static void guc_log_enable_flush_events(struct intel_guc_log *log)
{
+ /* relay wq must be ready for us to queue flush events */
+ GEM_BUG_ON(!log->relay.flush_wq);
+
intel_guc_enable_msg(log_to_guc(log),
INTEL_GUC_RECV_MSG_FLUSH_LOG_BUFFER |
INTEL_GUC_RECV_MSG_CRASH_DUMP_POSTED);
@@ -86,6 +89,9 @@ static void guc_log_enable_flush_events(struct intel_guc_log *log)
static void guc_log_disable_flush_events(struct intel_guc_log *log)
{
+ /* relay wq must stick around until we disable flush events */
+ GEM_BUG_ON(!log->relay.flush_wq);
+
intel_guc_disable_msg(log_to_guc(log),
INTEL_GUC_RECV_MSG_FLUSH_LOG_BUFFER |
INTEL_GUC_RECV_MSG_CRASH_DUMP_POSTED);
@@ -561,9 +567,29 @@ int intel_guc_log_relay_open(struct intel_guc_log *log)
goto out_unlock;
}
+ /*
+ * GuC log buffer flush work item has to do register access to
+ * send the ack to GuC and this work item, if not synced before
+ * suspend, can potentially get executed after the GFX device is
+ * suspended.
+ * By marking the WQ as freezable, we don't have to bother about
+ * flushing of this work item from the suspend hooks, the pending
+ * work item if any will be either executed before the suspend
+ * or scheduled later on resume. This way the handling of work
+ * item can be kept same between system suspend & rpm suspend.
+ */
+ log->relay.flush_wq =
+ alloc_ordered_workqueue("i915-guc_log",
+ WQ_HIGHPRI | WQ_FREEZABLE);
+ if (!log->relay.flush_wq) {
+ DRM_ERROR("Couldn't allocate workqueue for GuC log\n");
+ ret = -ENOMEM;
+ goto out_unlock;
+ }
+
ret = guc_log_relay_create(log);
if (ret)
- goto out_unlock;
+ goto out_wq;
ret = guc_log_map(log);
if (ret)
@@ -584,6 +610,8 @@ int intel_guc_log_relay_open(struct intel_guc_log *log)
out_relay:
guc_log_relay_destroy(log);
+out_wq:
+ destroy_workqueue(fetch_and_zero(&log->relay.flush_wq));
out_unlock:
mutex_unlock(&log->relay.lock);
@@ -623,6 +651,7 @@ void intel_guc_log_relay_close(struct intel_guc_log *log)
GEM_BUG_ON(!intel_guc_log_relay_enabled(log));
guc_log_unmap(log);
guc_log_relay_destroy(log);
+ destroy_workqueue(fetch_and_zero(&log->relay.flush_wq));
mutex_unlock(&log->relay.lock);
}
diff --git a/drivers/gpu/drm/i915/intel_huc.c b/drivers/gpu/drm/i915/intel_huc.c
index fb6f693d3cac..2a41ee89a16d 100644
--- a/drivers/gpu/drm/i915/intel_huc.c
+++ b/drivers/gpu/drm/i915/intel_huc.c
@@ -44,14 +44,6 @@ void intel_huc_init_early(struct intel_huc *huc)
}
}
-int intel_huc_init_misc(struct intel_huc *huc)
-{
- struct drm_i915_private *i915 = huc_to_i915(huc);
-
- intel_uc_fw_fetch(i915, &huc->fw);
- return 0;
-}
-
static int intel_huc_rsa_data_create(struct intel_huc *huc)
{
struct drm_i915_private *i915 = huc_to_i915(huc);
diff --git a/drivers/gpu/drm/i915/intel_huc.h b/drivers/gpu/drm/i915/intel_huc.h
index 2a6c94e79f17..9fa3d4629f2e 100644
--- a/drivers/gpu/drm/i915/intel_huc.h
+++ b/drivers/gpu/drm/i915/intel_huc.h
@@ -45,17 +45,11 @@ struct intel_huc {
};
void intel_huc_init_early(struct intel_huc *huc);
-int intel_huc_init_misc(struct intel_huc *huc);
int intel_huc_init(struct intel_huc *huc);
void intel_huc_fini(struct intel_huc *huc);
int intel_huc_auth(struct intel_huc *huc);
int intel_huc_check_status(struct intel_huc *huc);
-static inline void intel_huc_fini_misc(struct intel_huc *huc)
-{
- intel_uc_fw_cleanup_fetch(&huc->fw);
-}
-
static inline int intel_huc_sanitize(struct intel_huc *huc)
{
intel_uc_fw_sanitize(&huc->fw);
diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915/intel_uc.c
index fdf00f1ebb57..789b0bccfb41 100644
--- a/drivers/gpu/drm/i915/intel_uc.c
+++ b/drivers/gpu/drm/i915/intel_uc.c
@@ -345,44 +345,26 @@ static void guc_disable_communication(struct intel_guc *guc)
DRM_INFO("GuC communication disabled\n");
}
-int intel_uc_init_misc(struct drm_i915_private *i915)
+void intel_uc_fetch_firmwares(struct drm_i915_private *i915)
{
- struct intel_guc *guc = &i915->guc;
- struct intel_huc *huc = &i915->huc;
- int ret;
-
if (!USES_GUC(i915))
- return 0;
-
- ret = intel_guc_init_misc(guc);
- if (ret)
- return ret;
-
- if (USES_HUC(i915)) {
- ret = intel_huc_init_misc(huc);
- if (ret)
- goto err_guc;
- }
+ return;
- return 0;
+ intel_uc_fw_fetch(i915, &i915->guc.fw);
-err_guc:
- intel_guc_fini_misc(guc);
- return ret;
+ if (USES_HUC(i915))
+ intel_uc_fw_fetch(i915, &i915->huc.fw);
}
-void intel_uc_fini_misc(struct drm_i915_private *i915)
+void intel_uc_cleanup_firmwares(struct drm_i915_private *i915)
{
- struct intel_guc *guc = &i915->guc;
- struct intel_huc *huc = &i915->huc;
-
if (!USES_GUC(i915))
return;
if (USES_HUC(i915))
- intel_huc_fini_misc(huc);
+ intel_uc_fw_cleanup_fetch(&i915->huc.fw);
- intel_guc_fini_misc(guc);
+ intel_uc_fw_cleanup_fetch(&i915->guc.fw);
}
int intel_uc_init(struct drm_i915_private *i915)
diff --git a/drivers/gpu/drm/i915/intel_uc.h b/drivers/gpu/drm/i915/intel_uc.h
index 3ea06c87dfcd..5a1383e192dd 100644
--- a/drivers/gpu/drm/i915/intel_uc.h
+++ b/drivers/gpu/drm/i915/intel_uc.h
@@ -31,8 +31,8 @@
void intel_uc_init_early(struct drm_i915_private *dev_priv);
void intel_uc_cleanup_early(struct drm_i915_private *dev_priv);
void intel_uc_init_mmio(struct drm_i915_private *dev_priv);
-int intel_uc_init_misc(struct drm_i915_private *dev_priv);
-void intel_uc_fini_misc(struct drm_i915_private *dev_priv);
+void intel_uc_fetch_firmwares(struct drm_i915_private *dev_priv);
+void intel_uc_cleanup_firmwares(struct drm_i915_private *dev_priv);
void intel_uc_sanitize(struct drm_i915_private *dev_priv);
int intel_uc_init_hw(struct drm_i915_private *dev_priv);
void intel_uc_fini_hw(struct drm_i915_private *dev_priv);
--
2.20.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH 04/12] drm/i915/uc: introduce intel_uc_fw_supported
2019-07-10 0:54 [PATCH 00/12] GT-fy the uc code Daniele Ceraolo Spurio
` (2 preceding siblings ...)
2019-07-10 0:54 ` [PATCH 03/12] drm/i915/uc: replace uc init/fini misc Daniele Ceraolo Spurio
@ 2019-07-10 0:54 ` Daniele Ceraolo Spurio
2019-07-10 16:57 ` Michal Wajdeczko
2019-07-10 0:54 ` [PATCH 05/12] drm/i915/guc: move guc irq functions to intel_guc parameter Daniele Ceraolo Spurio
` (11 subsequent siblings)
15 siblings, 1 reply; 28+ messages in thread
From: Daniele Ceraolo Spurio @ 2019-07-10 0:54 UTC (permalink / raw)
To: intel-gfx
Instead of always checking in the device config is GuC and HuC are
supported or not, we can save the state in the uc_fw structure and
avoid going through i915 every time from the low-level uc management
code. while at it FIRMWARE_NONE has been renamed to better indicate that
we haven't started the fetch/load yet, but we might have already selected
a blob.
Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
---
drivers/gpu/drm/i915/intel_guc_fw.c | 6 +++++-
drivers/gpu/drm/i915/intel_huc_fw.c | 6 +++++-
drivers/gpu/drm/i915/intel_uc.c | 25 ++++++++++++------------
drivers/gpu/drm/i915/intel_uc_fw.c | 4 +++-
drivers/gpu/drm/i915/intel_uc_fw.h | 30 ++++++++++++++++++++++++-----
5 files changed, 51 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_guc_fw.c b/drivers/gpu/drm/i915/intel_guc_fw.c
index db1e0daca7db..ee95d4960c5c 100644
--- a/drivers/gpu/drm/i915/intel_guc_fw.c
+++ b/drivers/gpu/drm/i915/intel_guc_fw.c
@@ -79,8 +79,12 @@ static void guc_fw_select(struct intel_uc_fw *guc_fw)
GEM_BUG_ON(guc_fw->type != INTEL_UC_FW_TYPE_GUC);
- if (!HAS_GUC(i915))
+ if (!HAS_GUC(i915)) {
+ guc_fw->fetch_status = INTEL_UC_FIRMWARE_NOT_SUPPORTED;
return;
+ }
+
+ guc_fw->fetch_status = INTEL_UC_FIRMWARE_NOT_STARTED;
if (i915_modparams.guc_firmware_path) {
guc_fw->path = i915_modparams.guc_firmware_path;
diff --git a/drivers/gpu/drm/i915/intel_huc_fw.c b/drivers/gpu/drm/i915/intel_huc_fw.c
index 05cbf8338f53..06e726ba9863 100644
--- a/drivers/gpu/drm/i915/intel_huc_fw.c
+++ b/drivers/gpu/drm/i915/intel_huc_fw.c
@@ -73,8 +73,12 @@ static void huc_fw_select(struct intel_uc_fw *huc_fw)
GEM_BUG_ON(huc_fw->type != INTEL_UC_FW_TYPE_HUC);
- if (!HAS_HUC(dev_priv))
+ if (!HAS_HUC(dev_priv)) {
+ huc_fw->fetch_status = INTEL_UC_FIRMWARE_NOT_SUPPORTED;
return;
+ }
+
+ huc_fw->fetch_status = INTEL_UC_FIRMWARE_NOT_STARTED;
if (i915_modparams.huc_firmware_path) {
huc_fw->path = i915_modparams.huc_firmware_path;
diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915/intel_uc.c
index 789b0bccfb41..ef2a864b8990 100644
--- a/drivers/gpu/drm/i915/intel_uc.c
+++ b/drivers/gpu/drm/i915/intel_uc.c
@@ -71,7 +71,8 @@ static int __get_default_guc_log_level(struct drm_i915_private *i915)
{
int guc_log_level;
- if (!HAS_GUC(i915) || !intel_uc_is_using_guc(i915))
+ if (!intel_uc_fw_supported(&i915->guc.fw) ||
+ !intel_uc_is_using_guc(i915))
guc_log_level = GUC_LOG_LEVEL_DISABLED;
else if (IS_ENABLED(CONFIG_DRM_I915_DEBUG) ||
IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM))
@@ -119,16 +120,16 @@ static void sanitize_options_early(struct drm_i915_private *i915)
if (intel_uc_is_using_guc(i915) && !intel_uc_fw_is_selected(guc_fw)) {
DRM_WARN("Incompatible option detected: %s=%d, %s!\n",
"enable_guc", i915_modparams.enable_guc,
- !HAS_GUC(i915) ? "no GuC hardware" :
- "no GuC firmware");
+ !intel_uc_fw_supported(guc_fw) ?
+ "no GuC hardware" : "no GuC firmware");
}
/* Verify HuC firmware availability */
if (intel_uc_is_using_huc(i915) && !intel_uc_fw_is_selected(huc_fw)) {
DRM_WARN("Incompatible option detected: %s=%d, %s!\n",
"enable_guc", i915_modparams.enable_guc,
- !HAS_HUC(i915) ? "no HuC hardware" :
- "no HuC firmware");
+ !intel_uc_fw_supported(huc_fw) ?
+ "no HuC hardware" : "no HuC firmware");
}
/* XXX: GuC submission is unavailable for now */
@@ -148,8 +149,8 @@ static void sanitize_options_early(struct drm_i915_private *i915)
if (i915_modparams.guc_log_level > 0 && !intel_uc_is_using_guc(i915)) {
DRM_WARN("Incompatible option detected: %s=%d, %s!\n",
"guc_log_level", i915_modparams.guc_log_level,
- !HAS_GUC(i915) ? "no GuC hardware" :
- "GuC not enabled");
+ !intel_uc_fw_supported(guc_fw) ?
+ "no GuC hardware" : "GuC not enabled");
i915_modparams.guc_log_level = 0;
}
@@ -376,7 +377,7 @@ int intel_uc_init(struct drm_i915_private *i915)
if (!USES_GUC(i915))
return 0;
- if (!HAS_GUC(i915))
+ if (!intel_uc_fw_supported(&guc->fw))
return -ENODEV;
/* XXX: GuC submission is unavailable for now */
@@ -419,7 +420,7 @@ void intel_uc_fini(struct drm_i915_private *i915)
if (!USES_GUC(i915))
return;
- GEM_BUG_ON(!HAS_GUC(i915));
+ GEM_BUG_ON(!intel_uc_fw_supported(&guc->fw));
if (USES_GUC_SUBMISSION(i915))
intel_guc_submission_fini(guc);
@@ -435,7 +436,7 @@ static void __uc_sanitize(struct drm_i915_private *i915)
struct intel_guc *guc = &i915->guc;
struct intel_huc *huc = &i915->huc;
- GEM_BUG_ON(!HAS_GUC(i915));
+ GEM_BUG_ON(!intel_uc_fw_supported(&guc->fw));
intel_huc_sanitize(huc);
intel_guc_sanitize(guc);
@@ -460,7 +461,7 @@ int intel_uc_init_hw(struct drm_i915_private *i915)
if (!USES_GUC(i915))
return 0;
- GEM_BUG_ON(!HAS_GUC(i915));
+ GEM_BUG_ON(!intel_uc_fw_supported(&guc->fw));
guc_reset_interrupts(guc);
@@ -557,7 +558,7 @@ void intel_uc_fini_hw(struct drm_i915_private *i915)
if (!intel_guc_is_loaded(guc))
return;
- GEM_BUG_ON(!HAS_GUC(i915));
+ GEM_BUG_ON(!intel_uc_fw_supported(&guc->fw));
if (USES_GUC_SUBMISSION(i915))
intel_guc_submission_disable(guc);
diff --git a/drivers/gpu/drm/i915/intel_uc_fw.c b/drivers/gpu/drm/i915/intel_uc_fw.c
index f342ddd47df8..8ce7210907c0 100644
--- a/drivers/gpu/drm/i915/intel_uc_fw.c
+++ b/drivers/gpu/drm/i915/intel_uc_fw.c
@@ -47,6 +47,8 @@ void intel_uc_fw_fetch(struct drm_i915_private *dev_priv,
size_t size;
int err;
+ GEM_BUG_ON(!intel_uc_fw_supported(uc_fw));
+
if (!uc_fw->path) {
dev_info(dev_priv->drm.dev,
"%s: No firmware was defined for %s!\n",
@@ -328,7 +330,7 @@ void intel_uc_fw_cleanup_fetch(struct intel_uc_fw *uc_fw)
if (obj)
i915_gem_object_put(obj);
- uc_fw->fetch_status = INTEL_UC_FIRMWARE_NONE;
+ uc_fw->fetch_status = INTEL_UC_FIRMWARE_NOT_STARTED;
}
/**
diff --git a/drivers/gpu/drm/i915/intel_uc_fw.h b/drivers/gpu/drm/i915/intel_uc_fw.h
index 24e66469153c..833d04d06576 100644
--- a/drivers/gpu/drm/i915/intel_uc_fw.h
+++ b/drivers/gpu/drm/i915/intel_uc_fw.h
@@ -26,6 +26,7 @@
#define _INTEL_UC_FW_H_
#include <linux/types.h>
+#include "i915_gem.h"
struct drm_printer;
struct drm_i915_private;
@@ -34,8 +35,10 @@ struct drm_i915_private;
#define INTEL_UC_FIRMWARE_URL "https://git.kernel.org/pub/scm/linux/kernel/git/firmware/linux-firmware.git/tree/i915"
enum intel_uc_fw_status {
+ INTEL_UC_FIRMWARE_NOT_SUPPORTED = -2, /* no uc HW */
INTEL_UC_FIRMWARE_FAIL = -1,
- INTEL_UC_FIRMWARE_NONE = 0,
+ INTEL_UC_FIRMWARE_UNINITIALIZED = 0, /* used to catch checks done too early */
+ INTEL_UC_FIRMWARE_NOT_STARTED = 1,
INTEL_UC_FIRMWARE_PENDING,
INTEL_UC_FIRMWARE_SUCCESS
};
@@ -79,10 +82,14 @@ static inline
const char *intel_uc_fw_status_repr(enum intel_uc_fw_status status)
{
switch (status) {
+ case INTEL_UC_FIRMWARE_NOT_SUPPORTED:
+ return "N/A - uc HW not available";
case INTEL_UC_FIRMWARE_FAIL:
return "FAIL";
- case INTEL_UC_FIRMWARE_NONE:
- return "NONE";
+ case INTEL_UC_FIRMWARE_UNINITIALIZED:
+ return "UNINITIALIZED";
+ case INTEL_UC_FIRMWARE_NOT_STARTED:
+ return "NOT_STARTED";
case INTEL_UC_FIRMWARE_PENDING:
return "PENDING";
case INTEL_UC_FIRMWARE_SUCCESS:
@@ -106,9 +113,15 @@ static inline
void intel_uc_fw_init_early(struct intel_uc_fw *uc_fw,
enum intel_uc_fw_type type)
{
+ /*
+ * we use FIRMWARE_UNINITIALIZED to detect checks against fetch_status
+ * before we're looked at the HW caps to see if we have uc support
+ */
+ BUILD_BUG_ON(INTEL_UC_FIRMWARE_UNINITIALIZED);
+
uc_fw->path = NULL;
- uc_fw->fetch_status = INTEL_UC_FIRMWARE_NONE;
- uc_fw->load_status = INTEL_UC_FIRMWARE_NONE;
+ uc_fw->fetch_status = INTEL_UC_FIRMWARE_UNINITIALIZED;
+ uc_fw->load_status = INTEL_UC_FIRMWARE_NOT_STARTED;
uc_fw->type = type;
}
@@ -122,6 +135,13 @@ static inline bool intel_uc_fw_is_loaded(struct intel_uc_fw *uc_fw)
return uc_fw->load_status == INTEL_UC_FIRMWARE_SUCCESS;
}
+static inline bool intel_uc_fw_supported(struct intel_uc_fw *uc_fw)
+{
+ /* shouldn't call this before checking hw/blob availability */
+ GEM_BUG_ON(uc_fw->fetch_status == INTEL_UC_FIRMWARE_UNINITIALIZED);
+ return uc_fw->fetch_status != INTEL_UC_FIRMWARE_NOT_SUPPORTED;
+}
+
static inline void intel_uc_fw_sanitize(struct intel_uc_fw *uc_fw)
{
if (intel_uc_fw_is_loaded(uc_fw))
--
2.20.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH 05/12] drm/i915/guc: move guc irq functions to intel_guc parameter
2019-07-10 0:54 [PATCH 00/12] GT-fy the uc code Daniele Ceraolo Spurio
` (3 preceding siblings ...)
2019-07-10 0:54 ` [PATCH 04/12] drm/i915/uc: introduce intel_uc_fw_supported Daniele Ceraolo Spurio
@ 2019-07-10 0:54 ` Daniele Ceraolo Spurio
2019-07-10 0:54 ` [PATCH 06/12] drm/i915/guc: unify guc irq handling Daniele Ceraolo Spurio
` (10 subsequent siblings)
15 siblings, 0 replies; 28+ messages in thread
From: Daniele Ceraolo Spurio @ 2019-07-10 0:54 UTC (permalink / raw)
To: intel-gfx
No functional change, just moving the guc_to_i915 from the caller into
the irq function. This will help with the upcoming move of guc under
intel_gt.
Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
---
drivers/gpu/drm/i915/i915_irq.c | 40 +++++++++++++++++++++-----------
drivers/gpu/drm/i915/i915_irq.h | 13 ++++++-----
drivers/gpu/drm/i915/intel_guc.h | 6 ++---
drivers/gpu/drm/i915/intel_uc.c | 6 ++---
4 files changed, 39 insertions(+), 26 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 7c5ba5cbea34..831d185c07d2 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -599,8 +599,10 @@ void gen6_disable_rps_interrupts(struct drm_i915_private *dev_priv)
gen6_reset_rps_interrupts(dev_priv);
}
-void gen9_reset_guc_interrupts(struct drm_i915_private *dev_priv)
+void gen9_reset_guc_interrupts(struct intel_guc *guc)
{
+ struct drm_i915_private *dev_priv = guc_to_i915(guc);
+
assert_rpm_wakelock_held(&dev_priv->runtime_pm);
spin_lock_irq(&dev_priv->irq_lock);
@@ -608,61 +610,71 @@ void gen9_reset_guc_interrupts(struct drm_i915_private *dev_priv)
spin_unlock_irq(&dev_priv->irq_lock);
}
-void gen9_enable_guc_interrupts(struct drm_i915_private *dev_priv)
+void gen9_enable_guc_interrupts(struct intel_guc *guc)
{
+ struct drm_i915_private *dev_priv = guc_to_i915(guc);
+
assert_rpm_wakelock_held(&dev_priv->runtime_pm);
spin_lock_irq(&dev_priv->irq_lock);
- if (!dev_priv->guc.interrupts.enabled) {
+ if (!guc->interrupts.enabled) {
WARN_ON_ONCE(I915_READ(gen6_pm_iir(dev_priv)) &
dev_priv->pm_guc_events);
- dev_priv->guc.interrupts.enabled = true;
+ guc->interrupts.enabled = true;
gen6_enable_pm_irq(&dev_priv->gt, dev_priv->pm_guc_events);
}
spin_unlock_irq(&dev_priv->irq_lock);
}
-void gen9_disable_guc_interrupts(struct drm_i915_private *dev_priv)
+void gen9_disable_guc_interrupts(struct intel_guc *guc)
{
+ struct drm_i915_private *dev_priv = guc_to_i915(guc);
+
assert_rpm_wakelock_held(&dev_priv->runtime_pm);
spin_lock_irq(&dev_priv->irq_lock);
- dev_priv->guc.interrupts.enabled = false;
+ guc->interrupts.enabled = false;
gen6_disable_pm_irq(&dev_priv->gt, dev_priv->pm_guc_events);
spin_unlock_irq(&dev_priv->irq_lock);
intel_synchronize_irq(dev_priv);
- gen9_reset_guc_interrupts(dev_priv);
+ gen9_reset_guc_interrupts(guc);
}
-void gen11_reset_guc_interrupts(struct drm_i915_private *i915)
+void gen11_reset_guc_interrupts(struct intel_guc *guc)
{
+ struct drm_i915_private *i915 = guc_to_i915(guc);
+
spin_lock_irq(&i915->irq_lock);
gen11_reset_one_iir(&i915->gt, 0, GEN11_GUC);
spin_unlock_irq(&i915->irq_lock);
}
-void gen11_enable_guc_interrupts(struct drm_i915_private *dev_priv)
+void gen11_enable_guc_interrupts(struct intel_guc *guc)
{
+ struct drm_i915_private *dev_priv = guc_to_i915(guc);
+
spin_lock_irq(&dev_priv->irq_lock);
- if (!dev_priv->guc.interrupts.enabled) {
+ if (!guc->interrupts.enabled) {
u32 events = REG_FIELD_PREP(ENGINE1_MASK,
GEN11_GUC_INTR_GUC2HOST);
WARN_ON_ONCE(gen11_reset_one_iir(&dev_priv->gt, 0, GEN11_GUC));
I915_WRITE(GEN11_GUC_SG_INTR_ENABLE, events);
I915_WRITE(GEN11_GUC_SG_INTR_MASK, ~events);
- dev_priv->guc.interrupts.enabled = true;
+ guc->interrupts.enabled = true;
}
spin_unlock_irq(&dev_priv->irq_lock);
}
-void gen11_disable_guc_interrupts(struct drm_i915_private *dev_priv)
+void gen11_disable_guc_interrupts(struct intel_guc *guc)
{
+ struct drm_i915_private *dev_priv = guc_to_i915(guc);
+
spin_lock_irq(&dev_priv->irq_lock);
- dev_priv->guc.interrupts.enabled = false;
+ guc->interrupts.enabled = false;
I915_WRITE(GEN11_GUC_SG_INTR_MASK, ~0);
I915_WRITE(GEN11_GUC_SG_INTR_ENABLE, 0);
@@ -670,7 +682,7 @@ void gen11_disable_guc_interrupts(struct drm_i915_private *dev_priv)
spin_unlock_irq(&dev_priv->irq_lock);
intel_synchronize_irq(dev_priv);
- gen11_reset_guc_interrupts(dev_priv);
+ gen11_reset_guc_interrupts(guc);
}
/**
diff --git a/drivers/gpu/drm/i915/i915_irq.h b/drivers/gpu/drm/i915/i915_irq.h
index d93fa4e75442..c3716d674bb9 100644
--- a/drivers/gpu/drm/i915/i915_irq.h
+++ b/drivers/gpu/drm/i915/i915_irq.h
@@ -12,6 +12,7 @@
struct drm_i915_private;
struct intel_crtc;
+struct intel_guc;
extern void intel_irq_init(struct drm_i915_private *dev_priv);
extern void intel_irq_fini(struct drm_i915_private *dev_priv);
@@ -112,12 +113,12 @@ void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
u8 pipe_mask);
void gen8_irq_power_well_pre_disable(struct drm_i915_private *dev_priv,
u8 pipe_mask);
-void gen9_reset_guc_interrupts(struct drm_i915_private *dev_priv);
-void gen9_enable_guc_interrupts(struct drm_i915_private *dev_priv);
-void gen9_disable_guc_interrupts(struct drm_i915_private *dev_priv);
-void gen11_reset_guc_interrupts(struct drm_i915_private *i915);
-void gen11_enable_guc_interrupts(struct drm_i915_private *i915);
-void gen11_disable_guc_interrupts(struct drm_i915_private *i915);
+void gen9_reset_guc_interrupts(struct intel_guc *guc);
+void gen9_enable_guc_interrupts(struct intel_guc *guc);
+void gen9_disable_guc_interrupts(struct intel_guc *guc);
+void gen11_reset_guc_interrupts(struct intel_guc *guc);
+void gen11_enable_guc_interrupts(struct intel_guc *guc);
+void gen11_disable_guc_interrupts(struct intel_guc *guc);
bool i915_get_crtc_scanoutpos(struct drm_device *dev, unsigned int pipe,
bool in_vblank_irq, int *vpos, int *hpos,
diff --git a/drivers/gpu/drm/i915/intel_guc.h b/drivers/gpu/drm/i915/intel_guc.h
index 91d538fd5f65..6852352381ce 100644
--- a/drivers/gpu/drm/i915/intel_guc.h
+++ b/drivers/gpu/drm/i915/intel_guc.h
@@ -56,9 +56,9 @@ struct intel_guc {
struct {
bool enabled;
- void (*reset)(struct drm_i915_private *i915);
- void (*enable)(struct drm_i915_private *i915);
- void (*disable)(struct drm_i915_private *i915);
+ void (*reset)(struct intel_guc *guc);
+ void (*enable)(struct intel_guc *guc);
+ void (*disable)(struct intel_guc *guc);
} interrupts;
struct i915_vma *ads_vma;
diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915/intel_uc.c
index ef2a864b8990..6193b87855e0 100644
--- a/drivers/gpu/drm/i915/intel_uc.c
+++ b/drivers/gpu/drm/i915/intel_uc.c
@@ -268,17 +268,17 @@ static void guc_handle_mmio_msg(struct intel_guc *guc)
static void guc_reset_interrupts(struct intel_guc *guc)
{
- guc->interrupts.reset(guc_to_i915(guc));
+ guc->interrupts.reset(guc);
}
static void guc_enable_interrupts(struct intel_guc *guc)
{
- guc->interrupts.enable(guc_to_i915(guc));
+ guc->interrupts.enable(guc);
}
static void guc_disable_interrupts(struct intel_guc *guc)
{
- guc->interrupts.disable(guc_to_i915(guc));
+ guc->interrupts.disable(guc);
}
static int guc_enable_communication(struct intel_guc *guc)
--
2.20.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH 06/12] drm/i915/guc: unify guc irq handling
2019-07-10 0:54 [PATCH 00/12] GT-fy the uc code Daniele Ceraolo Spurio
` (4 preceding siblings ...)
2019-07-10 0:54 ` [PATCH 05/12] drm/i915/guc: move guc irq functions to intel_guc parameter Daniele Ceraolo Spurio
@ 2019-07-10 0:54 ` Daniele Ceraolo Spurio
2019-07-10 17:04 ` Michal Wajdeczko
2019-07-10 0:54 ` [PATCH 07/12] drm/i915/uc: move GuC and HuC files under gt/uc/ Daniele Ceraolo Spurio
` (9 subsequent siblings)
15 siblings, 1 reply; 28+ messages in thread
From: Daniele Ceraolo Spurio @ 2019-07-10 0:54 UTC (permalink / raw)
To: intel-gfx
The 16-bit guc irq vector is unchanged across gens, the only thing that
moved is its position (from the upper 16 bits of the PM regs to its own
register). Instead of duplicating all defines and functions to handle
the 2 different positions, we can work on the vector and shift it as
appropriate. While at it, update the handler to work on intel_guc.
Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
---
drivers/gpu/drm/i915/i915_irq.c | 24 ++++++++-------------
drivers/gpu/drm/i915/i915_reg.h | 10 ---------
drivers/gpu/drm/i915/intel_guc_reg.h | 32 ++++++++++++++--------------
3 files changed, 25 insertions(+), 41 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 831d185c07d2..42d6d8bfac70 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -264,7 +264,7 @@ static void gen2_irq_init(struct intel_uncore *uncore,
gen2_irq_init((uncore), imr_val, ier_val)
static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir);
-static void gen9_guc_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir);
+static void guc_irq_handler(struct intel_guc *guc, u16 guc_iir);
/* For display hotplug interrupt */
static inline void
@@ -658,8 +658,7 @@ void gen11_enable_guc_interrupts(struct intel_guc *guc)
spin_lock_irq(&dev_priv->irq_lock);
if (!guc->interrupts.enabled) {
- u32 events = REG_FIELD_PREP(ENGINE1_MASK,
- GEN11_GUC_INTR_GUC2HOST);
+ u32 events = REG_FIELD_PREP(ENGINE1_MASK, GUC_INTR_GUC2HOST);
WARN_ON_ONCE(gen11_reset_one_iir(&dev_priv->gt, 0, GEN11_GUC));
I915_WRITE(GEN11_GUC_SG_INTR_ENABLE, events);
@@ -1656,7 +1655,7 @@ static void gen8_gt_irq_handler(struct drm_i915_private *i915,
if (master_ctl & (GEN8_GT_PM_IRQ | GEN8_GT_GUC_IRQ)) {
gen6_rps_irq_handler(i915, gt_iir[2]);
- gen9_guc_irq_handler(i915, gt_iir[2]);
+ guc_irq_handler(&i915->guc, gt_iir[2] >> 16);
}
}
@@ -1955,16 +1954,10 @@ static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir)
DRM_DEBUG("Command parser error, pm_iir 0x%08x\n", pm_iir);
}
-static void gen9_guc_irq_handler(struct drm_i915_private *dev_priv, u32 gt_iir)
+static void guc_irq_handler(struct intel_guc *guc, u16 iir)
{
- if (gt_iir & GEN9_GUC_TO_HOST_INT_EVENT)
- intel_guc_to_host_event_handler(&dev_priv->guc);
-}
-
-static void gen11_guc_irq_handler(struct drm_i915_private *i915, u16 iir)
-{
- if (iir & GEN11_GUC_INTR_GUC2HOST)
- intel_guc_to_host_event_handler(&i915->guc);
+ if (iir & GUC_INTR_GUC2HOST)
+ intel_guc_to_host_event_handler(guc);
}
static void i9xx_pipestat_irq_reset(struct drm_i915_private *dev_priv)
@@ -3092,7 +3085,7 @@ gen11_other_irq_handler(struct intel_gt *gt, const u8 instance,
struct drm_i915_private *i915 = gt->i915;
if (instance == OTHER_GUC_INSTANCE)
- return gen11_guc_irq_handler(i915, iir);
+ return guc_irq_handler(&i915->guc, iir);
if (instance == OTHER_GTPM_INSTANCE)
return gen11_rps_irq_handler(gt, iir);
@@ -4764,8 +4757,9 @@ void intel_irq_init(struct drm_i915_private *dev_priv)
for (i = 0; i < MAX_L3_SLICES; ++i)
dev_priv->l3_parity.remap_info[i] = NULL;
+ /* pre-gen11 the guc irqs bits are in the upper 16 bits of the pm reg */
if (HAS_GUC_SCHED(dev_priv) && INTEL_GEN(dev_priv) < 11)
- dev_priv->pm_guc_events = GEN9_GUC_TO_HOST_INT_EVENT;
+ dev_priv->pm_guc_events = GUC_INTR_GUC2HOST << 16;
/* Let's track the enabled rps events */
if (IS_VALLEYVIEW(dev_priv))
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 5898f59e3dd7..4dc31e488b80 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7342,16 +7342,6 @@ enum {
#define GEN8_GT_IIR(which) _MMIO(0x44308 + (0x10 * (which)))
#define GEN8_GT_IER(which) _MMIO(0x4430c + (0x10 * (which)))
-#define GEN9_GUC_TO_HOST_INT_EVENT (1 << 31)
-#define GEN9_GUC_EXEC_ERROR_EVENT (1 << 30)
-#define GEN9_GUC_DISPLAY_EVENT (1 << 29)
-#define GEN9_GUC_SEMA_SIGNAL_EVENT (1 << 28)
-#define GEN9_GUC_IOMMU_MSG_EVENT (1 << 27)
-#define GEN9_GUC_DB_RING_EVENT (1 << 26)
-#define GEN9_GUC_DMA_DONE_EVENT (1 << 25)
-#define GEN9_GUC_FATAL_ERROR_EVENT (1 << 24)
-#define GEN9_GUC_NOTIFICATION_EVENT (1 << 23)
-
#define GEN8_RCS_IRQ_SHIFT 0
#define GEN8_BCS_IRQ_SHIFT 16
#define GEN8_VCS0_IRQ_SHIFT 0 /* NB: VCS1 in bspec! */
diff --git a/drivers/gpu/drm/i915/intel_guc_reg.h b/drivers/gpu/drm/i915/intel_guc_reg.h
index a5ab7bc5504c..e3cbb23299ce 100644
--- a/drivers/gpu/drm/i915/intel_guc_reg.h
+++ b/drivers/gpu/drm/i915/intel_guc_reg.h
@@ -141,21 +141,21 @@ struct guc_doorbell_info {
#define GUC_PM_P24C_IER _MMIO(0xC55C)
/* GuC Interrupt Vector */
-#define GEN11_GUC_INTR_GUC2HOST (1 << 15)
-#define GEN11_GUC_INTR_EXEC_ERROR (1 << 14)
-#define GEN11_GUC_INTR_DISPLAY_EVENT (1 << 13)
-#define GEN11_GUC_INTR_SEM_SIG (1 << 12)
-#define GEN11_GUC_INTR_IOMMU2GUC (1 << 11)
-#define GEN11_GUC_INTR_DOORBELL_RANG (1 << 10)
-#define GEN11_GUC_INTR_DMA_DONE (1 << 9)
-#define GEN11_GUC_INTR_FATAL_ERROR (1 << 8)
-#define GEN11_GUC_INTR_NOTIF_ERROR (1 << 7)
-#define GEN11_GUC_INTR_SW_INT_6 (1 << 6)
-#define GEN11_GUC_INTR_SW_INT_5 (1 << 5)
-#define GEN11_GUC_INTR_SW_INT_4 (1 << 4)
-#define GEN11_GUC_INTR_SW_INT_3 (1 << 3)
-#define GEN11_GUC_INTR_SW_INT_2 (1 << 2)
-#define GEN11_GUC_INTR_SW_INT_1 (1 << 1)
-#define GEN11_GUC_INTR_SW_INT_0 (1 << 0)
+#define GUC_INTR_GUC2HOST BIT(15)
+#define GUC_INTR_EXEC_ERROR BIT(14)
+#define GUC_INTR_DISPLAY_EVENT BIT(13)
+#define GUC_INTR_SEM_SIG BIT(12)
+#define GUC_INTR_IOMMU2GUC BIT(11)
+#define GUC_INTR_DOORBELL_RANG BIT(10)
+#define GUC_INTR_DMA_DONE BIT(9)
+#define GUC_INTR_FATAL_ERROR BIT(8)
+#define GUC_INTR_NOTIF_ERROR BIT(7)
+#define GUC_INTR_SW_INT_6 BIT(6)
+#define GUC_INTR_SW_INT_5 BIT(5)
+#define GUC_INTR_SW_INT_4 BIT(4)
+#define GUC_INTR_SW_INT_3 BIT(3)
+#define GUC_INTR_SW_INT_2 BIT(2)
+#define GUC_INTR_SW_INT_1 BIT(1)
+#define GUC_INTR_SW_INT_0 BIT(0)
#endif
--
2.20.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH 07/12] drm/i915/uc: move GuC and HuC files under gt/uc/
2019-07-10 0:54 [PATCH 00/12] GT-fy the uc code Daniele Ceraolo Spurio
` (5 preceding siblings ...)
2019-07-10 0:54 ` [PATCH 06/12] drm/i915/guc: unify guc irq handling Daniele Ceraolo Spurio
@ 2019-07-10 0:54 ` Daniele Ceraolo Spurio
2019-07-10 17:52 ` Michal Wajdeczko
2019-07-10 0:54 ` [PATCH 08/12] drm/i915/uc: move GuC/HuC inside intel_gt under a new intel_uc Daniele Ceraolo Spurio
` (8 subsequent siblings)
15 siblings, 1 reply; 28+ messages in thread
From: Daniele Ceraolo Spurio @ 2019-07-10 0:54 UTC (permalink / raw)
To: intel-gfx
Both microcontrollers are part of the GT HW and are closely related to
GT operations. To keep all the files cleanly together, they've been
placed in their own subdir inside the gt/ folder
Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
---
drivers/gpu/drm/i915/Makefile | 21 ++++++++++---------
| 4 ----
drivers/gpu/drm/i915/gt/intel_reset.c | 2 +-
drivers/gpu/drm/i915/gt/uc/Makefile | 5 +++++
| 16 ++++++++++++++
drivers/gpu/drm/i915/{ => gt/uc}/intel_guc.c | 0
drivers/gpu/drm/i915/{ => gt/uc}/intel_guc.h | 0
.../gpu/drm/i915/{ => gt/uc}/intel_guc_ads.c | 0
.../gpu/drm/i915/{ => gt/uc}/intel_guc_ads.h | 0
.../gpu/drm/i915/{ => gt/uc}/intel_guc_ct.c | 0
.../gpu/drm/i915/{ => gt/uc}/intel_guc_ct.h | 0
.../gpu/drm/i915/{ => gt/uc}/intel_guc_fw.c | 0
.../gpu/drm/i915/{ => gt/uc}/intel_guc_fw.h | 0
.../gpu/drm/i915/{ => gt/uc}/intel_guc_fwif.h | 0
.../gpu/drm/i915/{ => gt/uc}/intel_guc_log.c | 0
.../gpu/drm/i915/{ => gt/uc}/intel_guc_log.h | 0
.../gpu/drm/i915/{ => gt/uc}/intel_guc_reg.h | 0
.../i915/{ => gt/uc}/intel_guc_submission.c | 9 ++++----
.../i915/{ => gt/uc}/intel_guc_submission.h | 0
drivers/gpu/drm/i915/{ => gt/uc}/intel_huc.c | 0
drivers/gpu/drm/i915/{ => gt/uc}/intel_huc.h | 0
.../gpu/drm/i915/{ => gt/uc}/intel_huc_fw.c | 0
.../gpu/drm/i915/{ => gt/uc}/intel_huc_fw.h | 0
drivers/gpu/drm/i915/{ => gt/uc}/intel_uc.c | 0
drivers/gpu/drm/i915/{ => gt/uc}/intel_uc.h | 0
.../gpu/drm/i915/{ => gt/uc}/intel_uc_fw.c | 0
.../gpu/drm/i915/{ => gt/uc}/intel_uc_fw.h | 0
.../intel_guc.c => gt/uc/selftest_guc.c} | 0
drivers/gpu/drm/i915/i915_debugfs.c | 2 +-
drivers/gpu/drm/i915/i915_drv.c | 2 +-
drivers/gpu/drm/i915/i915_drv.h | 2 +-
drivers/gpu/drm/i915/i915_gpu_error.h | 2 +-
32 files changed, 42 insertions(+), 23 deletions(-)
create mode 100644 drivers/gpu/drm/i915/gt/uc/Makefile
create mode 100644 drivers/gpu/drm/i915/gt/uc/Makefile.header-test
rename drivers/gpu/drm/i915/{ => gt/uc}/intel_guc.c (100%)
rename drivers/gpu/drm/i915/{ => gt/uc}/intel_guc.h (100%)
rename drivers/gpu/drm/i915/{ => gt/uc}/intel_guc_ads.c (100%)
rename drivers/gpu/drm/i915/{ => gt/uc}/intel_guc_ads.h (100%)
rename drivers/gpu/drm/i915/{ => gt/uc}/intel_guc_ct.c (100%)
rename drivers/gpu/drm/i915/{ => gt/uc}/intel_guc_ct.h (100%)
rename drivers/gpu/drm/i915/{ => gt/uc}/intel_guc_fw.c (100%)
rename drivers/gpu/drm/i915/{ => gt/uc}/intel_guc_fw.h (100%)
rename drivers/gpu/drm/i915/{ => gt/uc}/intel_guc_fwif.h (100%)
rename drivers/gpu/drm/i915/{ => gt/uc}/intel_guc_log.c (100%)
rename drivers/gpu/drm/i915/{ => gt/uc}/intel_guc_log.h (100%)
rename drivers/gpu/drm/i915/{ => gt/uc}/intel_guc_reg.h (100%)
rename drivers/gpu/drm/i915/{ => gt/uc}/intel_guc_submission.c (99%)
rename drivers/gpu/drm/i915/{ => gt/uc}/intel_guc_submission.h (100%)
rename drivers/gpu/drm/i915/{ => gt/uc}/intel_huc.c (100%)
rename drivers/gpu/drm/i915/{ => gt/uc}/intel_huc.h (100%)
rename drivers/gpu/drm/i915/{ => gt/uc}/intel_huc_fw.c (100%)
rename drivers/gpu/drm/i915/{ => gt/uc}/intel_huc_fw.h (100%)
rename drivers/gpu/drm/i915/{ => gt/uc}/intel_uc.c (100%)
rename drivers/gpu/drm/i915/{ => gt/uc}/intel_uc.h (100%)
rename drivers/gpu/drm/i915/{ => gt/uc}/intel_uc_fw.c (100%)
rename drivers/gpu/drm/i915/{ => gt/uc}/intel_uc_fw.h (100%)
rename drivers/gpu/drm/i915/{selftests/intel_guc.c => gt/uc/selftest_guc.c} (100%)
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 5266dbeab01f..524516251a40 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -139,16 +139,17 @@ i915-y += \
intel_wopcm.o
# general-purpose microcontroller (GuC) support
-i915-y += intel_uc.o \
- intel_uc_fw.o \
- intel_guc.o \
- intel_guc_ads.o \
- intel_guc_ct.o \
- intel_guc_fw.o \
- intel_guc_log.o \
- intel_guc_submission.o \
- intel_huc.o \
- intel_huc_fw.o
+obj-y += gt/uc/
+i915-y += gt/uc/intel_uc.o \
+ gt/uc/intel_uc_fw.o \
+ gt/uc/intel_guc.o \
+ gt/uc/intel_guc_ads.o \
+ gt/uc/intel_guc_ct.o \
+ gt/uc/intel_guc_fw.o \
+ gt/uc/intel_guc_log.o \
+ gt/uc/intel_guc_submission.o \
+ gt/uc/intel_huc.o \
+ gt/uc/intel_huc_fw.o
# modesetting core code
obj-y += display/
--git a/drivers/gpu/drm/i915/Makefile.header-test b/drivers/gpu/drm/i915/Makefile.header-test
index 2fd61869bdaa..88ad1ad31c9b 100644
--- a/drivers/gpu/drm/i915/Makefile.header-test
+++ b/drivers/gpu/drm/i915/Makefile.header-test
@@ -19,14 +19,10 @@ header_test := \
i915_vgpu.h \
intel_csr.h \
intel_drv.h \
- intel_guc_ct.h \
- intel_guc_fwif.h \
- intel_guc_reg.h \
intel_gvt.h \
intel_pm.h \
intel_runtime_pm.h \
intel_sideband.h \
- intel_uc_fw.h \
intel_uncore.h \
intel_wakeref.h
diff --git a/drivers/gpu/drm/i915/gt/intel_reset.c b/drivers/gpu/drm/i915/gt/intel_reset.c
index adfdb908587f..9abfa28c3020 100644
--- a/drivers/gpu/drm/i915/gt/intel_reset.c
+++ b/drivers/gpu/drm/i915/gt/intel_reset.c
@@ -19,7 +19,7 @@
#include "intel_gt_pm.h"
#include "intel_reset.h"
-#include "intel_guc.h"
+#include "uc/intel_guc.h"
#define RESET_MAX_RETRIES 3
diff --git a/drivers/gpu/drm/i915/gt/uc/Makefile b/drivers/gpu/drm/i915/gt/uc/Makefile
new file mode 100644
index 000000000000..db9718aa3ee9
--- /dev/null
+++ b/drivers/gpu/drm/i915/gt/uc/Makefile
@@ -0,0 +1,5 @@
+# For building individual subdir files on the command line
+subdir-ccflags-y += -I$(srctree)/$(src)/../..
+
+# Extra header tests
+include $(src)/Makefile.header-test
--git a/drivers/gpu/drm/i915/gt/uc/Makefile.header-test b/drivers/gpu/drm/i915/gt/uc/Makefile.header-test
new file mode 100644
index 000000000000..61e06cbb4b32
--- /dev/null
+++ b/drivers/gpu/drm/i915/gt/uc/Makefile.header-test
@@ -0,0 +1,16 @@
+# SPDX-License-Identifier: MIT
+# Copyright © 2019 Intel Corporation
+
+# Test the headers are compilable as standalone units
+header_test := $(notdir $(wildcard $(src)/*.h))
+
+quiet_cmd_header_test = HDRTEST $@
+ cmd_header_test = echo "\#include \"$(<F)\"" > $@
+
+header_test_%.c: %.h
+ $(call cmd,header_test)
+
+extra-$(CONFIG_DRM_I915_WERROR) += \
+ $(foreach h,$(header_test),$(patsubst %.h,header_test_%.o,$(h)))
+
+clean-files += $(foreach h,$(header_test),$(patsubst %.h,header_test_%.c,$(h)))
diff --git a/drivers/gpu/drm/i915/intel_guc.c b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
similarity index 100%
rename from drivers/gpu/drm/i915/intel_guc.c
rename to drivers/gpu/drm/i915/gt/uc/intel_guc.c
diff --git a/drivers/gpu/drm/i915/intel_guc.h b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
similarity index 100%
rename from drivers/gpu/drm/i915/intel_guc.h
rename to drivers/gpu/drm/i915/gt/uc/intel_guc.h
diff --git a/drivers/gpu/drm/i915/intel_guc_ads.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
similarity index 100%
rename from drivers/gpu/drm/i915/intel_guc_ads.c
rename to drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
diff --git a/drivers/gpu/drm/i915/intel_guc_ads.h b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.h
similarity index 100%
rename from drivers/gpu/drm/i915/intel_guc_ads.h
rename to drivers/gpu/drm/i915/gt/uc/intel_guc_ads.h
diff --git a/drivers/gpu/drm/i915/intel_guc_ct.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
similarity index 100%
rename from drivers/gpu/drm/i915/intel_guc_ct.c
rename to drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
diff --git a/drivers/gpu/drm/i915/intel_guc_ct.h b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h
similarity index 100%
rename from drivers/gpu/drm/i915/intel_guc_ct.h
rename to drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h
diff --git a/drivers/gpu/drm/i915/intel_guc_fw.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c
similarity index 100%
rename from drivers/gpu/drm/i915/intel_guc_fw.c
rename to drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c
diff --git a/drivers/gpu/drm/i915/intel_guc_fw.h b/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.h
similarity index 100%
rename from drivers/gpu/drm/i915/intel_guc_fw.h
rename to drivers/gpu/drm/i915/gt/uc/intel_guc_fw.h
diff --git a/drivers/gpu/drm/i915/intel_guc_fwif.h b/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
similarity index 100%
rename from drivers/gpu/drm/i915/intel_guc_fwif.h
rename to drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
diff --git a/drivers/gpu/drm/i915/intel_guc_log.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_log.c
similarity index 100%
rename from drivers/gpu/drm/i915/intel_guc_log.c
rename to drivers/gpu/drm/i915/gt/uc/intel_guc_log.c
diff --git a/drivers/gpu/drm/i915/intel_guc_log.h b/drivers/gpu/drm/i915/gt/uc/intel_guc_log.h
similarity index 100%
rename from drivers/gpu/drm/i915/intel_guc_log.h
rename to drivers/gpu/drm/i915/gt/uc/intel_guc_log.h
diff --git a/drivers/gpu/drm/i915/intel_guc_reg.h b/drivers/gpu/drm/i915/gt/uc/intel_guc_reg.h
similarity index 100%
rename from drivers/gpu/drm/i915/intel_guc_reg.h
rename to drivers/gpu/drm/i915/gt/uc/intel_guc_reg.h
diff --git a/drivers/gpu/drm/i915/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
similarity index 99%
rename from drivers/gpu/drm/i915/intel_guc_submission.c
rename to drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index 30692f8289bd..f015f7dee453 100644
--- a/drivers/gpu/drm/i915/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -24,12 +24,13 @@
#include <linux/circ_buf.h>
-#include "gt/intel_engine_pm.h"
-#include "gt/intel_lrc_reg.h"
-#include "gt/intel_context.h"
#include "gem/i915_gem_context.h"
+#include "gt/intel_context.h"
+#include "gt/intel_engine_pm.h"
+#include "gt/intel_lrc_reg.h"
#include "intel_guc_submission.h"
+
#include "i915_drv.h"
enum {
@@ -1162,5 +1163,5 @@ void intel_guc_submission_disable(struct intel_guc *guc)
}
#if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
-#include "selftests/intel_guc.c"
+#include "selftest_guc.c"
#endif
diff --git a/drivers/gpu/drm/i915/intel_guc_submission.h b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.h
similarity index 100%
rename from drivers/gpu/drm/i915/intel_guc_submission.h
rename to drivers/gpu/drm/i915/gt/uc/intel_guc_submission.h
diff --git a/drivers/gpu/drm/i915/intel_huc.c b/drivers/gpu/drm/i915/gt/uc/intel_huc.c
similarity index 100%
rename from drivers/gpu/drm/i915/intel_huc.c
rename to drivers/gpu/drm/i915/gt/uc/intel_huc.c
diff --git a/drivers/gpu/drm/i915/intel_huc.h b/drivers/gpu/drm/i915/gt/uc/intel_huc.h
similarity index 100%
rename from drivers/gpu/drm/i915/intel_huc.h
rename to drivers/gpu/drm/i915/gt/uc/intel_huc.h
diff --git a/drivers/gpu/drm/i915/intel_huc_fw.c b/drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c
similarity index 100%
rename from drivers/gpu/drm/i915/intel_huc_fw.c
rename to drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c
diff --git a/drivers/gpu/drm/i915/intel_huc_fw.h b/drivers/gpu/drm/i915/gt/uc/intel_huc_fw.h
similarity index 100%
rename from drivers/gpu/drm/i915/intel_huc_fw.h
rename to drivers/gpu/drm/i915/gt/uc/intel_huc_fw.h
diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
similarity index 100%
rename from drivers/gpu/drm/i915/intel_uc.c
rename to drivers/gpu/drm/i915/gt/uc/intel_uc.c
diff --git a/drivers/gpu/drm/i915/intel_uc.h b/drivers/gpu/drm/i915/gt/uc/intel_uc.h
similarity index 100%
rename from drivers/gpu/drm/i915/intel_uc.h
rename to drivers/gpu/drm/i915/gt/uc/intel_uc.h
diff --git a/drivers/gpu/drm/i915/intel_uc_fw.c b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
similarity index 100%
rename from drivers/gpu/drm/i915/intel_uc_fw.c
rename to drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
diff --git a/drivers/gpu/drm/i915/intel_uc_fw.h b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.h
similarity index 100%
rename from drivers/gpu/drm/i915/intel_uc_fw.h
rename to drivers/gpu/drm/i915/gt/uc/intel_uc_fw.h
diff --git a/drivers/gpu/drm/i915/selftests/intel_guc.c b/drivers/gpu/drm/i915/gt/uc/selftest_guc.c
similarity index 100%
rename from drivers/gpu/drm/i915/selftests/intel_guc.c
rename to drivers/gpu/drm/i915/gt/uc/selftest_guc.c
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index dc65a6131a5b..c00ccd736dea 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -40,12 +40,12 @@
#include "gem/i915_gem_context.h"
#include "gt/intel_reset.h"
+#include "gt/uc/intel_guc_submission.h"
#include "i915_debugfs.h"
#include "i915_irq.h"
#include "intel_csr.h"
#include "intel_drv.h"
-#include "intel_guc_submission.h"
#include "intel_pm.h"
#include "intel_sideband.h"
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 794c6814a6d0..4a8d90304e21 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -65,6 +65,7 @@
#include "gt/intel_gt_pm.h"
#include "gt/intel_reset.h"
#include "gt/intel_workarounds.h"
+#include "gt/uc/intel_uc.h"
#include "i915_debugfs.h"
#include "i915_drv.h"
@@ -76,7 +77,6 @@
#include "intel_csr.h"
#include "intel_drv.h"
#include "intel_pm.h"
-#include "intel_uc.h"
static struct drm_driver driver;
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 76116e44b7e1..b172d9ee3041 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -74,10 +74,10 @@
#include "gt/intel_engine.h"
#include "gt/intel_gt_types.h"
#include "gt/intel_workarounds.h"
+#include "gt/uc/intel_uc.h"
#include "intel_device_info.h"
#include "intel_runtime_pm.h"
-#include "intel_uc.h"
#include "intel_uncore.h"
#include "intel_wakeref.h"
#include "intel_wopcm.h"
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.h b/drivers/gpu/drm/i915/i915_gpu_error.h
index 2ecd0c6a1c94..6936527670a4 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.h
+++ b/drivers/gpu/drm/i915/i915_gpu_error.h
@@ -14,9 +14,9 @@
#include <drm/drm_mm.h>
#include "gt/intel_engine.h"
+#include "gt/uc/intel_uc_fw.h"
#include "intel_device_info.h"
-#include "intel_uc_fw.h"
#include "i915_gem.h"
#include "i915_gem_gtt.h"
--
2.20.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH 08/12] drm/i915/uc: move GuC/HuC inside intel_gt under a new intel_uc
2019-07-10 0:54 [PATCH 00/12] GT-fy the uc code Daniele Ceraolo Spurio
` (6 preceding siblings ...)
2019-07-10 0:54 ` [PATCH 07/12] drm/i915/uc: move GuC and HuC files under gt/uc/ Daniele Ceraolo Spurio
@ 2019-07-10 0:54 ` Daniele Ceraolo Spurio
2019-07-10 18:22 ` Michal Wajdeczko
2019-07-10 0:54 ` [PATCH 09/12] drm/i915/uc: Move intel functions to intel_uc Daniele Ceraolo Spurio
` (7 subsequent siblings)
15 siblings, 1 reply; 28+ messages in thread
From: Daniele Ceraolo Spurio @ 2019-07-10 0:54 UTC (permalink / raw)
To: intel-gfx
Being part of the GT HW, it make sense to keep the guc/huc structures
inside the GT structure. To help with the encapsulation work done by the
following patches, both structures are placed inside a new intel_uc
container. Although this results in code with ugly nested dereferences
(i915->gt.uc.guc...), it saves us the extra work required in moving
the structures twice (i915 -> gt -> uc). The following patches will
reduce the number of places where we try to access the guc/huc
structures directly from i915 and reduce the ugliness.
Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
---
drivers/gpu/drm/i915/gt/intel_gt_types.h | 4 ++
drivers/gpu/drm/i915/gt/intel_reset.c | 6 +--
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 2 +-
drivers/gpu/drm/i915/gt/uc/intel_huc.c | 4 +-
drivers/gpu/drm/i915/gt/uc/intel_uc.c | 52 +++++++++----------
drivers/gpu/drm/i915/gt/uc/intel_uc.h | 5 ++
drivers/gpu/drm/i915/gt/uc/selftest_guc.c | 4 +-
drivers/gpu/drm/i915/i915_debugfs.c | 26 +++++-----
drivers/gpu/drm/i915/i915_drv.c | 2 +-
drivers/gpu/drm/i915/i915_drv.h | 7 +--
drivers/gpu/drm/i915/i915_gpu_error.c | 11 ++--
drivers/gpu/drm/i915/i915_irq.c | 6 +--
drivers/gpu/drm/i915/intel_wopcm.c | 4 +-
13 files changed, 69 insertions(+), 64 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_types.h b/drivers/gpu/drm/i915/gt/intel_gt_types.h
index 3563ce970102..b711252ff427 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h
@@ -13,6 +13,8 @@
#include <linux/spinlock.h>
#include <linux/types.h>
+#include "uc/intel_uc.h"
+
#include "i915_vma.h"
#include "intel_wakeref.h"
@@ -25,6 +27,8 @@ struct intel_gt {
struct intel_uncore *uncore;
struct i915_ggtt *ggtt;
+ struct intel_uc uc;
+
struct intel_gt_timelines {
struct mutex mutex; /* protects list */
struct list_head active_list;
diff --git a/drivers/gpu/drm/i915/gt/intel_reset.c b/drivers/gpu/drm/i915/gt/intel_reset.c
index 9abfa28c3020..ccedea636ba3 100644
--- a/drivers/gpu/drm/i915/gt/intel_reset.c
+++ b/drivers/gpu/drm/i915/gt/intel_reset.c
@@ -1109,14 +1109,14 @@ int i915_reset_engine(struct intel_engine_cs *engine, const char *msg)
"Resetting %s for %s\n", engine->name, msg);
error->reset_engine_count[engine->id]++;
- if (!engine->i915->guc.execbuf_client)
+ if (!engine->gt->uc.guc.execbuf_client)
ret = intel_gt_reset_engine(engine->i915, engine);
else
- ret = intel_guc_reset_engine(&engine->i915->guc, engine);
+ ret = intel_guc_reset_engine(&engine->gt->uc.guc, engine);
if (ret) {
/* If we fail here, we expect to fallback to a global reset */
DRM_DEBUG_DRIVER("%sFailed to reset %s, ret=%d\n",
- engine->i915->guc.execbuf_client ? "GuC " : "",
+ engine->gt->uc.guc.execbuf_client ? "GuC " : "",
engine->name, ret);
goto out;
}
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index f015f7dee453..23906228b9b4 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -509,7 +509,7 @@ static void guc_submit(struct intel_engine_cs *engine,
struct i915_request **out,
struct i915_request **end)
{
- struct intel_guc *guc = &engine->i915->guc;
+ struct intel_guc *guc = &engine->gt->uc.guc;
struct intel_guc_client *client = guc->execbuf_client;
spin_lock(&client->wq_lock);
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_huc.c b/drivers/gpu/drm/i915/gt/uc/intel_huc.c
index 2a41ee89a16d..581c9c3d4fc0 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_huc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_huc.c
@@ -47,7 +47,7 @@ void intel_huc_init_early(struct intel_huc *huc)
static int intel_huc_rsa_data_create(struct intel_huc *huc)
{
struct drm_i915_private *i915 = huc_to_i915(huc);
- struct intel_guc *guc = &i915->guc;
+ struct intel_guc *guc = &i915->gt.uc.guc;
struct i915_vma *vma;
void *vaddr;
@@ -113,7 +113,7 @@ void intel_huc_fini(struct intel_huc *huc)
int intel_huc_auth(struct intel_huc *huc)
{
struct drm_i915_private *i915 = huc_to_i915(huc);
- struct intel_guc *guc = &i915->guc;
+ struct intel_guc *guc = &i915->gt.uc.guc;
int ret;
if (huc->fw.load_status != INTEL_UC_FIRMWARE_SUCCESS)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc.c b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
index 6193b87855e0..e2080da2e1e4 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_uc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
@@ -54,8 +54,8 @@ static int __intel_uc_reset_hw(struct drm_i915_private *dev_priv)
static int __get_platform_enable_guc(struct drm_i915_private *i915)
{
- struct intel_uc_fw *guc_fw = &i915->guc.fw;
- struct intel_uc_fw *huc_fw = &i915->huc.fw;
+ struct intel_uc_fw *guc_fw = &i915->gt.uc.guc.fw;
+ struct intel_uc_fw *huc_fw = &i915->gt.uc.huc.fw;
int enable_guc = 0;
/* Default is to use HuC if we know GuC and HuC firmwares */
@@ -71,7 +71,7 @@ static int __get_default_guc_log_level(struct drm_i915_private *i915)
{
int guc_log_level;
- if (!intel_uc_fw_supported(&i915->guc.fw) ||
+ if (!intel_uc_fw_supported(&i915->gt.uc.guc.fw) ||
!intel_uc_is_using_guc(i915))
guc_log_level = GUC_LOG_LEVEL_DISABLED;
else if (IS_ENABLED(CONFIG_DRM_I915_DEBUG) ||
@@ -104,8 +104,8 @@ static int __get_default_guc_log_level(struct drm_i915_private *i915)
*/
static void sanitize_options_early(struct drm_i915_private *i915)
{
- struct intel_uc_fw *guc_fw = &i915->guc.fw;
- struct intel_uc_fw *huc_fw = &i915->huc.fw;
+ struct intel_uc_fw *guc_fw = &i915->gt.uc.guc.fw;
+ struct intel_uc_fw *huc_fw = &i915->gt.uc.huc.fw;
/* A negative value means "use platform default" */
if (i915_modparams.enable_guc < 0)
@@ -174,8 +174,8 @@ static void sanitize_options_early(struct drm_i915_private *i915)
void intel_uc_init_early(struct drm_i915_private *i915)
{
- struct intel_guc *guc = &i915->guc;
- struct intel_huc *huc = &i915->huc;
+ struct intel_guc *guc = &i915->gt.uc.guc;
+ struct intel_huc *huc = &i915->gt.uc.huc;
intel_guc_init_early(guc);
intel_huc_init_early(huc);
@@ -185,7 +185,7 @@ void intel_uc_init_early(struct drm_i915_private *i915)
void intel_uc_cleanup_early(struct drm_i915_private *i915)
{
- struct intel_guc *guc = &i915->guc;
+ struct intel_guc *guc = &i915->gt.uc.guc;
guc_free_load_err_log(guc);
}
@@ -199,7 +199,7 @@ void intel_uc_cleanup_early(struct drm_i915_private *i915)
*/
void intel_uc_init_mmio(struct drm_i915_private *i915)
{
- intel_guc_init_send_regs(&i915->guc);
+ intel_guc_init_send_regs(&i915->gt.uc.guc);
}
static void guc_capture_load_err_log(struct intel_guc *guc)
@@ -351,10 +351,10 @@ void intel_uc_fetch_firmwares(struct drm_i915_private *i915)
if (!USES_GUC(i915))
return;
- intel_uc_fw_fetch(i915, &i915->guc.fw);
+ intel_uc_fw_fetch(i915, &i915->gt.uc.guc.fw);
if (USES_HUC(i915))
- intel_uc_fw_fetch(i915, &i915->huc.fw);
+ intel_uc_fw_fetch(i915, &i915->gt.uc.huc.fw);
}
void intel_uc_cleanup_firmwares(struct drm_i915_private *i915)
@@ -363,15 +363,15 @@ void intel_uc_cleanup_firmwares(struct drm_i915_private *i915)
return;
if (USES_HUC(i915))
- intel_uc_fw_cleanup_fetch(&i915->huc.fw);
+ intel_uc_fw_cleanup_fetch(&i915->gt.uc.huc.fw);
- intel_uc_fw_cleanup_fetch(&i915->guc.fw);
+ intel_uc_fw_cleanup_fetch(&i915->gt.uc.guc.fw);
}
int intel_uc_init(struct drm_i915_private *i915)
{
- struct intel_guc *guc = &i915->guc;
- struct intel_huc *huc = &i915->huc;
+ struct intel_guc *guc = &i915->gt.uc.guc;
+ struct intel_huc *huc = &i915->gt.uc.huc;
int ret;
if (!USES_GUC(i915))
@@ -415,7 +415,7 @@ int intel_uc_init(struct drm_i915_private *i915)
void intel_uc_fini(struct drm_i915_private *i915)
{
- struct intel_guc *guc = &i915->guc;
+ struct intel_guc *guc = &i915->gt.uc.guc;
if (!USES_GUC(i915))
return;
@@ -426,15 +426,15 @@ void intel_uc_fini(struct drm_i915_private *i915)
intel_guc_submission_fini(guc);
if (USES_HUC(i915))
- intel_huc_fini(&i915->huc);
+ intel_huc_fini(&i915->gt.uc.huc);
intel_guc_fini(guc);
}
static void __uc_sanitize(struct drm_i915_private *i915)
{
- struct intel_guc *guc = &i915->guc;
- struct intel_huc *huc = &i915->huc;
+ struct intel_guc *guc = &i915->gt.uc.guc;
+ struct intel_huc *huc = &i915->gt.uc.huc;
GEM_BUG_ON(!intel_uc_fw_supported(&guc->fw));
@@ -454,8 +454,8 @@ void intel_uc_sanitize(struct drm_i915_private *i915)
int intel_uc_init_hw(struct drm_i915_private *i915)
{
- struct intel_guc *guc = &i915->guc;
- struct intel_huc *huc = &i915->huc;
+ struct intel_guc *guc = &i915->gt.uc.guc;
+ struct intel_huc *huc = &i915->gt.uc.huc;
int ret, attempts;
if (!USES_GUC(i915))
@@ -553,7 +553,7 @@ int intel_uc_init_hw(struct drm_i915_private *i915)
void intel_uc_fini_hw(struct drm_i915_private *i915)
{
- struct intel_guc *guc = &i915->guc;
+ struct intel_guc *guc = &i915->gt.uc.guc;
if (!intel_guc_is_loaded(guc))
return;
@@ -575,7 +575,7 @@ void intel_uc_fini_hw(struct drm_i915_private *i915)
*/
void intel_uc_reset_prepare(struct drm_i915_private *i915)
{
- struct intel_guc *guc = &i915->guc;
+ struct intel_guc *guc = &i915->gt.uc.guc;
if (!intel_guc_is_loaded(guc))
return;
@@ -586,7 +586,7 @@ void intel_uc_reset_prepare(struct drm_i915_private *i915)
void intel_uc_runtime_suspend(struct drm_i915_private *i915)
{
- struct intel_guc *guc = &i915->guc;
+ struct intel_guc *guc = &i915->gt.uc.guc;
int err;
if (!intel_guc_is_loaded(guc))
@@ -601,7 +601,7 @@ void intel_uc_runtime_suspend(struct drm_i915_private *i915)
void intel_uc_suspend(struct drm_i915_private *i915)
{
- struct intel_guc *guc = &i915->guc;
+ struct intel_guc *guc = &i915->gt.uc.guc;
intel_wakeref_t wakeref;
if (!intel_guc_is_loaded(guc))
@@ -613,7 +613,7 @@ void intel_uc_suspend(struct drm_i915_private *i915)
int intel_uc_resume(struct drm_i915_private *i915)
{
- struct intel_guc *guc = &i915->guc;
+ struct intel_guc *guc = &i915->gt.uc.guc;
int err;
if (!intel_guc_is_loaded(guc))
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc.h b/drivers/gpu/drm/i915/gt/uc/intel_uc.h
index 5a1383e192dd..a2fdc84afff2 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_uc.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_uc.h
@@ -28,6 +28,11 @@
#include "intel_huc.h"
#include "i915_params.h"
+struct intel_uc {
+ struct intel_guc guc;
+ struct intel_huc huc;
+};
+
void intel_uc_init_early(struct drm_i915_private *dev_priv);
void intel_uc_cleanup_early(struct drm_i915_private *dev_priv);
void intel_uc_init_mmio(struct drm_i915_private *dev_priv);
diff --git a/drivers/gpu/drm/i915/gt/uc/selftest_guc.c b/drivers/gpu/drm/i915/gt/uc/selftest_guc.c
index 6ca76f5a98d4..93f7c930ab18 100644
--- a/drivers/gpu/drm/i915/gt/uc/selftest_guc.c
+++ b/drivers/gpu/drm/i915/gt/uc/selftest_guc.c
@@ -138,7 +138,7 @@ static int igt_guc_clients(void *args)
mutex_lock(&dev_priv->drm.struct_mutex);
wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm);
- guc = &dev_priv->guc;
+ guc = &dev_priv->gt.uc.guc;
if (!guc) {
pr_err("No guc object!\n");
err = -EINVAL;
@@ -230,7 +230,7 @@ static int igt_guc_doorbells(void *arg)
mutex_lock(&dev_priv->drm.struct_mutex);
wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm);
- guc = &dev_priv->guc;
+ guc = &dev_priv->gt.uc.guc;
if (!guc) {
pr_err("No guc object!\n");
err = -EINVAL;
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index c00ccd736dea..f082d54b0b75 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1885,7 +1885,7 @@ static int i915_huc_load_status_info(struct seq_file *m, void *data)
return -ENODEV;
p = drm_seq_file_printer(m);
- intel_uc_fw_dump(&dev_priv->huc.fw, &p);
+ intel_uc_fw_dump(&dev_priv->gt.uc.huc.fw, &p);
with_intel_runtime_pm(&dev_priv->runtime_pm, wakeref)
seq_printf(m, "\nHuC status 0x%08x:\n", I915_READ(HUC_STATUS2));
@@ -1903,7 +1903,7 @@ static int i915_guc_load_status_info(struct seq_file *m, void *data)
return -ENODEV;
p = drm_seq_file_printer(m);
- intel_uc_fw_dump(&dev_priv->guc.fw, &p);
+ intel_uc_fw_dump(&dev_priv->gt.uc.guc.fw, &p);
with_intel_runtime_pm(&dev_priv->runtime_pm, wakeref) {
u32 tmp = I915_READ(GUC_STATUS);
@@ -1946,7 +1946,7 @@ stringify_guc_log_type(enum guc_log_buffer_type type)
static void i915_guc_log_info(struct seq_file *m,
struct drm_i915_private *dev_priv)
{
- struct intel_guc_log *log = &dev_priv->guc.log;
+ struct intel_guc_log *log = &dev_priv->gt.uc.guc.log;
enum guc_log_buffer_type type;
if (!intel_guc_log_relay_enabled(log)) {
@@ -1992,7 +1992,7 @@ static void i915_guc_client_info(struct seq_file *m,
static int i915_guc_info(struct seq_file *m, void *data)
{
struct drm_i915_private *dev_priv = node_to_i915(m->private);
- const struct intel_guc *guc = &dev_priv->guc;
+ const struct intel_guc *guc = &dev_priv->gt.uc.guc;
if (!USES_GUC(dev_priv))
return -ENODEV;
@@ -2019,7 +2019,7 @@ static int i915_guc_info(struct seq_file *m, void *data)
static int i915_guc_stage_pool(struct seq_file *m, void *data)
{
struct drm_i915_private *dev_priv = node_to_i915(m->private);
- const struct intel_guc *guc = &dev_priv->guc;
+ const struct intel_guc *guc = &dev_priv->gt.uc.guc;
struct guc_stage_desc *desc = guc->stage_desc_pool_vaddr;
intel_engine_mask_t tmp;
int index;
@@ -2082,9 +2082,9 @@ static int i915_guc_log_dump(struct seq_file *m, void *data)
return -ENODEV;
if (dump_load_err)
- obj = dev_priv->guc.load_err_log;
- else if (dev_priv->guc.log.vma)
- obj = dev_priv->guc.log.vma->obj;
+ obj = dev_priv->gt.uc.guc.load_err_log;
+ else if (dev_priv->gt.uc.guc.log.vma)
+ obj = dev_priv->gt.uc.guc.log.vma->obj;
if (!obj)
return 0;
@@ -2115,7 +2115,7 @@ static int i915_guc_log_level_get(void *data, u64 *val)
if (!USES_GUC(dev_priv))
return -ENODEV;
- *val = intel_guc_log_get_level(&dev_priv->guc.log);
+ *val = intel_guc_log_get_level(&dev_priv->gt.uc.guc.log);
return 0;
}
@@ -2127,7 +2127,7 @@ static int i915_guc_log_level_set(void *data, u64 val)
if (!USES_GUC(dev_priv))
return -ENODEV;
- return intel_guc_log_set_level(&dev_priv->guc.log, val);
+ return intel_guc_log_set_level(&dev_priv->gt.uc.guc.log, val);
}
DEFINE_SIMPLE_ATTRIBUTE(i915_guc_log_level_fops,
@@ -2141,9 +2141,9 @@ static int i915_guc_log_relay_open(struct inode *inode, struct file *file)
if (!USES_GUC(dev_priv))
return -ENODEV;
- file->private_data = &dev_priv->guc.log;
+ file->private_data = &dev_priv->gt.uc.guc.log;
- return intel_guc_log_relay_open(&dev_priv->guc.log);
+ return intel_guc_log_relay_open(&dev_priv->gt.uc.guc.log);
}
static ssize_t
@@ -2163,7 +2163,7 @@ static int i915_guc_log_relay_release(struct inode *inode, struct file *file)
{
struct drm_i915_private *dev_priv = inode->i_private;
- intel_guc_log_relay_close(&dev_priv->guc.log);
+ intel_guc_log_relay_close(&dev_priv->gt.uc.guc.log);
return 0;
}
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 4a8d90304e21..e7c89d320375 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -420,7 +420,7 @@ static int i915_getparam_ioctl(struct drm_device *dev, void *data,
value = sseu->min_eu_in_pool;
break;
case I915_PARAM_HUC_STATUS:
- value = intel_huc_check_status(&dev_priv->huc);
+ value = intel_huc_check_status(&dev_priv->gt.uc.huc);
if (value < 0)
return value;
break;
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index b172d9ee3041..c4757cbf9a33 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1348,9 +1348,6 @@ struct drm_i915_private {
struct intel_wopcm wopcm;
- struct intel_huc huc;
- struct intel_guc guc;
-
struct intel_csr csr;
struct intel_gmbus gmbus[GMBUS_NUM_PINS];
@@ -1907,12 +1904,12 @@ static inline struct drm_i915_private *wopcm_to_i915(struct intel_wopcm *wopcm)
static inline struct drm_i915_private *guc_to_i915(struct intel_guc *guc)
{
- return container_of(guc, struct drm_i915_private, guc);
+ return container_of(guc, struct drm_i915_private, gt.uc.guc);
}
static inline struct drm_i915_private *huc_to_i915(struct intel_huc *huc)
{
- return container_of(huc, struct drm_i915_private, huc);
+ return container_of(huc, struct drm_i915_private, gt.uc.huc);
}
/* Simple iterator over all initialised engines */
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c
index 5489cd879315..78e388fa059c 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -1552,21 +1552,22 @@ static void capture_uc_state(struct i915_gpu_state *error)
{
struct drm_i915_private *i915 = error->i915;
struct i915_error_uc *error_uc = &error->uc;
+ struct intel_uc *uc = &i915->gt.uc;
/* Capturing uC state won't be useful if there is no GuC */
if (!error->device_info.has_guc)
return;
- error_uc->guc_fw = i915->guc.fw;
- error_uc->huc_fw = i915->huc.fw;
+ error_uc->guc_fw = uc->guc.fw;
+ error_uc->huc_fw = uc->huc.fw;
/* Non-default firmware paths will be specified by the modparam.
* As modparams are generally accesible from the userspace make
* explicit copies of the firmware paths.
*/
- error_uc->guc_fw.path = kstrdup(i915->guc.fw.path, GFP_ATOMIC);
- error_uc->huc_fw.path = kstrdup(i915->huc.fw.path, GFP_ATOMIC);
- error_uc->guc_log = i915_error_object_create(i915, i915->guc.log.vma);
+ error_uc->guc_fw.path = kstrdup(uc->guc.fw.path, GFP_ATOMIC);
+ error_uc->huc_fw.path = kstrdup(uc->huc.fw.path, GFP_ATOMIC);
+ error_uc->guc_log = i915_error_object_create(i915, uc->guc.log.vma);
}
/* Capture all registers which don't fit into another category. */
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 42d6d8bfac70..78c748cb9df8 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -1655,7 +1655,7 @@ static void gen8_gt_irq_handler(struct drm_i915_private *i915,
if (master_ctl & (GEN8_GT_PM_IRQ | GEN8_GT_GUC_IRQ)) {
gen6_rps_irq_handler(i915, gt_iir[2]);
- guc_irq_handler(&i915->guc, gt_iir[2] >> 16);
+ guc_irq_handler(&i915->gt.uc.guc, gt_iir[2] >> 16);
}
}
@@ -3082,10 +3082,8 @@ static void
gen11_other_irq_handler(struct intel_gt *gt, const u8 instance,
const u16 iir)
{
- struct drm_i915_private *i915 = gt->i915;
-
if (instance == OTHER_GUC_INSTANCE)
- return guc_irq_handler(&i915->guc, iir);
+ return guc_irq_handler(>->uc.guc, iir);
if (instance == OTHER_GTPM_INSTANCE)
return gen11_rps_irq_handler(gt, iir);
diff --git a/drivers/gpu/drm/i915/intel_wopcm.c b/drivers/gpu/drm/i915/intel_wopcm.c
index 8c850785e4b4..0c05c5e6c7be 100644
--- a/drivers/gpu/drm/i915/intel_wopcm.c
+++ b/drivers/gpu/drm/i915/intel_wopcm.c
@@ -164,8 +164,8 @@ static inline int check_hw_restriction(struct drm_i915_private *i915,
int intel_wopcm_init(struct intel_wopcm *wopcm)
{
struct drm_i915_private *i915 = wopcm_to_i915(wopcm);
- u32 guc_fw_size = intel_uc_fw_get_upload_size(&i915->guc.fw);
- u32 huc_fw_size = intel_uc_fw_get_upload_size(&i915->huc.fw);
+ u32 guc_fw_size = intel_uc_fw_get_upload_size(&i915->gt.uc.guc.fw);
+ u32 huc_fw_size = intel_uc_fw_get_upload_size(&i915->gt.uc.huc.fw);
u32 ctx_rsvd = context_reserved_size(i915);
u32 guc_wopcm_base;
u32 guc_wopcm_size;
--
2.20.1
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH 09/12] drm/i915/uc: Move intel functions to intel_uc
2019-07-10 0:54 [PATCH 00/12] GT-fy the uc code Daniele Ceraolo Spurio
` (7 preceding siblings ...)
2019-07-10 0:54 ` [PATCH 08/12] drm/i915/uc: move GuC/HuC inside intel_gt under a new intel_uc Daniele Ceraolo Spurio
@ 2019-07-10 0:54 ` Daniele Ceraolo Spurio
2019-07-10 18:26 ` Michal Wajdeczko
2019-07-10 0:54 ` [PATCH 10/12] drm/i915/uc: prefer intel_gt over i915 in GuC/HuC paths Daniele Ceraolo Spurio
` (6 subsequent siblings)
15 siblings, 1 reply; 28+ messages in thread
From: Daniele Ceraolo Spurio @ 2019-07-10 0:54 UTC (permalink / raw)
To: intel-gfx
All the intel_uc_* can now be moved to work on the intel_uc structure
for better encapsulation of uc-related actions.
Note: I've introduced uc_to_gt instead of uc_to_i915 because the aim is
to move everything to be gt-focused in the medium term, so we would've
had to replace it soon anyway.
Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
---
drivers/gpu/drm/i915/gem/i915_gem_pm.c | 6 +-
drivers/gpu/drm/i915/gt/intel_gt.h | 5 +
drivers/gpu/drm/i915/gt/intel_reset.c | 2 +-
drivers/gpu/drm/i915/gt/uc/intel_uc.c | 184 ++++++++++++-------------
drivers/gpu/drm/i915/gt/uc/intel_uc.h | 34 ++---
drivers/gpu/drm/i915/i915_drv.c | 14 +-
drivers/gpu/drm/i915/i915_drv.h | 6 +-
drivers/gpu/drm/i915/i915_gem.c | 18 +--
8 files changed, 137 insertions(+), 132 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_pm.c b/drivers/gpu/drm/i915/gem/i915_gem_pm.c
index 4d774376f5b8..3c674c952a78 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_pm.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_pm.c
@@ -173,7 +173,7 @@ void i915_gem_suspend(struct drm_i915_private *i915)
i915_gem_drain_freed_objects(i915);
- intel_uc_suspend(i915);
+ intel_uc_suspend(&i915->gt.uc);
}
static struct drm_i915_gem_object *first_mm_object(struct list_head *list)
@@ -238,7 +238,7 @@ void i915_gem_suspend_late(struct drm_i915_private *i915)
}
spin_unlock_irqrestore(&i915->mm.obj_lock, flags);
- intel_uc_sanitize(i915);
+ intel_uc_sanitize(&i915->gt.uc);
i915_gem_sanitize(i915);
}
@@ -265,7 +265,7 @@ void i915_gem_resume(struct drm_i915_private *i915)
if (intel_gt_resume(&i915->gt))
goto err_wedged;
- intel_uc_resume(i915);
+ intel_uc_resume(&i915->gt.uc);
/* Always reload a context for powersaving. */
if (!i915_gem_load_power_context(i915))
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.h b/drivers/gpu/drm/i915/gt/intel_gt.h
index 1093dcf36f63..880be05a3f4a 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt.h
@@ -11,6 +11,11 @@
struct drm_i915_private;
+static inline struct intel_gt *uc_to_gt(struct intel_uc *uc)
+{
+ return container_of(uc, struct intel_gt, uc);
+}
+
void intel_gt_init_early(struct intel_gt *gt, struct drm_i915_private *i915);
void intel_gt_init_hw(struct drm_i915_private *i915);
diff --git a/drivers/gpu/drm/i915/gt/intel_reset.c b/drivers/gpu/drm/i915/gt/intel_reset.c
index ccedea636ba3..be23f4557111 100644
--- a/drivers/gpu/drm/i915/gt/intel_reset.c
+++ b/drivers/gpu/drm/i915/gt/intel_reset.c
@@ -720,7 +720,7 @@ static intel_engine_mask_t reset_prepare(struct drm_i915_private *i915)
reset_prepare_engine(engine);
}
- intel_uc_reset_prepare(i915);
+ intel_uc_reset_prepare(&i915->gt.uc);
return awake;
}
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc.c b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
index e2080da2e1e4..2062e7ff05e8 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_uc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
@@ -22,19 +22,22 @@
*
*/
+#include "gt/intel_gt.h"
#include "gt/intel_reset.h"
-#include "intel_uc.h"
#include "intel_guc.h"
#include "intel_guc_ads.h"
#include "intel_guc_submission.h"
+#include "intel_uc.h"
+
#include "i915_drv.h"
static void guc_free_load_err_log(struct intel_guc *guc);
/* Reset GuC providing us with fresh state for both GuC and HuC.
*/
-static int __intel_uc_reset_hw(struct drm_i915_private *dev_priv)
+static int __intel_uc_reset_hw(struct intel_uc *uc)
{
+ struct drm_i915_private *dev_priv = uc_to_gt(uc)->i915;
int ret;
u32 guc_status;
@@ -52,10 +55,10 @@ static int __intel_uc_reset_hw(struct drm_i915_private *dev_priv)
return ret;
}
-static int __get_platform_enable_guc(struct drm_i915_private *i915)
+static int __get_platform_enable_guc(struct intel_uc *uc)
{
- struct intel_uc_fw *guc_fw = &i915->gt.uc.guc.fw;
- struct intel_uc_fw *huc_fw = &i915->gt.uc.huc.fw;
+ struct intel_uc_fw *guc_fw = &uc->guc.fw;
+ struct intel_uc_fw *huc_fw = &uc->huc.fw;
int enable_guc = 0;
/* Default is to use HuC if we know GuC and HuC firmwares */
@@ -67,12 +70,11 @@ static int __get_platform_enable_guc(struct drm_i915_private *i915)
return enable_guc;
}
-static int __get_default_guc_log_level(struct drm_i915_private *i915)
+static int __get_default_guc_log_level(struct intel_uc *uc)
{
int guc_log_level;
- if (!intel_uc_fw_supported(&i915->gt.uc.guc.fw) ||
- !intel_uc_is_using_guc(i915))
+ if (!intel_uc_fw_supported(&uc->guc.fw) || !intel_uc_is_using_guc(uc))
guc_log_level = GUC_LOG_LEVEL_DISABLED;
else if (IS_ENABLED(CONFIG_DRM_I915_DEBUG) ||
IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM))
@@ -87,7 +89,7 @@ static int __get_default_guc_log_level(struct drm_i915_private *i915)
/**
* sanitize_options_early - sanitize uC related modparam options
- * @i915: device private
+ * @uc: the intel_uc structure
*
* In case of "enable_guc" option this function will attempt to modify
* it only if it was initially set to "auto(-1)". Default value for this
@@ -102,22 +104,22 @@ static int __get_default_guc_log_level(struct drm_i915_private *i915)
* unless GuC is enabled on given platform and the driver is compiled with
* debug config when this modparam will default to "enable(1..4)".
*/
-static void sanitize_options_early(struct drm_i915_private *i915)
+static void sanitize_options_early(struct intel_uc *uc)
{
- struct intel_uc_fw *guc_fw = &i915->gt.uc.guc.fw;
- struct intel_uc_fw *huc_fw = &i915->gt.uc.huc.fw;
+ struct intel_uc_fw *guc_fw = &uc->guc.fw;
+ struct intel_uc_fw *huc_fw = &uc->huc.fw;
/* A negative value means "use platform default" */
if (i915_modparams.enable_guc < 0)
- i915_modparams.enable_guc = __get_platform_enable_guc(i915);
+ i915_modparams.enable_guc = __get_platform_enable_guc(uc);
DRM_DEBUG_DRIVER("enable_guc=%d (submission:%s huc:%s)\n",
i915_modparams.enable_guc,
- yesno(intel_uc_is_using_guc_submission(i915)),
- yesno(intel_uc_is_using_huc(i915)));
+ yesno(intel_uc_is_using_guc_submission(uc)),
+ yesno(intel_uc_is_using_huc(uc)));
/* Verify GuC firmware availability */
- if (intel_uc_is_using_guc(i915) && !intel_uc_fw_is_selected(guc_fw)) {
+ if (intel_uc_is_using_guc(uc) && !intel_uc_fw_is_selected(guc_fw)) {
DRM_WARN("Incompatible option detected: %s=%d, %s!\n",
"enable_guc", i915_modparams.enable_guc,
!intel_uc_fw_supported(guc_fw) ?
@@ -125,7 +127,7 @@ static void sanitize_options_early(struct drm_i915_private *i915)
}
/* Verify HuC firmware availability */
- if (intel_uc_is_using_huc(i915) && !intel_uc_fw_is_selected(huc_fw)) {
+ if (intel_uc_is_using_huc(uc) && !intel_uc_fw_is_selected(huc_fw)) {
DRM_WARN("Incompatible option detected: %s=%d, %s!\n",
"enable_guc", i915_modparams.enable_guc,
!intel_uc_fw_supported(huc_fw) ?
@@ -133,7 +135,7 @@ static void sanitize_options_early(struct drm_i915_private *i915)
}
/* XXX: GuC submission is unavailable for now */
- if (intel_uc_is_using_guc_submission(i915)) {
+ if (intel_uc_is_using_guc_submission(uc)) {
DRM_INFO("Incompatible option detected: %s=%d, %s!\n",
"enable_guc", i915_modparams.enable_guc,
"GuC submission not supported");
@@ -144,9 +146,9 @@ static void sanitize_options_early(struct drm_i915_private *i915)
/* A negative value means "use platform/config default" */
if (i915_modparams.guc_log_level < 0)
i915_modparams.guc_log_level =
- __get_default_guc_log_level(i915);
+ __get_default_guc_log_level(uc);
- if (i915_modparams.guc_log_level > 0 && !intel_uc_is_using_guc(i915)) {
+ if (i915_modparams.guc_log_level > 0 && !intel_uc_is_using_guc(uc)) {
DRM_WARN("Incompatible option detected: %s=%d, %s!\n",
"guc_log_level", i915_modparams.guc_log_level,
!intel_uc_fw_supported(guc_fw) ?
@@ -172,34 +174,29 @@ static void sanitize_options_early(struct drm_i915_private *i915)
GEM_BUG_ON(i915_modparams.guc_log_level < 0);
}
-void intel_uc_init_early(struct drm_i915_private *i915)
+void intel_uc_init_early(struct intel_uc *uc)
{
- struct intel_guc *guc = &i915->gt.uc.guc;
- struct intel_huc *huc = &i915->gt.uc.huc;
+ intel_guc_init_early(&uc->guc);
+ intel_huc_init_early(&uc->huc);
- intel_guc_init_early(guc);
- intel_huc_init_early(huc);
-
- sanitize_options_early(i915);
+ sanitize_options_early(uc);
}
-void intel_uc_cleanup_early(struct drm_i915_private *i915)
+void intel_uc_cleanup_early(struct intel_uc *uc)
{
- struct intel_guc *guc = &i915->gt.uc.guc;
-
- guc_free_load_err_log(guc);
+ guc_free_load_err_log(&uc->guc);
}
/**
* intel_uc_init_mmio - setup uC MMIO access
- * @i915: device private
+ * @uc: the intel_uc structure
*
* Setup minimal state necessary for MMIO accesses later in the
* initialization sequence.
*/
-void intel_uc_init_mmio(struct drm_i915_private *i915)
+void intel_uc_init_mmio(struct intel_uc *uc)
{
- intel_guc_init_send_regs(&i915->gt.uc.guc);
+ intel_guc_init_send_regs(&uc->guc);
}
static void guc_capture_load_err_log(struct intel_guc *guc)
@@ -346,54 +343,56 @@ static void guc_disable_communication(struct intel_guc *guc)
DRM_INFO("GuC communication disabled\n");
}
-void intel_uc_fetch_firmwares(struct drm_i915_private *i915)
+void intel_uc_fetch_firmwares(struct intel_uc *uc)
{
- if (!USES_GUC(i915))
+ struct drm_i915_private *i915 = uc_to_gt(uc)->i915;
+
+ if (!intel_uc_is_using_guc(uc))
return;
- intel_uc_fw_fetch(i915, &i915->gt.uc.guc.fw);
+ intel_uc_fw_fetch(i915, &uc->guc.fw);
- if (USES_HUC(i915))
- intel_uc_fw_fetch(i915, &i915->gt.uc.huc.fw);
+ if (intel_uc_is_using_huc(uc))
+ intel_uc_fw_fetch(i915, &uc->huc.fw);
}
-void intel_uc_cleanup_firmwares(struct drm_i915_private *i915)
+void intel_uc_cleanup_firmwares(struct intel_uc *uc)
{
- if (!USES_GUC(i915))
+ if (!intel_uc_is_using_guc(uc))
return;
- if (USES_HUC(i915))
- intel_uc_fw_cleanup_fetch(&i915->gt.uc.huc.fw);
+ if (intel_uc_is_using_huc(uc))
+ intel_uc_fw_cleanup_fetch(&uc->huc.fw);
- intel_uc_fw_cleanup_fetch(&i915->gt.uc.guc.fw);
+ intel_uc_fw_cleanup_fetch(&uc->guc.fw);
}
-int intel_uc_init(struct drm_i915_private *i915)
+int intel_uc_init(struct intel_uc *uc)
{
- struct intel_guc *guc = &i915->gt.uc.guc;
- struct intel_huc *huc = &i915->gt.uc.huc;
+ struct intel_guc *guc = &uc->guc;
+ struct intel_huc *huc = &uc->huc;
int ret;
- if (!USES_GUC(i915))
+ if (!intel_uc_is_using_guc(uc))
return 0;
if (!intel_uc_fw_supported(&guc->fw))
return -ENODEV;
/* XXX: GuC submission is unavailable for now */
- GEM_BUG_ON(USES_GUC_SUBMISSION(i915));
+ GEM_BUG_ON(intel_uc_is_using_guc_submission(uc));
ret = intel_guc_init(guc);
if (ret)
return ret;
- if (USES_HUC(i915)) {
+ if (intel_uc_is_using_huc(uc)) {
ret = intel_huc_init(huc);
if (ret)
goto err_guc;
}
- if (USES_GUC_SUBMISSION(i915)) {
+ if (intel_uc_is_using_guc_submission(uc)) {
/*
* This is stuff we need to have available at fw load time
* if we are planning to enable submission later
@@ -406,59 +405,60 @@ int intel_uc_init(struct drm_i915_private *i915)
return 0;
err_huc:
- if (USES_HUC(i915))
+ if (intel_uc_is_using_huc(uc))
intel_huc_fini(huc);
err_guc:
intel_guc_fini(guc);
return ret;
}
-void intel_uc_fini(struct drm_i915_private *i915)
+void intel_uc_fini(struct intel_uc *uc)
{
- struct intel_guc *guc = &i915->gt.uc.guc;
+ struct intel_guc *guc = &uc->guc;
- if (!USES_GUC(i915))
+ if (!intel_uc_is_using_guc(uc))
return;
GEM_BUG_ON(!intel_uc_fw_supported(&guc->fw));
- if (USES_GUC_SUBMISSION(i915))
+ if (intel_uc_is_using_guc_submission(uc))
intel_guc_submission_fini(guc);
- if (USES_HUC(i915))
- intel_huc_fini(&i915->gt.uc.huc);
+ if (intel_uc_is_using_huc(uc))
+ intel_huc_fini(&uc->huc);
intel_guc_fini(guc);
}
-static void __uc_sanitize(struct drm_i915_private *i915)
+static void __uc_sanitize(struct intel_uc *uc)
{
- struct intel_guc *guc = &i915->gt.uc.guc;
- struct intel_huc *huc = &i915->gt.uc.huc;
+ struct intel_guc *guc = &uc->guc;
+ struct intel_huc *huc = &uc->huc;
GEM_BUG_ON(!intel_uc_fw_supported(&guc->fw));
intel_huc_sanitize(huc);
intel_guc_sanitize(guc);
- __intel_uc_reset_hw(i915);
+ __intel_uc_reset_hw(uc);
}
-void intel_uc_sanitize(struct drm_i915_private *i915)
+void intel_uc_sanitize(struct intel_uc *uc)
{
- if (!USES_GUC(i915))
+ if (!intel_uc_is_using_guc(uc))
return;
- __uc_sanitize(i915);
+ __uc_sanitize(uc);
}
-int intel_uc_init_hw(struct drm_i915_private *i915)
+int intel_uc_init_hw(struct intel_uc *uc)
{
- struct intel_guc *guc = &i915->gt.uc.guc;
- struct intel_huc *huc = &i915->gt.uc.huc;
+ struct drm_i915_private *i915 = uc_to_gt(uc)->i915;
+ struct intel_guc *guc = &uc->guc;
+ struct intel_huc *huc = &uc->huc;
int ret, attempts;
- if (!USES_GUC(i915))
+ if (!intel_uc_is_using_guc(uc))
return 0;
GEM_BUG_ON(!intel_uc_fw_supported(&guc->fw));
@@ -477,11 +477,11 @@ int intel_uc_init_hw(struct drm_i915_private *i915)
* Always reset the GuC just before (re)loading, so
* that the state and timing are fairly predictable
*/
- ret = __intel_uc_reset_hw(i915);
+ ret = __intel_uc_reset_hw(uc);
if (ret)
goto err_out;
- if (USES_HUC(i915)) {
+ if (intel_uc_is_using_huc(uc)) {
ret = intel_huc_fw_upload(huc);
if (ret)
goto err_out;
@@ -505,7 +505,7 @@ int intel_uc_init_hw(struct drm_i915_private *i915)
if (ret)
goto err_log_capture;
- if (USES_HUC(i915)) {
+ if (intel_uc_is_using_huc(uc)) {
ret = intel_huc_auth(huc);
if (ret)
goto err_communication;
@@ -515,7 +515,7 @@ int intel_uc_init_hw(struct drm_i915_private *i915)
if (ret)
goto err_communication;
- if (USES_GUC_SUBMISSION(i915)) {
+ if (intel_uc_is_using_guc_submission(uc)) {
ret = intel_guc_submission_enable(guc);
if (ret)
goto err_communication;
@@ -524,9 +524,9 @@ int intel_uc_init_hw(struct drm_i915_private *i915)
dev_info(i915->drm.dev, "GuC firmware version %u.%u\n",
guc->fw.major_ver_found, guc->fw.minor_ver_found);
dev_info(i915->drm.dev, "GuC submission %s\n",
- enableddisabled(USES_GUC_SUBMISSION(i915)));
+ enableddisabled(intel_uc_is_using_guc_submission(uc)));
dev_info(i915->drm.dev, "HuC %s\n",
- enableddisabled(USES_HUC(i915)));
+ enableddisabled(intel_uc_is_using_huc(uc)));
return 0;
@@ -538,7 +538,7 @@ int intel_uc_init_hw(struct drm_i915_private *i915)
err_log_capture:
guc_capture_load_err_log(guc);
err_out:
- __uc_sanitize(i915);
+ __uc_sanitize(uc);
/*
* Note that there is no fallback as either user explicitly asked for
@@ -551,42 +551,42 @@ int intel_uc_init_hw(struct drm_i915_private *i915)
return ret;
}
-void intel_uc_fini_hw(struct drm_i915_private *i915)
+void intel_uc_fini_hw(struct intel_uc *uc)
{
- struct intel_guc *guc = &i915->gt.uc.guc;
+ struct intel_guc *guc = &uc->guc;
if (!intel_guc_is_loaded(guc))
return;
GEM_BUG_ON(!intel_uc_fw_supported(&guc->fw));
- if (USES_GUC_SUBMISSION(i915))
+ if (intel_uc_is_using_guc_submission(uc))
intel_guc_submission_disable(guc);
guc_disable_communication(guc);
- __uc_sanitize(i915);
+ __uc_sanitize(uc);
}
/**
* intel_uc_reset_prepare - Prepare for reset
- * @i915: device private
+ * @uc: the intel_uc structure
*
* Preparing for full gpu reset.
*/
-void intel_uc_reset_prepare(struct drm_i915_private *i915)
+void intel_uc_reset_prepare(struct intel_uc *uc)
{
- struct intel_guc *guc = &i915->gt.uc.guc;
+ struct intel_guc *guc = &uc->guc;
if (!intel_guc_is_loaded(guc))
return;
guc_stop_communication(guc);
- __uc_sanitize(i915);
+ __uc_sanitize(uc);
}
-void intel_uc_runtime_suspend(struct drm_i915_private *i915)
+void intel_uc_runtime_suspend(struct intel_uc *uc)
{
- struct intel_guc *guc = &i915->gt.uc.guc;
+ struct intel_guc *guc = &uc->guc;
int err;
if (!intel_guc_is_loaded(guc))
@@ -599,21 +599,21 @@ void intel_uc_runtime_suspend(struct drm_i915_private *i915)
guc_disable_communication(guc);
}
-void intel_uc_suspend(struct drm_i915_private *i915)
+void intel_uc_suspend(struct intel_uc *uc)
{
- struct intel_guc *guc = &i915->gt.uc.guc;
+ struct intel_guc *guc = &uc->guc;
intel_wakeref_t wakeref;
if (!intel_guc_is_loaded(guc))
return;
- with_intel_runtime_pm(&i915->runtime_pm, wakeref)
- intel_uc_runtime_suspend(i915);
+ with_intel_runtime_pm(&uc_to_gt(uc)->i915->runtime_pm, wakeref)
+ intel_uc_runtime_suspend(uc);
}
-int intel_uc_resume(struct drm_i915_private *i915)
+int intel_uc_resume(struct intel_uc *uc)
{
- struct intel_guc *guc = &i915->gt.uc.guc;
+ struct intel_guc *guc = &uc->guc;
int err;
if (!intel_guc_is_loaded(guc))
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc.h b/drivers/gpu/drm/i915/gt/uc/intel_uc.h
index a2fdc84afff2..fe3362fd7706 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_uc.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_uc.h
@@ -33,34 +33,34 @@ struct intel_uc {
struct intel_huc huc;
};
-void intel_uc_init_early(struct drm_i915_private *dev_priv);
-void intel_uc_cleanup_early(struct drm_i915_private *dev_priv);
-void intel_uc_init_mmio(struct drm_i915_private *dev_priv);
-void intel_uc_fetch_firmwares(struct drm_i915_private *dev_priv);
-void intel_uc_cleanup_firmwares(struct drm_i915_private *dev_priv);
-void intel_uc_sanitize(struct drm_i915_private *dev_priv);
-int intel_uc_init_hw(struct drm_i915_private *dev_priv);
-void intel_uc_fini_hw(struct drm_i915_private *dev_priv);
-int intel_uc_init(struct drm_i915_private *dev_priv);
-void intel_uc_fini(struct drm_i915_private *dev_priv);
-void intel_uc_reset_prepare(struct drm_i915_private *i915);
-void intel_uc_suspend(struct drm_i915_private *i915);
-void intel_uc_runtime_suspend(struct drm_i915_private *i915);
-int intel_uc_resume(struct drm_i915_private *dev_priv);
+void intel_uc_init_early(struct intel_uc *uc);
+void intel_uc_cleanup_early(struct intel_uc *uc);
+void intel_uc_init_mmio(struct intel_uc *uc);
+void intel_uc_fetch_firmwares(struct intel_uc *uc);
+void intel_uc_cleanup_firmwares(struct intel_uc *uc);
+void intel_uc_sanitize(struct intel_uc *uc);
+int intel_uc_init_hw(struct intel_uc *uc);
+void intel_uc_fini_hw(struct intel_uc *uc);
+int intel_uc_init(struct intel_uc *uc);
+void intel_uc_fini(struct intel_uc *uc);
+void intel_uc_reset_prepare(struct intel_uc *uc);
+void intel_uc_suspend(struct intel_uc *uc);
+void intel_uc_runtime_suspend(struct intel_uc *uc);
+int intel_uc_resume(struct intel_uc *uc);
-static inline bool intel_uc_is_using_guc(struct drm_i915_private *i915)
+static inline bool intel_uc_is_using_guc(struct intel_uc *uc)
{
GEM_BUG_ON(i915_modparams.enable_guc < 0);
return i915_modparams.enable_guc > 0;
}
-static inline bool intel_uc_is_using_guc_submission(struct drm_i915_private *i915)
+static inline bool intel_uc_is_using_guc_submission(struct intel_uc *uc)
{
GEM_BUG_ON(i915_modparams.enable_guc < 0);
return i915_modparams.enable_guc & ENABLE_GUC_SUBMISSION;
}
-static inline bool intel_uc_is_using_huc(struct drm_i915_private *i915)
+static inline bool intel_uc_is_using_huc(struct intel_uc *uc)
{
GEM_BUG_ON(i915_modparams.enable_guc < 0);
return i915_modparams.enable_guc & ENABLE_GUC_LOAD_HUC;
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index e7c89d320375..f594e74f097d 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -934,7 +934,7 @@ static int i915_driver_init_early(struct drm_i915_private *dev_priv)
intel_detect_pch(dev_priv);
intel_wopcm_init_early(&dev_priv->wopcm);
- intel_uc_init_early(dev_priv);
+ intel_uc_init_early(&dev_priv->gt.uc);
intel_pm_setup(dev_priv);
intel_init_dpio(dev_priv);
ret = intel_power_domains_init(dev_priv);
@@ -952,7 +952,7 @@ static int i915_driver_init_early(struct drm_i915_private *dev_priv)
return 0;
err_uc:
- intel_uc_cleanup_early(dev_priv);
+ intel_uc_cleanup_early(&dev_priv->gt.uc);
i915_gem_cleanup_early(dev_priv);
err_workqueues:
i915_workqueues_cleanup(dev_priv);
@@ -969,7 +969,7 @@ static void i915_driver_cleanup_early(struct drm_i915_private *dev_priv)
{
intel_irq_fini(dev_priv);
intel_power_domains_cleanup(dev_priv);
- intel_uc_cleanup_early(dev_priv);
+ intel_uc_cleanup_early(&dev_priv->gt.uc);
i915_gem_cleanup_early(dev_priv);
i915_workqueues_cleanup(dev_priv);
i915_engines_cleanup(dev_priv);
@@ -1008,7 +1008,7 @@ static int i915_driver_init_mmio(struct drm_i915_private *dev_priv)
intel_uncore_prune_mmio_domains(&dev_priv->uncore);
- intel_uc_init_mmio(dev_priv);
+ intel_uc_init_mmio(&dev_priv->gt.uc);
ret = intel_engines_init_mmio(dev_priv);
if (ret)
@@ -2933,7 +2933,7 @@ static int intel_runtime_suspend(struct device *kdev)
*/
i915_gem_runtime_suspend(dev_priv);
- intel_uc_runtime_suspend(dev_priv);
+ intel_uc_runtime_suspend(&dev_priv->gt.uc);
intel_runtime_pm_disable_interrupts(dev_priv);
@@ -2958,7 +2958,7 @@ static int intel_runtime_suspend(struct device *kdev)
intel_runtime_pm_enable_interrupts(dev_priv);
- intel_uc_resume(dev_priv);
+ intel_uc_resume(&dev_priv->gt.uc);
intel_gt_init_swizzling(&dev_priv->gt);
i915_gem_restore_fences(dev_priv);
@@ -3056,7 +3056,7 @@ static int intel_runtime_resume(struct device *kdev)
intel_runtime_pm_enable_interrupts(dev_priv);
- intel_uc_resume(dev_priv);
+ intel_uc_resume(&dev_priv->gt.uc);
/*
* No point of rolling back things in case of an error, as the best
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index c4757cbf9a33..99004c8b833f 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2293,9 +2293,9 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
#define HAS_HUC_UCODE(dev_priv) (HAS_GUC(dev_priv))
/* Having a GuC is not the same as using a GuC */
-#define USES_GUC(dev_priv) intel_uc_is_using_guc(dev_priv)
-#define USES_GUC_SUBMISSION(dev_priv) intel_uc_is_using_guc_submission(dev_priv)
-#define USES_HUC(dev_priv) intel_uc_is_using_huc(dev_priv)
+#define USES_GUC(dev_priv) intel_uc_is_using_guc(&(dev_priv)->gt.uc)
+#define USES_GUC_SUBMISSION(dev_priv) intel_uc_is_using_guc_submission(&(dev_priv)->gt.uc)
+#define USES_HUC(dev_priv) intel_uc_is_using_huc(&(dev_priv)->gt.uc)
#define HAS_POOLED_EU(dev_priv) (INTEL_INFO(dev_priv)->has_pooled_eu)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index e6e8e4d5ebb1..b792e85b8c2b 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -1248,7 +1248,7 @@ int i915_gem_init_hw(struct drm_i915_private *i915)
}
/* We can't enable contexts until all firmware is loaded */
- ret = intel_uc_init_hw(i915);
+ ret = intel_uc_init_hw(&i915->gt.uc);
if (ret) {
DRM_ERROR("Enabling uc failed (%d)\n", ret);
goto out;
@@ -1433,7 +1433,7 @@ int i915_gem_init(struct drm_i915_private *dev_priv)
if (ret)
return ret;
- intel_uc_fetch_firmwares(dev_priv);
+ intel_uc_fetch_firmwares(&dev_priv->gt.uc);
ret = intel_wopcm_init(&dev_priv->wopcm);
if (ret)
@@ -1481,7 +1481,7 @@ int i915_gem_init(struct drm_i915_private *dev_priv)
intel_init_gt_powersave(dev_priv);
- ret = intel_uc_init(dev_priv);
+ ret = intel_uc_init(&dev_priv->gt.uc);
if (ret)
goto err_pm;
@@ -1545,9 +1545,9 @@ int i915_gem_init(struct drm_i915_private *dev_priv)
mutex_lock(&dev_priv->drm.struct_mutex);
err_init_hw:
- intel_uc_fini_hw(dev_priv);
+ intel_uc_fini_hw(&dev_priv->gt.uc);
err_uc_init:
- intel_uc_fini(dev_priv);
+ intel_uc_fini(&dev_priv->gt.uc);
err_pm:
if (ret != -EIO) {
intel_cleanup_gt_powersave(dev_priv);
@@ -1564,7 +1564,7 @@ int i915_gem_init(struct drm_i915_private *dev_priv)
mutex_unlock(&dev_priv->drm.struct_mutex);
err_uc_fw:
- intel_uc_cleanup_firmwares(dev_priv);
+ intel_uc_cleanup_firmwares(&dev_priv->gt.uc);
if (ret != -EIO) {
i915_gem_cleanup_userptr(dev_priv);
@@ -1611,8 +1611,8 @@ void i915_gem_fini_hw(struct drm_i915_private *dev_priv)
i915_gem_drain_workqueue(dev_priv);
mutex_lock(&dev_priv->drm.struct_mutex);
- intel_uc_fini_hw(dev_priv);
- intel_uc_fini(dev_priv);
+ intel_uc_fini_hw(&dev_priv->gt.uc);
+ intel_uc_fini(&dev_priv->gt.uc);
mutex_unlock(&dev_priv->drm.struct_mutex);
i915_gem_drain_freed_objects(dev_priv);
@@ -1630,7 +1630,7 @@ void i915_gem_fini(struct drm_i915_private *dev_priv)
intel_cleanup_gt_powersave(dev_priv);
- intel_uc_cleanup_firmwares(dev_priv);
+ intel_uc_cleanup_firmwares(&dev_priv->gt.uc);
i915_gem_cleanup_userptr(dev_priv);
intel_timelines_fini(dev_priv);
--
2.20.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH 10/12] drm/i915/uc: prefer intel_gt over i915 in GuC/HuC paths
2019-07-10 0:54 [PATCH 00/12] GT-fy the uc code Daniele Ceraolo Spurio
` (8 preceding siblings ...)
2019-07-10 0:54 ` [PATCH 09/12] drm/i915/uc: Move intel functions to intel_uc Daniele Ceraolo Spurio
@ 2019-07-10 0:54 ` Daniele Ceraolo Spurio
2019-07-10 18:35 ` Michal Wajdeczko
2019-07-10 0:54 ` [PATCH 11/12] drm/i915/guc: prefer intel_gt in guc interrupt functions Daniele Ceraolo Spurio
` (5 subsequent siblings)
15 siblings, 1 reply; 28+ messages in thread
From: Daniele Ceraolo Spurio @ 2019-07-10 0:54 UTC (permalink / raw)
To: intel-gfx
With our HW interface logic moving from i915 to gt and with GuC and HuC
being part of the gt HW, it makes sense to use the intel_gt structure
instead of i915 as our reference object in GuC/HuC paths.
Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
---
drivers/gpu/drm/i915/gt/intel_gt.h | 10 +++
drivers/gpu/drm/i915/gt/uc/intel_guc.c | 52 ++++++------
drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c | 81 ++++++++++---------
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 43 +++++-----
drivers/gpu/drm/i915/gt/uc/intel_huc.c | 22 ++---
drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c | 4 +-
drivers/gpu/drm/i915/gt/uc/intel_uc.c | 4 +-
drivers/gpu/drm/i915/i915_gem_gtt.c | 8 +-
drivers/gpu/drm/i915/i915_gem_gtt.h | 4 +-
9 files changed, 120 insertions(+), 108 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.h b/drivers/gpu/drm/i915/gt/intel_gt.h
index 880be05a3f4a..e182509d44ba 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt.h
@@ -16,6 +16,16 @@ static inline struct intel_gt *uc_to_gt(struct intel_uc *uc)
return container_of(uc, struct intel_gt, uc);
}
+static inline struct intel_gt *guc_to_gt(struct intel_guc *guc)
+{
+ return container_of(guc, struct intel_gt, uc.guc);
+}
+
+static inline struct intel_gt *huc_to_gt(struct intel_huc *huc)
+{
+ return container_of(huc, struct intel_gt, uc.huc);
+}
+
void intel_gt_init_early(struct intel_gt *gt, struct drm_i915_private *i915);
void intel_gt_init_hw(struct drm_i915_private *i915);
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
index 4173b35bf104..6b56f39072b1 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
@@ -22,6 +22,7 @@
*
*/
+#include "gt/intel_gt.h"
#include "intel_guc.h"
#include "intel_guc_ads.h"
#include "intel_guc_submission.h"
@@ -29,16 +30,16 @@
static void gen8_guc_raise_irq(struct intel_guc *guc)
{
- struct drm_i915_private *dev_priv = guc_to_i915(guc);
+ struct intel_gt *gt = guc_to_gt(guc);
- I915_WRITE(GUC_SEND_INTERRUPT, GUC_SEND_TRIGGER);
+ intel_uncore_write(gt->uncore, GUC_SEND_INTERRUPT, GUC_SEND_TRIGGER);
}
static void gen11_guc_raise_irq(struct intel_guc *guc)
{
- struct drm_i915_private *dev_priv = guc_to_i915(guc);
+ struct intel_gt *gt = guc_to_gt(guc);
- I915_WRITE(GEN11_GUC_HOST_INTERRUPT, 0);
+ intel_uncore_write(gt->uncore, GEN11_GUC_HOST_INTERRUPT, 0);
}
static inline i915_reg_t guc_send_reg(struct intel_guc *guc, u32 i)
@@ -52,11 +53,11 @@ static inline i915_reg_t guc_send_reg(struct intel_guc *guc, u32 i)
void intel_guc_init_send_regs(struct intel_guc *guc)
{
- struct drm_i915_private *dev_priv = guc_to_i915(guc);
+ struct intel_gt *gt = guc_to_gt(guc);
enum forcewake_domains fw_domains = 0;
unsigned int i;
- if (INTEL_GEN(dev_priv) >= 11) {
+ if (INTEL_GEN(gt->i915) >= 11) {
guc->send_regs.base =
i915_mmio_reg_offset(GEN11_SOFT_SCRATCH(0));
guc->send_regs.count = GEN11_SOFT_SCRATCH_COUNT;
@@ -67,7 +68,7 @@ void intel_guc_init_send_regs(struct intel_guc *guc)
}
for (i = 0; i < guc->send_regs.count; i++) {
- fw_domains |= intel_uncore_forcewake_for_reg(&dev_priv->uncore,
+ fw_domains |= intel_uncore_forcewake_for_reg(gt->uncore,
guc_send_reg(guc, i),
FW_REG_READ | FW_REG_WRITE);
}
@@ -127,7 +128,7 @@ static void guc_shared_data_destroy(struct intel_guc *guc)
int intel_guc_init(struct intel_guc *guc)
{
- struct drm_i915_private *dev_priv = guc_to_i915(guc);
+ struct intel_gt *gt = guc_to_gt(guc);
int ret;
ret = intel_uc_fw_init(&guc->fw);
@@ -153,7 +154,7 @@ int intel_guc_init(struct intel_guc *guc)
goto err_ads;
/* We need to notify the guc whenever we change the GGTT */
- i915_ggtt_enable_guc(dev_priv);
+ i915_ggtt_enable_guc(gt->ggtt);
return 0;
@@ -172,9 +173,9 @@ int intel_guc_init(struct intel_guc *guc)
void intel_guc_fini(struct intel_guc *guc)
{
- struct drm_i915_private *dev_priv = guc_to_i915(guc);
+ struct intel_gt *gt = guc_to_gt(guc);
- i915_ggtt_disable_guc(dev_priv);
+ i915_ggtt_disable_guc(gt->ggtt);
intel_guc_ct_fini(&guc->ct);
@@ -282,7 +283,7 @@ static u32 guc_ctl_ads_flags(struct intel_guc *guc)
*/
void intel_guc_init_params(struct intel_guc *guc)
{
- struct drm_i915_private *dev_priv = guc_to_i915(guc);
+ struct intel_uncore *uncore = guc_to_gt(guc)->uncore;
u32 params[GUC_CTL_MAX_DWORDS];
int i;
@@ -302,14 +303,14 @@ void intel_guc_init_params(struct intel_guc *guc)
* they are power context saved so it's ok to release forcewake
* when we are done here and take it again at xfer time.
*/
- intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_BLITTER);
+ intel_uncore_forcewake_get(uncore, FORCEWAKE_BLITTER);
- I915_WRITE(SOFT_SCRATCH(0), 0);
+ intel_uncore_write(uncore, SOFT_SCRATCH(0), 0);
for (i = 0; i < GUC_CTL_MAX_DWORDS; i++)
- I915_WRITE(SOFT_SCRATCH(1 + i), params[i]);
+ intel_uncore_write(uncore, SOFT_SCRATCH(1 + i), params[i]);
- intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_BLITTER);
+ intel_uncore_forcewake_put(uncore, FORCEWAKE_BLITTER);
}
int intel_guc_send_nop(struct intel_guc *guc, const u32 *action, u32 len,
@@ -330,8 +331,7 @@ void intel_guc_to_host_event_handler_nop(struct intel_guc *guc)
int intel_guc_send_mmio(struct intel_guc *guc, const u32 *action, u32 len,
u32 *response_buf, u32 response_buf_size)
{
- struct drm_i915_private *dev_priv = guc_to_i915(guc);
- struct intel_uncore *uncore = &dev_priv->uncore;
+ struct intel_uncore *uncore = guc_to_gt(guc)->uncore;
u32 status;
int i;
int ret;
@@ -380,7 +380,8 @@ int intel_guc_send_mmio(struct intel_guc *guc, const u32 *action, u32 len,
int count = min(response_buf_size, guc->send_regs.count - 1);
for (i = 0; i < count; i++)
- response_buf[i] = I915_READ(guc_send_reg(guc, i + 1));
+ response_buf[i] = intel_uncore_read(uncore,
+ guc_send_reg(guc, i + 1));
}
/* Use data from the GuC response as our return value */
@@ -454,7 +455,7 @@ int intel_guc_auth_huc(struct intel_guc *guc, u32 rsa_offset)
*/
int intel_guc_suspend(struct intel_guc *guc)
{
- struct drm_i915_private *dev_priv = guc_to_i915(guc);
+ struct intel_uncore *uncore = guc_to_gt(guc)->uncore;
int ret;
u32 status;
u32 action[] = {
@@ -472,13 +473,14 @@ int intel_guc_suspend(struct intel_guc *guc)
* in progress so we need to take care of that ourselves as well.
*/
- I915_WRITE(SOFT_SCRATCH(14), INTEL_GUC_SLEEP_STATE_INVALID_MASK);
+ intel_uncore_write(uncore, SOFT_SCRATCH(14),
+ INTEL_GUC_SLEEP_STATE_INVALID_MASK);
ret = intel_guc_send(guc, action, ARRAY_SIZE(action));
if (ret)
return ret;
- ret = __intel_wait_for_register(&dev_priv->uncore, SOFT_SCRATCH(14),
+ ret = __intel_wait_for_register(uncore, SOFT_SCRATCH(14),
INTEL_GUC_SLEEP_STATE_INVALID_MASK,
0, 0, 10, &status);
if (ret)
@@ -574,17 +576,17 @@ int intel_guc_resume(struct intel_guc *guc)
*/
struct i915_vma *intel_guc_allocate_vma(struct intel_guc *guc, u32 size)
{
- struct drm_i915_private *dev_priv = guc_to_i915(guc);
+ struct intel_gt *gt = guc_to_gt(guc);
struct drm_i915_gem_object *obj;
struct i915_vma *vma;
u64 flags;
int ret;
- obj = i915_gem_object_create_shmem(dev_priv, size);
+ obj = i915_gem_object_create_shmem(gt->i915, size);
if (IS_ERR(obj))
return ERR_CAST(obj);
- vma = i915_vma_instance(obj, &dev_priv->ggtt.vm, NULL);
+ vma = i915_vma_instance(obj, >->ggtt->vm, NULL);
if (IS_ERR(vma))
goto err;
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c
index ee95d4960c5c..98305e3fd42c 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c
@@ -27,6 +27,7 @@
* Alex Dai <yu.dai@intel.com>
*/
+#include "gt/intel_gt.h"
#include "intel_guc_fw.h"
#include "i915_drv.h"
@@ -129,35 +130,37 @@ void intel_guc_fw_init_early(struct intel_guc *guc)
static void guc_prepare_xfer(struct intel_guc *guc)
{
- struct drm_i915_private *dev_priv = guc_to_i915(guc);
+ struct intel_gt *gt = guc_to_gt(guc);
+ struct intel_uncore *uncore = gt->uncore;
+ u32 shim_flags = GUC_DISABLE_SRAM_INIT_TO_ZEROES |
+ GUC_ENABLE_READ_CACHE_LOGIC |
+ GUC_ENABLE_MIA_CACHING |
+ GUC_ENABLE_READ_CACHE_FOR_SRAM_DATA |
+ GUC_ENABLE_READ_CACHE_FOR_WOPCM_DATA |
+ GUC_ENABLE_MIA_CLOCK_GATING;
/* Must program this register before loading the ucode with DMA */
- I915_WRITE(GUC_SHIM_CONTROL, GUC_DISABLE_SRAM_INIT_TO_ZEROES |
- GUC_ENABLE_READ_CACHE_LOGIC |
- GUC_ENABLE_MIA_CACHING |
- GUC_ENABLE_READ_CACHE_FOR_SRAM_DATA |
- GUC_ENABLE_READ_CACHE_FOR_WOPCM_DATA |
- GUC_ENABLE_MIA_CLOCK_GATING);
-
- if (IS_GEN9_LP(dev_priv))
- I915_WRITE(GEN9LP_GT_PM_CONFIG, GT_DOORBELL_ENABLE);
+ intel_uncore_write(uncore, GUC_SHIM_CONTROL, shim_flags);
+
+ if (IS_GEN9_LP(gt->i915))
+ intel_uncore_write(uncore, GEN9LP_GT_PM_CONFIG, GT_DOORBELL_ENABLE);
else
- I915_WRITE(GEN9_GT_PM_CONFIG, GT_DOORBELL_ENABLE);
+ intel_uncore_write(uncore, GEN9_GT_PM_CONFIG, GT_DOORBELL_ENABLE);
- if (IS_GEN(dev_priv, 9)) {
+ if (IS_GEN(gt->i915, 9)) {
/* DOP Clock Gating Enable for GuC clocks */
- I915_WRITE(GEN7_MISCCPCTL, (GEN8_DOP_CLOCK_GATE_GUC_ENABLE |
- I915_READ(GEN7_MISCCPCTL)));
+ intel_uncore_rmw(uncore, GEN7_MISCCPCTL,
+ 0, GEN8_DOP_CLOCK_GATE_GUC_ENABLE);
/* allows for 5us (in 10ns units) before GT can go to RC6 */
- I915_WRITE(GUC_ARAT_C6DIS, 0x1FF);
+ intel_uncore_write(uncore, GUC_ARAT_C6DIS, 0x1FF);
}
}
/* Copy RSA signature from the fw image to HW for verification */
static void guc_xfer_rsa(struct intel_guc *guc)
{
- struct drm_i915_private *dev_priv = guc_to_i915(guc);
+ struct intel_uncore *uncore = guc_to_gt(guc)->uncore;
struct intel_uc_fw *fw = &guc->fw;
struct sg_table *pages = fw->obj->mm.pages;
u32 rsa[UOS_RSA_SCRATCH_COUNT];
@@ -167,15 +170,13 @@ static void guc_xfer_rsa(struct intel_guc *guc)
rsa, sizeof(rsa), fw->rsa_offset);
for (i = 0; i < UOS_RSA_SCRATCH_COUNT; i++)
- I915_WRITE(UOS_RSA_SCRATCH(i), rsa[i]);
+ intel_uncore_write(uncore, UOS_RSA_SCRATCH(i), rsa[i]);
}
-static bool guc_xfer_completed(struct intel_guc *guc, u32 *status)
+static bool guc_xfer_completed(struct intel_uncore *uncore, u32 *status)
{
- struct drm_i915_private *dev_priv = guc_to_i915(guc);
-
/* Did we complete the xfer? */
- *status = I915_READ(DMA_CTRL);
+ *status = intel_uncore_read(uncore, DMA_CTRL);
return !(*status & START_DMA);
}
@@ -188,10 +189,9 @@ static bool guc_xfer_completed(struct intel_guc *guc, u32 *status)
* This is used for polling the GuC status in a wait_for()
* loop below.
*/
-static inline bool guc_ready(struct intel_guc *guc, u32 *status)
+static inline bool guc_ready(struct intel_uncore *uncore, u32 *status)
{
- struct drm_i915_private *dev_priv = guc_to_i915(guc);
- u32 val = I915_READ(GUC_STATUS);
+ u32 val = intel_uncore_read(uncore, GUC_STATUS);
u32 uk_val = val & GS_UKERNEL_MASK;
*status = val;
@@ -199,9 +199,8 @@ static inline bool guc_ready(struct intel_guc *guc, u32 *status)
((val & GS_MIA_CORE_STATE) && (uk_val == GS_UKERNEL_LAPIC_DONE));
}
-static int guc_wait_ucode(struct intel_guc *guc)
+static int guc_wait_ucode(struct intel_uncore *uncore)
{
- struct drm_i915_private *i915 = guc_to_i915(guc);
u32 status;
int ret;
@@ -213,7 +212,7 @@ static int guc_wait_ucode(struct intel_guc *guc)
* (Higher levels of the driver may decide to reset the GuC and
* attempt the ucode load again if this happens.)
*/
- ret = wait_for(guc_ready(guc, &status), 100);
+ ret = wait_for(guc_ready(uncore, &status), 100);
DRM_DEBUG_DRIVER("GuC status %#x\n", status);
if ((status & GS_BOOTROM_MASK) == GS_BOOTROM_RSA_FAILED) {
@@ -223,11 +222,11 @@ static int guc_wait_ucode(struct intel_guc *guc)
if ((status & GS_UKERNEL_MASK) == GS_UKERNEL_EXCEPTION) {
DRM_ERROR("GuC firmware exception. EIP: %#x\n",
- intel_uncore_read(&i915->uncore, SOFT_SCRATCH(13)));
+ intel_uncore_read(uncore, SOFT_SCRATCH(13)));
ret = -ENXIO;
}
- if (ret == 0 && !guc_xfer_completed(guc, &status)) {
+ if (ret == 0 && !guc_xfer_completed(uncore, &status)) {
DRM_ERROR("GuC is ready, but the xfer %08x is incomplete\n",
status);
ret = -ENXIO;
@@ -245,7 +244,7 @@ static int guc_wait_ucode(struct intel_guc *guc)
*/
static int guc_xfer_ucode(struct intel_guc *guc)
{
- struct drm_i915_private *dev_priv = guc_to_i915(guc);
+ struct intel_uncore *uncore = guc_to_gt(guc)->uncore;
struct intel_uc_fw *guc_fw = &guc->fw;
unsigned long offset;
@@ -253,24 +252,26 @@ static int guc_xfer_ucode(struct intel_guc *guc)
* The header plus uCode will be copied to WOPCM via DMA, excluding any
* other components
*/
- I915_WRITE(DMA_COPY_SIZE, guc_fw->header_size + guc_fw->ucode_size);
+ intel_uncore_write(uncore, DMA_COPY_SIZE,
+ guc_fw->header_size + guc_fw->ucode_size);
/* Set the source address for the new blob */
offset = intel_uc_fw_ggtt_offset(guc_fw) + guc_fw->header_offset;
- I915_WRITE(DMA_ADDR_0_LOW, lower_32_bits(offset));
- I915_WRITE(DMA_ADDR_0_HIGH, upper_32_bits(offset) & 0xFFFF);
+ intel_uncore_write(uncore, DMA_ADDR_0_LOW, lower_32_bits(offset));
+ intel_uncore_write(uncore, DMA_ADDR_0_HIGH, upper_32_bits(offset) & 0xFFFF);
/*
* Set the DMA destination. Current uCode expects the code to be
* loaded at 8k; locations below this are used for the stack.
*/
- I915_WRITE(DMA_ADDR_1_LOW, 0x2000);
- I915_WRITE(DMA_ADDR_1_HIGH, DMA_ADDRESS_SPACE_WOPCM);
+ intel_uncore_write(uncore, DMA_ADDR_1_LOW, 0x2000);
+ intel_uncore_write(uncore, DMA_ADDR_1_HIGH, DMA_ADDRESS_SPACE_WOPCM);
/* Finally start the DMA */
- I915_WRITE(DMA_CTRL, _MASKED_BIT_ENABLE(UOS_MOVE | START_DMA));
+ intel_uncore_write(uncore, DMA_CTRL,
+ _MASKED_BIT_ENABLE(UOS_MOVE | START_DMA));
- return guc_wait_ucode(guc);
+ return guc_wait_ucode(uncore);
}
/*
* Load the GuC firmware blob into the MinuteIA.
@@ -278,12 +279,12 @@ static int guc_xfer_ucode(struct intel_guc *guc)
static int guc_fw_xfer(struct intel_uc_fw *guc_fw)
{
struct intel_guc *guc = container_of(guc_fw, struct intel_guc, fw);
- struct drm_i915_private *dev_priv = guc_to_i915(guc);
+ struct intel_uncore *uncore = guc_to_gt(guc)->uncore;
int ret;
GEM_BUG_ON(guc_fw->type != INTEL_UC_FW_TYPE_GUC);
- intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_ALL);
+ intel_uncore_forcewake_get(uncore, FORCEWAKE_ALL);
guc_prepare_xfer(guc);
@@ -296,7 +297,7 @@ static int guc_fw_xfer(struct intel_uc_fw *guc_fw)
ret = guc_xfer_ucode(guc);
- intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL);
+ intel_uncore_forcewake_put(uncore, FORCEWAKE_ALL);
return ret;
}
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index 23906228b9b4..9ec6eb71f37d 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -28,6 +28,7 @@
#include "gt/intel_context.h"
#include "gt/intel_engine_pm.h"
+#include "gt/intel_gt.h"
#include "gt/intel_lrc_reg.h"
#include "intel_guc_submission.h"
@@ -201,10 +202,10 @@ static struct guc_doorbell_info *__get_doorbell(struct intel_guc_client *client)
static bool __doorbell_valid(struct intel_guc *guc, u16 db_id)
{
- struct drm_i915_private *dev_priv = guc_to_i915(guc);
+ struct intel_uncore *uncore = guc_to_gt(guc)->uncore;
GEM_BUG_ON(db_id >= GUC_NUM_DOORBELLS);
- return I915_READ(GEN8_DRBREGL(db_id)) & GEN8_DRB_VALID;
+ return intel_uncore_read(uncore, GEN8_DRBREGL(db_id)) & GEN8_DRB_VALID;
}
static void __init_doorbell(struct intel_guc_client *client)
@@ -1003,9 +1004,10 @@ void intel_guc_submission_fini(struct intel_guc *guc)
guc_stage_desc_pool_destroy(guc);
}
-static void guc_interrupts_capture(struct drm_i915_private *dev_priv)
+static void guc_interrupts_capture(struct intel_gt *gt)
{
- struct intel_rps *rps = &dev_priv->gt_pm.rps;
+ struct intel_rps *rps = >->i915->gt_pm.rps;
+ struct intel_uncore *uncore = gt->uncore;
struct intel_engine_cs *engine;
enum intel_engine_id id;
int irqs;
@@ -1014,16 +1016,16 @@ static void guc_interrupts_capture(struct drm_i915_private *dev_priv)
* to GuC
*/
irqs = _MASKED_BIT_ENABLE(GFX_INTERRUPT_STEERING);
- for_each_engine(engine, dev_priv, id)
+ for_each_engine(engine, gt->i915, id)
ENGINE_WRITE(engine, RING_MODE_GEN7, irqs);
/* route USER_INTERRUPT to Host, all others are sent to GuC. */
irqs = GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT |
GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT;
/* These three registers have the same bit definitions */
- I915_WRITE(GUC_BCS_RCS_IER, ~irqs);
- I915_WRITE(GUC_VCS2_VCS1_IER, ~irqs);
- I915_WRITE(GUC_WD_VECS_IER, ~irqs);
+ intel_uncore_write(uncore, GUC_BCS_RCS_IER, ~irqs);
+ intel_uncore_write(uncore, GUC_VCS2_VCS1_IER, ~irqs);
+ intel_uncore_write(uncore, GUC_WD_VECS_IER, ~irqs);
/*
* The REDIRECT_TO_GUC bit of the PMINTRMSK register directs all
@@ -1048,9 +1050,10 @@ static void guc_interrupts_capture(struct drm_i915_private *dev_priv)
rps->pm_intrmsk_mbz &= ~GEN8_PMINTR_DISABLE_REDIRECT_TO_GUC;
}
-static void guc_interrupts_release(struct drm_i915_private *dev_priv)
+static void guc_interrupts_release(struct intel_gt *gt)
{
- struct intel_rps *rps = &dev_priv->gt_pm.rps;
+ struct intel_rps *rps = >->i915->gt_pm.rps;
+ struct intel_uncore *uncore = gt->uncore;
struct intel_engine_cs *engine;
enum intel_engine_id id;
int irqs;
@@ -1061,13 +1064,13 @@ static void guc_interrupts_release(struct drm_i915_private *dev_priv)
*/
irqs = _MASKED_FIELD(GFX_FORWARD_VBLANK_MASK, GFX_FORWARD_VBLANK_NEVER);
irqs |= _MASKED_BIT_DISABLE(GFX_INTERRUPT_STEERING);
- for_each_engine(engine, dev_priv, id)
+ for_each_engine(engine, gt->i915, id)
ENGINE_WRITE(engine, RING_MODE_GEN7, irqs);
/* route all GT interrupts to the host */
- I915_WRITE(GUC_BCS_RCS_IER, 0);
- I915_WRITE(GUC_VCS2_VCS1_IER, 0);
- I915_WRITE(GUC_WD_VECS_IER, 0);
+ intel_uncore_write(uncore, GUC_BCS_RCS_IER, 0);
+ intel_uncore_write(uncore, GUC_VCS2_VCS1_IER, 0);
+ intel_uncore_write(uncore, GUC_WD_VECS_IER, 0);
rps->pm_intrmsk_mbz |= GEN8_PMINTR_DISABLE_REDIRECT_TO_GUC;
rps->pm_intrmsk_mbz &= ~ARAT_EXPIRED_INTRMSK;
@@ -1117,7 +1120,7 @@ static void guc_set_default_submission(struct intel_engine_cs *engine)
int intel_guc_submission_enable(struct intel_guc *guc)
{
- struct drm_i915_private *dev_priv = guc_to_i915(guc);
+ struct intel_gt *gt = guc_to_gt(guc);
struct intel_engine_cs *engine;
enum intel_engine_id id;
int err;
@@ -1142,9 +1145,9 @@ int intel_guc_submission_enable(struct intel_guc *guc)
return err;
/* Take over from manual control of ELSP (execlists) */
- guc_interrupts_capture(dev_priv);
+ guc_interrupts_capture(gt);
- for_each_engine(engine, dev_priv, id) {
+ for_each_engine(engine, gt->i915, id) {
engine->set_default_submission = guc_set_default_submission;
engine->set_default_submission(engine);
}
@@ -1154,11 +1157,11 @@ int intel_guc_submission_enable(struct intel_guc *guc)
void intel_guc_submission_disable(struct intel_guc *guc)
{
- struct drm_i915_private *dev_priv = guc_to_i915(guc);
+ struct intel_gt *gt = guc_to_gt(guc);
- GEM_BUG_ON(dev_priv->gt.awake); /* GT should be parked first */
+ GEM_BUG_ON(gt->awake); /* GT should be parked first */
- guc_interrupts_release(dev_priv);
+ guc_interrupts_release(gt);
guc_clients_disable(guc);
}
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_huc.c b/drivers/gpu/drm/i915/gt/uc/intel_huc.c
index 581c9c3d4fc0..99f0fa2e8ff5 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_huc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_huc.c
@@ -24,6 +24,7 @@
#include <linux/types.h>
+#include "gt/intel_gt.h"
#include "intel_huc.h"
#include "i915_drv.h"
@@ -46,8 +47,8 @@ void intel_huc_init_early(struct intel_huc *huc)
static int intel_huc_rsa_data_create(struct intel_huc *huc)
{
- struct drm_i915_private *i915 = huc_to_i915(huc);
- struct intel_guc *guc = &i915->gt.uc.guc;
+ struct intel_gt *gt = huc_to_gt(huc);
+ struct intel_guc *guc = >->uc.guc;
struct i915_vma *vma;
void *vaddr;
@@ -112,8 +113,8 @@ void intel_huc_fini(struct intel_huc *huc)
*/
int intel_huc_auth(struct intel_huc *huc)
{
- struct drm_i915_private *i915 = huc_to_i915(huc);
- struct intel_guc *guc = &i915->gt.uc.guc;
+ struct intel_gt *gt = huc_to_gt(huc);
+ struct intel_guc *guc = >->uc.guc;
int ret;
if (huc->fw.load_status != INTEL_UC_FIRMWARE_SUCCESS)
@@ -127,7 +128,7 @@ int intel_huc_auth(struct intel_huc *huc)
}
/* Check authentication status, it should be done by now */
- ret = __intel_wait_for_register(&i915->uncore,
+ ret = __intel_wait_for_register(gt->uncore,
huc->status.reg,
huc->status.mask,
huc->status.value,
@@ -159,16 +160,15 @@ int intel_huc_auth(struct intel_huc *huc)
*/
int intel_huc_check_status(struct intel_huc *huc)
{
- struct drm_i915_private *dev_priv = huc_to_i915(huc);
+ struct intel_gt *gt = huc_to_gt(huc);
intel_wakeref_t wakeref;
bool status = false;
- if (!HAS_HUC(dev_priv))
+ if (!intel_uc_is_using_huc(>->uc))
return -ENODEV;
- with_intel_runtime_pm(&dev_priv->runtime_pm, wakeref)
- status = (I915_READ(huc->status.reg) & huc->status.mask) ==
- huc->status.value;
+ with_intel_runtime_pm(>->i915->runtime_pm, wakeref)
+ status = intel_uncore_read(gt->uncore, huc->status.reg);
- return status;
+ return (status & huc->status.mask) == huc->status.value;
}
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c b/drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c
index 06e726ba9863..becfd34a26c1 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c
@@ -4,6 +4,7 @@
* Copyright © 2014-2018 Intel Corporation
*/
+#include "gt/intel_gt.h"
#include "intel_huc_fw.h"
#include "i915_drv.h"
@@ -139,8 +140,7 @@ static void huc_xfer_rsa(struct intel_huc *huc)
static int huc_xfer_ucode(struct intel_huc *huc)
{
struct intel_uc_fw *huc_fw = &huc->fw;
- struct drm_i915_private *dev_priv = huc_to_i915(huc);
- struct intel_uncore *uncore = &dev_priv->uncore;
+ struct intel_uncore *uncore = huc_to_gt(huc)->uncore;
unsigned long offset = 0;
u32 size;
int ret;
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc.c b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
index 2062e7ff05e8..3fead2dc9d32 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_uc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
@@ -224,7 +224,7 @@ static void guc_free_load_err_log(struct intel_guc *guc)
*/
static void guc_clear_mmio_msg(struct intel_guc *guc)
{
- intel_uncore_write(&guc_to_i915(guc)->uncore, SOFT_SCRATCH(15), 0);
+ intel_uncore_write(guc_to_gt(guc)->uncore, SOFT_SCRATCH(15), 0);
}
static void guc_get_mmio_msg(struct intel_guc *guc)
@@ -233,7 +233,7 @@ static void guc_get_mmio_msg(struct intel_guc *guc)
spin_lock_irq(&guc->irq_lock);
- val = intel_uncore_read(&guc_to_i915(guc)->uncore, SOFT_SCRATCH(15));
+ val = intel_uncore_read(guc_to_gt(guc)->uncore, SOFT_SCRATCH(15));
guc->mmio_msg |= val & guc->msg_enabled_mask;
/*
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 236c964dd761..4d694bff08ce 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -3395,10 +3395,8 @@ int i915_ggtt_enable_hw(struct drm_i915_private *dev_priv)
return 0;
}
-void i915_ggtt_enable_guc(struct drm_i915_private *i915)
+void i915_ggtt_enable_guc(struct i915_ggtt *ggtt)
{
- struct i915_ggtt *ggtt = &i915->ggtt;
-
GEM_BUG_ON(ggtt->invalidate != gen6_ggtt_invalidate);
ggtt->invalidate = guc_ggtt_invalidate;
@@ -3406,10 +3404,8 @@ void i915_ggtt_enable_guc(struct drm_i915_private *i915)
ggtt->invalidate(ggtt);
}
-void i915_ggtt_disable_guc(struct drm_i915_private *i915)
+void i915_ggtt_disable_guc(struct i915_ggtt *ggtt)
{
- struct i915_ggtt *ggtt = &i915->ggtt;
-
/* XXX Temporary pardon for error unload */
if (ggtt->invalidate == gen6_ggtt_invalidate)
return;
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.h b/drivers/gpu/drm/i915/i915_gem_gtt.h
index 57a68ef4eda7..666cd505c99b 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.h
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.h
@@ -614,8 +614,8 @@ i915_vm_to_ppgtt(struct i915_address_space *vm)
int i915_ggtt_probe_hw(struct drm_i915_private *dev_priv);
int i915_ggtt_init_hw(struct drm_i915_private *dev_priv);
int i915_ggtt_enable_hw(struct drm_i915_private *dev_priv);
-void i915_ggtt_enable_guc(struct drm_i915_private *i915);
-void i915_ggtt_disable_guc(struct drm_i915_private *i915);
+void i915_ggtt_enable_guc(struct i915_ggtt *ggtt);
+void i915_ggtt_disable_guc(struct i915_ggtt *ggtt);
int i915_init_ggtt(struct drm_i915_private *dev_priv);
void i915_ggtt_cleanup_hw(struct drm_i915_private *dev_priv);
--
2.20.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH 11/12] drm/i915/guc: prefer intel_gt in guc interrupt functions
2019-07-10 0:54 [PATCH 00/12] GT-fy the uc code Daniele Ceraolo Spurio
` (9 preceding siblings ...)
2019-07-10 0:54 ` [PATCH 10/12] drm/i915/uc: prefer intel_gt over i915 in GuC/HuC paths Daniele Ceraolo Spurio
@ 2019-07-10 0:54 ` Daniele Ceraolo Spurio
2019-07-10 0:54 ` [PATCH 12/12] drm/i915/uc: kill <g,h>uc_to_i915 Daniele Ceraolo Spurio
` (4 subsequent siblings)
15 siblings, 0 replies; 28+ messages in thread
From: Daniele Ceraolo Spurio @ 2019-07-10 0:54 UTC (permalink / raw)
To: intel-gfx
We can get rid of a few more guc_to_i915 and start compartmentalizing
interrupt management a bit more. We should be able to move more code in
the future once the gt_pm code is also moved across to gt.
Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
---
drivers/gpu/drm/i915/gt/intel_gt_types.h | 2 +
drivers/gpu/drm/i915/i915_drv.h | 1 -
drivers/gpu/drm/i915/i915_irq.c | 73 +++++++++++++-----------
3 files changed, 42 insertions(+), 34 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_types.h b/drivers/gpu/drm/i915/gt/intel_gt_types.h
index b711252ff427..735dcf7a445c 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h
@@ -62,6 +62,8 @@ struct intel_gt {
u32 pm_imr;
u32 pm_ier;
+
+ u32 pm_guc_events;
};
enum intel_gt_scratch_field {
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 99004c8b833f..2ace1ad173ad 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1399,7 +1399,6 @@ struct drm_i915_private {
};
u32 gt_irq_mask;
u32 pm_rps_events;
- u32 pm_guc_events;
u32 pipestat_irq_mask[I915_MAX_PIPES];
struct i915_hotplug hotplug;
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 78c748cb9df8..91f8c81028c3 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -42,6 +42,8 @@
#include "display/intel_lpe_audio.h"
#include "display/intel_psr.h"
+#include "gt/intel_gt.h"
+
#include "i915_drv.h"
#include "i915_irq.h"
#include "i915_trace.h"
@@ -601,85 +603,90 @@ void gen6_disable_rps_interrupts(struct drm_i915_private *dev_priv)
void gen9_reset_guc_interrupts(struct intel_guc *guc)
{
- struct drm_i915_private *dev_priv = guc_to_i915(guc);
+ struct intel_gt *gt = guc_to_gt(guc);
+ struct drm_i915_private *i915 = gt->i915;
- assert_rpm_wakelock_held(&dev_priv->runtime_pm);
+ assert_rpm_wakelock_held(&i915->runtime_pm);
- spin_lock_irq(&dev_priv->irq_lock);
- gen6_reset_pm_iir(dev_priv, dev_priv->pm_guc_events);
- spin_unlock_irq(&dev_priv->irq_lock);
+ spin_lock_irq(&i915->irq_lock);
+ gen6_reset_pm_iir(i915, gt->pm_guc_events);
+ spin_unlock_irq(&i915->irq_lock);
}
void gen9_enable_guc_interrupts(struct intel_guc *guc)
{
- struct drm_i915_private *dev_priv = guc_to_i915(guc);
+ struct intel_gt *gt = guc_to_gt(guc);
+ struct drm_i915_private *i915 = gt->i915;
- assert_rpm_wakelock_held(&dev_priv->runtime_pm);
+ assert_rpm_wakelock_held(&i915->runtime_pm);
- spin_lock_irq(&dev_priv->irq_lock);
+ spin_lock_irq(&i915->irq_lock);
if (!guc->interrupts.enabled) {
- WARN_ON_ONCE(I915_READ(gen6_pm_iir(dev_priv)) &
- dev_priv->pm_guc_events);
+ WARN_ON_ONCE(intel_uncore_read(gt->uncore, gen6_pm_iir(i915)) &
+ gt->pm_guc_events);
guc->interrupts.enabled = true;
- gen6_enable_pm_irq(&dev_priv->gt, dev_priv->pm_guc_events);
+ gen6_enable_pm_irq(gt, gt->pm_guc_events);
}
- spin_unlock_irq(&dev_priv->irq_lock);
+ spin_unlock_irq(&i915->irq_lock);
}
void gen9_disable_guc_interrupts(struct intel_guc *guc)
{
- struct drm_i915_private *dev_priv = guc_to_i915(guc);
+ struct intel_gt *gt = guc_to_gt(guc);
+ struct drm_i915_private *i915 = gt->i915;
- assert_rpm_wakelock_held(&dev_priv->runtime_pm);
+ assert_rpm_wakelock_held(&i915->runtime_pm);
- spin_lock_irq(&dev_priv->irq_lock);
+ spin_lock_irq(&i915->irq_lock);
guc->interrupts.enabled = false;
- gen6_disable_pm_irq(&dev_priv->gt, dev_priv->pm_guc_events);
+ gen6_disable_pm_irq(gt, gt->pm_guc_events);
- spin_unlock_irq(&dev_priv->irq_lock);
- intel_synchronize_irq(dev_priv);
+ spin_unlock_irq(&i915->irq_lock);
+ intel_synchronize_irq(i915);
gen9_reset_guc_interrupts(guc);
}
void gen11_reset_guc_interrupts(struct intel_guc *guc)
{
- struct drm_i915_private *i915 = guc_to_i915(guc);
+ struct intel_gt *gt = guc_to_gt(guc);
+ struct drm_i915_private *i915 = gt->i915;
spin_lock_irq(&i915->irq_lock);
- gen11_reset_one_iir(&i915->gt, 0, GEN11_GUC);
+ gen11_reset_one_iir(gt, 0, GEN11_GUC);
spin_unlock_irq(&i915->irq_lock);
}
void gen11_enable_guc_interrupts(struct intel_guc *guc)
{
- struct drm_i915_private *dev_priv = guc_to_i915(guc);
+ struct intel_gt *gt = guc_to_gt(guc);
- spin_lock_irq(&dev_priv->irq_lock);
+ spin_lock_irq(>->i915->irq_lock);
if (!guc->interrupts.enabled) {
u32 events = REG_FIELD_PREP(ENGINE1_MASK, GUC_INTR_GUC2HOST);
- WARN_ON_ONCE(gen11_reset_one_iir(&dev_priv->gt, 0, GEN11_GUC));
- I915_WRITE(GEN11_GUC_SG_INTR_ENABLE, events);
- I915_WRITE(GEN11_GUC_SG_INTR_MASK, ~events);
+ WARN_ON_ONCE(gen11_reset_one_iir(gt, 0, GEN11_GUC));
+ intel_uncore_write(gt->uncore, GEN11_GUC_SG_INTR_ENABLE, events);
+ intel_uncore_write(gt->uncore, GEN11_GUC_SG_INTR_MASK, ~events);
guc->interrupts.enabled = true;
}
- spin_unlock_irq(&dev_priv->irq_lock);
+ spin_unlock_irq(>->i915->irq_lock);
}
void gen11_disable_guc_interrupts(struct intel_guc *guc)
{
- struct drm_i915_private *dev_priv = guc_to_i915(guc);
+ struct intel_gt *gt = guc_to_gt(guc);
+ struct drm_i915_private *i915 = gt->i915;
- spin_lock_irq(&dev_priv->irq_lock);
+ spin_lock_irq(&i915->irq_lock);
guc->interrupts.enabled = false;
- I915_WRITE(GEN11_GUC_SG_INTR_MASK, ~0);
- I915_WRITE(GEN11_GUC_SG_INTR_ENABLE, 0);
+ intel_uncore_write(gt->uncore, GEN11_GUC_SG_INTR_MASK, ~0);
+ intel_uncore_write(gt->uncore, GEN11_GUC_SG_INTR_ENABLE, 0);
- spin_unlock_irq(&dev_priv->irq_lock);
- intel_synchronize_irq(dev_priv);
+ spin_unlock_irq(&i915->irq_lock);
+ intel_synchronize_irq(i915);
gen11_reset_guc_interrupts(guc);
}
@@ -4757,7 +4764,7 @@ void intel_irq_init(struct drm_i915_private *dev_priv)
/* pre-gen11 the guc irqs bits are in the upper 16 bits of the pm reg */
if (HAS_GUC_SCHED(dev_priv) && INTEL_GEN(dev_priv) < 11)
- dev_priv->pm_guc_events = GUC_INTR_GUC2HOST << 16;
+ dev_priv->gt.pm_guc_events = GUC_INTR_GUC2HOST << 16;
/* Let's track the enabled rps events */
if (IS_VALLEYVIEW(dev_priv))
--
2.20.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH 12/12] drm/i915/uc: kill <g,h>uc_to_i915
2019-07-10 0:54 [PATCH 00/12] GT-fy the uc code Daniele Ceraolo Spurio
` (10 preceding siblings ...)
2019-07-10 0:54 ` [PATCH 11/12] drm/i915/guc: prefer intel_gt in guc interrupt functions Daniele Ceraolo Spurio
@ 2019-07-10 0:54 ` Daniele Ceraolo Spurio
2019-07-10 18:37 ` Michal Wajdeczko
2019-07-10 1:12 ` ✗ Fi.CI.CHECKPATCH: warning for GT-fy the uc code Patchwork
` (3 subsequent siblings)
15 siblings, 1 reply; 28+ messages in thread
From: Daniele Ceraolo Spurio @ 2019-07-10 0:54 UTC (permalink / raw)
To: intel-gfx
Get rid of them to avoid more users being added while the guc code
transitions to use gt more than i915.
Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
---
drivers/gpu/drm/i915/gt/uc/intel_guc.c | 8 ++++----
drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c | 3 ++-
drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c | 2 +-
drivers/gpu/drm/i915/gt/uc/intel_guc_log.c | 13 +++++++------
drivers/gpu/drm/i915/gt/uc/intel_huc.c | 2 +-
drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c | 2 +-
drivers/gpu/drm/i915/gt/uc/intel_uc.c | 4 ++--
drivers/gpu/drm/i915/i915_drv.h | 10 ----------
8 files changed, 18 insertions(+), 26 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
index 6b56f39072b1..83f2c197375f 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
@@ -77,7 +77,7 @@ void intel_guc_init_send_regs(struct intel_guc *guc)
void intel_guc_init_early(struct intel_guc *guc)
{
- struct drm_i915_private *i915 = guc_to_i915(guc);
+ struct drm_i915_private *i915 = guc_to_gt(guc)->i915;
intel_guc_fw_init_early(guc);
intel_guc_ct_init_early(&guc->ct);
@@ -204,7 +204,7 @@ static u32 guc_ctl_feature_flags(struct intel_guc *guc)
{
u32 flags = 0;
- if (!USES_GUC_SUBMISSION(guc_to_i915(guc)))
+ if (!intel_uc_is_using_guc_submission(&guc_to_gt(guc)->uc))
flags |= GUC_CTL_DISABLE_SCHEDULER;
return flags;
@@ -214,7 +214,7 @@ static u32 guc_ctl_ctxinfo_flags(struct intel_guc *guc)
{
u32 flags = 0;
- if (USES_GUC_SUBMISSION(guc_to_i915(guc))) {
+ if (intel_uc_is_using_guc_submission(&guc_to_gt(guc)->uc)) {
u32 ctxnum, base;
base = intel_guc_ggtt_offset(guc, guc->stage_desc_pool);
@@ -414,7 +414,7 @@ int intel_guc_to_host_process_recv_msg(struct intel_guc *guc,
int intel_guc_sample_forcewake(struct intel_guc *guc)
{
- struct drm_i915_private *dev_priv = guc_to_i915(guc);
+ struct drm_i915_private *dev_priv = guc_to_gt(guc)->i915;
u32 action[2];
action[0] = INTEL_GUC_ACTION_SAMPLE_FORCEWAKE;
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
index 69859d1e047f..a0da80241f22 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
@@ -22,6 +22,7 @@
*
*/
+#include "gt/intel_gt.h"
#include "intel_guc_ads.h"
#include "intel_uc.h"
#include "i915_drv.h"
@@ -85,7 +86,7 @@ struct __guc_ads_blob {
static void __guc_ads_init(struct intel_guc *guc)
{
- struct drm_i915_private *dev_priv = guc_to_i915(guc);
+ struct drm_i915_private *dev_priv = guc_to_gt(guc)->i915;
struct __guc_ads_blob *blob = guc->ads_blob;
const u32 skipped_size = LRC_PPHWSP_SZ * PAGE_SIZE + LR_HW_CONTEXT_SIZE;
u32 base;
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c
index 98305e3fd42c..3dfa40fdbe99 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c
@@ -76,7 +76,7 @@ MODULE_FIRMWARE(ICL_GUC_FIRMWARE_PATH);
static void guc_fw_select(struct intel_uc_fw *guc_fw)
{
struct intel_guc *guc = container_of(guc_fw, struct intel_guc, fw);
- struct drm_i915_private *i915 = guc_to_i915(guc);
+ struct drm_i915_private *i915 = guc_to_gt(guc)->i915;
GEM_BUG_ON(guc_fw->type != INTEL_UC_FW_TYPE_GUC);
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_log.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_log.c
index 0355724ee997..52f814704d8e 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_log.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_log.c
@@ -24,6 +24,7 @@
#include <linux/debugfs.h>
+#include "gt/intel_gt.h"
#include "intel_guc_log.h"
#include "i915_drv.h"
@@ -215,7 +216,7 @@ static bool guc_check_log_buf_overflow(struct intel_guc_log *log,
log->stats[type].sampled_overflow += 16;
}
- dev_notice_ratelimited(guc_to_i915(log_to_guc(log))->drm.dev,
+ dev_notice_ratelimited(guc_to_gt(log_to_guc(log))->i915->drm.dev,
"GuC log buffer overflow\n");
}
@@ -389,7 +390,7 @@ void intel_guc_log_init_early(struct intel_guc_log *log)
static int guc_log_relay_create(struct intel_guc_log *log)
{
struct intel_guc *guc = log_to_guc(log);
- struct drm_i915_private *dev_priv = guc_to_i915(guc);
+ struct drm_i915_private *dev_priv = guc_to_gt(guc)->i915;
struct rchan *guc_log_relay_chan;
size_t n_subbufs, subbuf_size;
int ret;
@@ -435,7 +436,7 @@ static void guc_log_relay_destroy(struct intel_guc_log *log)
static void guc_log_capture_logs(struct intel_guc_log *log)
{
struct intel_guc *guc = log_to_guc(log);
- struct drm_i915_private *dev_priv = guc_to_i915(guc);
+ struct drm_i915_private *dev_priv = guc_to_gt(guc)->i915;
intel_wakeref_t wakeref;
guc_read_update_log_buffer(log);
@@ -504,7 +505,7 @@ void intel_guc_log_destroy(struct intel_guc_log *log)
int intel_guc_log_set_level(struct intel_guc_log *log, u32 level)
{
struct intel_guc *guc = log_to_guc(log);
- struct drm_i915_private *dev_priv = guc_to_i915(guc);
+ struct drm_i915_private *dev_priv = guc_to_gt(guc)->i915;
intel_wakeref_t wakeref;
int ret = 0;
@@ -621,7 +622,7 @@ int intel_guc_log_relay_open(struct intel_guc_log *log)
void intel_guc_log_relay_flush(struct intel_guc_log *log)
{
struct intel_guc *guc = log_to_guc(log);
- struct drm_i915_private *i915 = guc_to_i915(guc);
+ struct drm_i915_private *i915 = guc_to_gt(guc)->i915;
intel_wakeref_t wakeref;
/*
@@ -640,7 +641,7 @@ void intel_guc_log_relay_flush(struct intel_guc_log *log)
void intel_guc_log_relay_close(struct intel_guc_log *log)
{
struct intel_guc *guc = log_to_guc(log);
- struct drm_i915_private *i915 = guc_to_i915(guc);
+ struct drm_i915_private *i915 = guc_to_gt(guc)->i915;
guc_log_disable_flush_events(log);
intel_synchronize_irq(i915);
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_huc.c b/drivers/gpu/drm/i915/gt/uc/intel_huc.c
index 99f0fa2e8ff5..bc14439173d7 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_huc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_huc.c
@@ -30,7 +30,7 @@
void intel_huc_init_early(struct intel_huc *huc)
{
- struct drm_i915_private *i915 = huc_to_i915(huc);
+ struct drm_i915_private *i915 = huc_to_gt(huc)->i915;
intel_huc_fw_init_early(huc);
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c b/drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c
index becfd34a26c1..543854c42d9d 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c
@@ -70,7 +70,7 @@ MODULE_FIRMWARE(I915_ICL_HUC_UCODE);
static void huc_fw_select(struct intel_uc_fw *huc_fw)
{
struct intel_huc *huc = container_of(huc_fw, struct intel_huc, fw);
- struct drm_i915_private *dev_priv = huc_to_i915(huc);
+ struct drm_i915_private *dev_priv = huc_to_gt(huc)->i915;
GEM_BUG_ON(huc_fw->type != INTEL_UC_FW_TYPE_HUC);
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc.c b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
index 3fead2dc9d32..be0f8deba2cb 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_uc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
@@ -248,7 +248,7 @@ static void guc_get_mmio_msg(struct intel_guc *guc)
static void guc_handle_mmio_msg(struct intel_guc *guc)
{
- struct drm_i915_private *i915 = guc_to_i915(guc);
+ struct drm_i915_private *i915 = guc_to_gt(guc)->i915;
/* we need communication to be enabled to reply to GuC */
GEM_BUG_ON(guc->handler == intel_guc_to_host_event_handler_nop);
@@ -280,7 +280,7 @@ static void guc_disable_interrupts(struct intel_guc *guc)
static int guc_enable_communication(struct intel_guc *guc)
{
- struct drm_i915_private *i915 = guc_to_i915(guc);
+ struct drm_i915_private *i915 = guc_to_gt(guc)->i915;
int ret;
ret = intel_guc_ct_enable(&guc->ct);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 2ace1ad173ad..1dbc4f5c8661 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1901,16 +1901,6 @@ static inline struct drm_i915_private *wopcm_to_i915(struct intel_wopcm *wopcm)
return container_of(wopcm, struct drm_i915_private, wopcm);
}
-static inline struct drm_i915_private *guc_to_i915(struct intel_guc *guc)
-{
- return container_of(guc, struct drm_i915_private, gt.uc.guc);
-}
-
-static inline struct drm_i915_private *huc_to_i915(struct intel_huc *huc)
-{
- return container_of(huc, struct drm_i915_private, gt.uc.huc);
-}
-
/* Simple iterator over all initialised engines */
#define for_each_engine(engine__, dev_priv__, id__) \
for ((id__) = 0; \
--
2.20.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 28+ messages in thread
* ✗ Fi.CI.CHECKPATCH: warning for GT-fy the uc code
2019-07-10 0:54 [PATCH 00/12] GT-fy the uc code Daniele Ceraolo Spurio
` (11 preceding siblings ...)
2019-07-10 0:54 ` [PATCH 12/12] drm/i915/uc: kill <g,h>uc_to_i915 Daniele Ceraolo Spurio
@ 2019-07-10 1:12 ` Patchwork
2019-07-10 1:19 ` ✗ Fi.CI.SPARSE: " Patchwork
` (2 subsequent siblings)
15 siblings, 0 replies; 28+ messages in thread
From: Patchwork @ 2019-07-10 1:12 UTC (permalink / raw)
To: Daniele Ceraolo Spurio; +Cc: intel-gfx
== Series Details ==
Series: GT-fy the uc code
URL : https://patchwork.freedesktop.org/series/63460/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
418baf3690fe drm/i915/guc: Remove preemption support for current fw
caf053260254 drm/i915/guc: simplify guc client
363bd5df02b4 drm/i915/uc: replace uc init/fini misc
07dbb4f939f7 drm/i915/uc: introduce intel_uc_fw_supported
b38761341584 drm/i915/guc: move guc irq functions to intel_guc parameter
7202c0751a1b drm/i915/guc: unify guc irq handling
9a92b2f4550e drm/i915/uc: move GuC and HuC files under gt/uc/
-:79: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#79:
new file mode 100644
total: 0 errors, 1 warnings, 0 checks, 140 lines checked
8b866904cad6 drm/i915/uc: move GuC/HuC inside intel_gt under a new intel_uc
ee62b0fb9e59 drm/i915/uc: Move intel functions to intel_uc
26611015f973 drm/i915/uc: prefer intel_gt over i915 in GuC/HuC paths
a43499aad172 drm/i915/guc: prefer intel_gt in guc interrupt functions
3b20a1de17fc drm/i915/uc: kill <g,h>uc_to_i915
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 28+ messages in thread
* ✗ Fi.CI.SPARSE: warning for GT-fy the uc code
2019-07-10 0:54 [PATCH 00/12] GT-fy the uc code Daniele Ceraolo Spurio
` (12 preceding siblings ...)
2019-07-10 1:12 ` ✗ Fi.CI.CHECKPATCH: warning for GT-fy the uc code Patchwork
@ 2019-07-10 1:19 ` Patchwork
2019-07-10 1:35 ` ✗ Fi.CI.BAT: failure " Patchwork
2019-07-10 13:02 ` [PATCH 00/12] " Chris Wilson
15 siblings, 0 replies; 28+ messages in thread
From: Patchwork @ 2019-07-10 1:19 UTC (permalink / raw)
To: Daniele Ceraolo Spurio; +Cc: intel-gfx
== Series Details ==
Series: GT-fy the uc code
URL : https://patchwork.freedesktop.org/series/63460/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm/i915/guc: Remove preemption support for current fw
-./drivers/gpu/drm/i915/i915_scheduler.h:70:23: warning: expression using sizeof(void)
Commit: drm/i915/guc: simplify guc client
Okay!
Commit: drm/i915/uc: replace uc init/fini misc
Okay!
Commit: drm/i915/uc: introduce intel_uc_fw_supported
Okay!
Commit: drm/i915/guc: move guc irq functions to intel_guc parameter
Okay!
Commit: drm/i915/guc: unify guc irq handling
Okay!
Commit: drm/i915/uc: move GuC and HuC files under gt/uc/
+drivers/gpu/drm/i915/gt/uc/intel_guc.c:380:29: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/gt/uc/intel_guc.c:380:29: warning: expression using sizeof(void)
-drivers/gpu/drm/i915/gt/uc/intel_guc.c:380:29: warning: expression using sizeof(void)
-drivers/gpu/drm/i915/gt/uc/intel_guc.c:380:29: warning: expression using sizeof(void)
+./include/uapi/linux/perf_event.h:147:56: warning: cast truncates bits from constant value (8000000000000000 becomes 0)
+./include/uapi/linux/perf_event.h:147:56: warning: cast truncates bits from constant value (8000000000000000 becomes 0)
+./include/uapi/linux/perf_event.h:147:56: warning: cast truncates bits from constant value (8000000000000000 becomes 0)
Commit: drm/i915/uc: move GuC/HuC inside intel_gt under a new intel_uc
Okay!
Commit: drm/i915/uc: Move intel functions to intel_uc
Okay!
Commit: drm/i915/uc: prefer intel_gt over i915 in GuC/HuC paths
-O:drivers/gpu/drm/i915/gt/uc/intel_guc.c:380:29: warning: expression using sizeof(void)
-O:drivers/gpu/drm/i915/gt/uc/intel_guc.c:380:29: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/gt/uc/intel_guc.c:380:29: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/gt/uc/intel_guc.c:380:29: warning: expression using sizeof(void)
Commit: drm/i915/guc: prefer intel_gt in guc interrupt functions
Okay!
Commit: drm/i915/uc: kill <g,h>uc_to_i915
Okay!
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 28+ messages in thread
* ✗ Fi.CI.BAT: failure for GT-fy the uc code
2019-07-10 0:54 [PATCH 00/12] GT-fy the uc code Daniele Ceraolo Spurio
` (13 preceding siblings ...)
2019-07-10 1:19 ` ✗ Fi.CI.SPARSE: " Patchwork
@ 2019-07-10 1:35 ` Patchwork
2019-07-10 13:02 ` [PATCH 00/12] " Chris Wilson
15 siblings, 0 replies; 28+ messages in thread
From: Patchwork @ 2019-07-10 1:35 UTC (permalink / raw)
To: Daniele Ceraolo Spurio; +Cc: intel-gfx
== Series Details ==
Series: GT-fy the uc code
URL : https://patchwork.freedesktop.org/series/63460/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_6446 -> Patchwork_13594
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_13594 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_13594, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13594/
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_13594:
### IGT changes ###
#### Possible regressions ####
* igt@debugfs_test@read_all_entries:
- fi-kbl-guc: [PASS][1] -> [DMESG-WARN][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6446/fi-kbl-guc/igt@debugfs_test@read_all_entries.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13594/fi-kbl-guc/igt@debugfs_test@read_all_entries.html
- fi-skl-guc: [PASS][3] -> [DMESG-WARN][4]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6446/fi-skl-guc/igt@debugfs_test@read_all_entries.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13594/fi-skl-guc/igt@debugfs_test@read_all_entries.html
- fi-apl-guc: [PASS][5] -> [DMESG-WARN][6]
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6446/fi-apl-guc/igt@debugfs_test@read_all_entries.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13594/fi-apl-guc/igt@debugfs_test@read_all_entries.html
- fi-cfl-guc: [PASS][7] -> [DMESG-WARN][8]
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6446/fi-cfl-guc/igt@debugfs_test@read_all_entries.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13594/fi-cfl-guc/igt@debugfs_test@read_all_entries.html
- fi-icl-guc: [PASS][9] -> [DMESG-WARN][10]
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6446/fi-icl-guc/igt@debugfs_test@read_all_entries.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13594/fi-icl-guc/igt@debugfs_test@read_all_entries.html
* igt@i915_selftest@live_mman:
- fi-bsw-n3050: [PASS][11] -> [INCOMPLETE][12]
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6446/fi-bsw-n3050/igt@i915_selftest@live_mman.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13594/fi-bsw-n3050/igt@i915_selftest@live_mman.html
Known issues
------------
Here are the changes found in Patchwork_13594 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_mmap_gtt@basic-write:
- fi-icl-u3: [PASS][13] -> [DMESG-WARN][14] ([fdo#107724]) +1 similar issue
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6446/fi-icl-u3/igt@gem_mmap_gtt@basic-write.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13594/fi-icl-u3/igt@gem_mmap_gtt@basic-write.html
* igt@i915_selftest@live_contexts:
- fi-skl-iommu: [PASS][15] -> [INCOMPLETE][16] ([fdo#111050])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6446/fi-skl-iommu/igt@i915_selftest@live_contexts.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13594/fi-skl-iommu/igt@i915_selftest@live_contexts.html
* igt@i915_selftest@live_hangcheck:
- fi-icl-u2: [PASS][17] -> [INCOMPLETE][18] ([fdo#107713] / [fdo#108569])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6446/fi-icl-u2/igt@i915_selftest@live_hangcheck.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13594/fi-icl-u2/igt@i915_selftest@live_hangcheck.html
#### Possible fixes ####
* {igt@gem_ctx_switch@legacy-render}:
- fi-cml-u: [INCOMPLETE][19] ([fdo#110566]) -> [PASS][20]
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6446/fi-cml-u/igt@gem_ctx_switch@legacy-render.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13594/fi-cml-u/igt@gem_ctx_switch@legacy-render.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: [FAIL][21] ([fdo#109485]) -> [PASS][22]
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6446/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13594/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569
[fdo#109485]: https://bugs.freedesktop.org/show_bug.cgi?id=109485
[fdo#110566]: https://bugs.freedesktop.org/show_bug.cgi?id=110566
[fdo#111046 ]: https://bugs.freedesktop.org/show_bug.cgi?id=111046
[fdo#111050]: https://bugs.freedesktop.org/show_bug.cgi?id=111050
Participating hosts (51 -> 46)
------------------------------
Additional (2): fi-byt-j1900 fi-snb-2600
Missing (7): fi-kbl-soraka fi-bxt-dsi fi-byt-squawks fi-bsw-cyan fi-icl-y fi-byt-clapper fi-bdw-samus
Build changes
-------------
* Linux: CI_DRM_6446 -> Patchwork_13594
CI_DRM_6446: 835fbe24abe47946fc514871f5cbe334d0be9854 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5092: 2a66ae6626d5583240509f84117d1345a799b75a @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_13594: 3b20a1de17fcc713089d0782207397f98d5113ea @ git://anongit.freedesktop.org/gfx-ci/linux
== Kernel 32bit build ==
Warning: Kernel 32bit buildtest failed:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13594/build_32bit.log
CALL scripts/checksyscalls.sh
CALL scripts/atomic/check-atomics.sh
CHK include/generated/compile.h
Kernel: arch/x86/boot/bzImage is ready (#1)
Building modules, stage 2.
MODPOST 112 modules
ERROR: "__udivdi3" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined!
ERROR: "__divdi3" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined!
scripts/Makefile.modpost:91: recipe for target '__modpost' failed
make[1]: *** [__modpost] Error 1
Makefile:1287: recipe for target 'modules' failed
make: *** [modules] Error 2
== Linux commits ==
3b20a1de17fc drm/i915/uc: kill <g,h>uc_to_i915
a43499aad172 drm/i915/guc: prefer intel_gt in guc interrupt functions
26611015f973 drm/i915/uc: prefer intel_gt over i915 in GuC/HuC paths
ee62b0fb9e59 drm/i915/uc: Move intel functions to intel_uc
8b866904cad6 drm/i915/uc: move GuC/HuC inside intel_gt under a new intel_uc
9a92b2f4550e drm/i915/uc: move GuC and HuC files under gt/uc/
7202c0751a1b drm/i915/guc: unify guc irq handling
b38761341584 drm/i915/guc: move guc irq functions to intel_guc parameter
07dbb4f939f7 drm/i915/uc: introduce intel_uc_fw_supported
363bd5df02b4 drm/i915/uc: replace uc init/fini misc
caf053260254 drm/i915/guc: simplify guc client
418baf3690fe drm/i915/guc: Remove preemption support for current fw
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13594/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH 00/12] GT-fy the uc code
2019-07-10 0:54 [PATCH 00/12] GT-fy the uc code Daniele Ceraolo Spurio
` (14 preceding siblings ...)
2019-07-10 1:35 ` ✗ Fi.CI.BAT: failure " Patchwork
@ 2019-07-10 13:02 ` Chris Wilson
15 siblings, 0 replies; 28+ messages in thread
From: Chris Wilson @ 2019-07-10 13:02 UTC (permalink / raw)
To: Daniele Ceraolo Spurio, intel-gfx
Quoting Daniele Ceraolo Spurio (2019-07-10 01:54:25)
> GuC and HuC are a subunits of the GT HW, so it makes sense for the
> relevant structures to be inside intel_gt. This series introduces a new
> intel_uc structure under intel_gt and moves the GuC/HuC structures in
> there. All the general uc code is then encapsulated, working on intel_uc
> instead of i915.
>
> Note that a bit of ugliness is inroduced with the move because we have a
> lot of layers (i915->gt.uc.guc.fw). Most of these "deep" accesses are
> removed by the later patches in the series, but some of them remain,
> mainly in debugfs functions. Follow up updates to make the code more
> encapsulated should help cleaning up.
Fwiw, this series convinced me that gt/uc is the right way to structure
it. We just need to fixup the log_wq handling and grab a few acks/reviews
from Michal et al.
-Chris
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH 01/12] drm/i915/guc: Remove preemption support for current fw
2019-07-10 0:54 ` [PATCH 01/12] drm/i915/guc: Remove preemption support for current fw Daniele Ceraolo Spurio
@ 2019-07-10 15:45 ` Michał Winiarski
0 siblings, 0 replies; 28+ messages in thread
From: Michał Winiarski @ 2019-07-10 15:45 UTC (permalink / raw)
To: Daniele Ceraolo Spurio; +Cc: intel-gfx
On Tue, Jul 09, 2019 at 05:54:26PM -0700, Daniele Ceraolo Spurio wrote:
> From: Chris Wilson <chris@chris-wilson.co.uk>
>
> Preemption via GuC submission is not being supported with its current
> legacy incarnation. The current FW does support a similar pre-emption
> flow via H2G, but it is class-based instead of being instance-based,
> which doesn't fit well with the i915 tracking. To fix this, the
> firmware is being updated to better support our needs with a new flow,
> so we can safely remove the old code.
>
> v2 (Daniele): resurrect & rebase, reword commit message, remove
> preempt_context as well
>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
> Cc: Matthew Brost <matthew.brost@intel.com>
> Cc: John Harrison <John.C.Harrison@Intel.com>
> Acked-by: Matthew Brost <matthew.brost@intel.com>
Reviewed-by: Michał Winiarski <michal.winiarski@intel.com>
-Michał
> ---
> drivers/gpu/drm/i915/gem/i915_gem_context.c | 17 --
> drivers/gpu/drm/i915/gt/intel_engine_cs.c | 13 --
> drivers/gpu/drm/i915/gt/intel_engine_types.h | 1 -
> drivers/gpu/drm/i915/gt/intel_gt_pm.c | 4 -
> drivers/gpu/drm/i915/i915_debugfs.c | 5 -
> drivers/gpu/drm/i915/i915_drv.h | 2 -
> drivers/gpu/drm/i915/intel_guc.c | 31 ---
> drivers/gpu/drm/i915/intel_guc.h | 9 -
> drivers/gpu/drm/i915/intel_guc_submission.c | 231 +------------------
> drivers/gpu/drm/i915/selftests/intel_guc.c | 31 +--
> 10 files changed, 14 insertions(+), 330 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c b/drivers/gpu/drm/i915/gem/i915_gem_context.c
> index e367dce2a696..078592912d97 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
> @@ -644,18 +644,12 @@ static void init_contexts(struct drm_i915_private *i915)
> init_llist_head(&i915->contexts.free_list);
> }
>
> -static bool needs_preempt_context(struct drm_i915_private *i915)
> -{
> - return USES_GUC_SUBMISSION(i915);
> -}
> -
> int i915_gem_contexts_init(struct drm_i915_private *dev_priv)
> {
> struct i915_gem_context *ctx;
>
> /* Reassure ourselves we are only called once */
> GEM_BUG_ON(dev_priv->kernel_context);
> - GEM_BUG_ON(dev_priv->preempt_context);
>
> init_contexts(dev_priv);
>
> @@ -676,15 +670,6 @@ int i915_gem_contexts_init(struct drm_i915_private *dev_priv)
> GEM_BUG_ON(!atomic_read(&ctx->hw_id_pin_count));
> dev_priv->kernel_context = ctx;
>
> - /* highest priority; preempting task */
> - if (needs_preempt_context(dev_priv)) {
> - ctx = i915_gem_context_create_kernel(dev_priv, INT_MAX);
> - if (!IS_ERR(ctx))
> - dev_priv->preempt_context = ctx;
> - else
> - DRM_ERROR("Failed to create preempt context; disabling preemption\n");
> - }
> -
> DRM_DEBUG_DRIVER("%s context support initialized\n",
> DRIVER_CAPS(dev_priv)->has_logical_contexts ?
> "logical" : "fake");
> @@ -695,8 +680,6 @@ void i915_gem_contexts_fini(struct drm_i915_private *i915)
> {
> lockdep_assert_held(&i915->drm.struct_mutex);
>
> - if (i915->preempt_context)
> - destroy_kernel_context(&i915->preempt_context);
> destroy_kernel_context(&i915->kernel_context);
>
> /* Must free all deferred contexts (via flush_workqueue) first */
> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> index bdf279fa3b2e..76b5c068a26d 100644
> --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> @@ -841,15 +841,6 @@ int intel_engine_init_common(struct intel_engine_cs *engine)
> if (ret)
> return ret;
>
> - /*
> - * Similarly the preempt context must always be available so that
> - * we can interrupt the engine at any time. However, as preemption
> - * is optional, we allow it to fail.
> - */
> - if (i915->preempt_context)
> - pin_context(i915->preempt_context, engine,
> - &engine->preempt_context);
> -
> ret = measure_breadcrumb_dw(engine);
> if (ret < 0)
> goto err_unpin;
> @@ -861,8 +852,6 @@ int intel_engine_init_common(struct intel_engine_cs *engine)
> return 0;
>
> err_unpin:
> - if (engine->preempt_context)
> - intel_context_unpin(engine->preempt_context);
> intel_context_unpin(engine->kernel_context);
> return ret;
> }
> @@ -887,8 +876,6 @@ void intel_engine_cleanup_common(struct intel_engine_cs *engine)
> if (engine->default_state)
> i915_gem_object_put(engine->default_state);
>
> - if (engine->preempt_context)
> - intel_context_unpin(engine->preempt_context);
> intel_context_unpin(engine->kernel_context);
> GEM_BUG_ON(!llist_empty(&engine->barrier_tasks));
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h b/drivers/gpu/drm/i915/gt/intel_engine_types.h
> index 7e056114344e..8be63019d707 100644
> --- a/drivers/gpu/drm/i915/gt/intel_engine_types.h
> +++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h
> @@ -288,7 +288,6 @@ struct intel_engine_cs {
> struct llist_head barrier_tasks;
>
> struct intel_context *kernel_context; /* pinned */
> - struct intel_context *preempt_context; /* pinned; optional */
>
> intel_engine_mask_t saturated; /* submitting semaphores too late? */
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm.c b/drivers/gpu/drm/i915/gt/intel_gt_pm.c
> index 36ba80e6a0b7..da81b3a92d16 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_pm.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_pm.c
> @@ -145,10 +145,6 @@ int intel_gt_resume(struct intel_gt *gt)
> if (ce)
> ce->ops->reset(ce);
>
> - ce = engine->preempt_context;
> - if (ce)
> - ce->ops->reset(ce);
> -
> engine->serial++; /* kernel context lost */
> err = engine->resume(engine);
>
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> index 3e4f58f19362..b4d195677877 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -2010,11 +2010,6 @@ static int i915_guc_info(struct seq_file *m, void *data)
>
> seq_printf(m, "\nGuC execbuf client @ %p:\n", guc->execbuf_client);
> i915_guc_client_info(m, dev_priv, guc->execbuf_client);
> - if (guc->preempt_client) {
> - seq_printf(m, "\nGuC preempt client @ %p:\n",
> - guc->preempt_client);
> - i915_guc_client_info(m, dev_priv, guc->preempt_client);
> - }
>
> /* Add more as required ... */
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index f9878cbef4d9..76116e44b7e1 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1378,8 +1378,6 @@ struct drm_i915_private {
> struct intel_engine_cs *engine[I915_NUM_ENGINES];
> /* Context used internally to idle the GPU and setup initial state */
> struct i915_gem_context *kernel_context;
> - /* Context only to be used for injecting preemption commands */
> - struct i915_gem_context *preempt_context;
> struct intel_engine_cs *engine_class[MAX_ENGINE_CLASS + 1]
> [MAX_ENGINE_INSTANCE + 1];
>
> diff --git a/drivers/gpu/drm/i915/intel_guc.c b/drivers/gpu/drm/i915/intel_guc.c
> index c40a6efdd33a..501b74f44374 100644
> --- a/drivers/gpu/drm/i915/intel_guc.c
> +++ b/drivers/gpu/drm/i915/intel_guc.c
> @@ -101,8 +101,6 @@ void intel_guc_init_early(struct intel_guc *guc)
>
> static int guc_init_wq(struct intel_guc *guc)
> {
> - struct drm_i915_private *dev_priv = guc_to_i915(guc);
> -
> /*
> * GuC log buffer flush work item has to do register access to
> * send the ack to GuC and this work item, if not synced before
> @@ -122,31 +120,6 @@ static int guc_init_wq(struct intel_guc *guc)
> return -ENOMEM;
> }
>
> - /*
> - * Even though both sending GuC action, and adding a new workitem to
> - * GuC workqueue are serialized (each with its own locking), since
> - * we're using mutliple engines, it's possible that we're going to
> - * issue a preempt request with two (or more - each for different
> - * engine) workitems in GuC queue. In this situation, GuC may submit
> - * all of them, which will make us very confused.
> - * Our preemption contexts may even already be complete - before we
> - * even had the chance to sent the preempt action to GuC!. Rather
> - * than introducing yet another lock, we can just use ordered workqueue
> - * to make sure we're always sending a single preemption request with a
> - * single workitem.
> - */
> - if (HAS_LOGICAL_RING_PREEMPTION(dev_priv) &&
> - USES_GUC_SUBMISSION(dev_priv)) {
> - guc->preempt_wq = alloc_ordered_workqueue("i915-guc_preempt",
> - WQ_HIGHPRI);
> - if (!guc->preempt_wq) {
> - destroy_workqueue(guc->log.relay.flush_wq);
> - DRM_ERROR("Couldn't allocate workqueue for GuC "
> - "preemption\n");
> - return -ENOMEM;
> - }
> - }
> -
> return 0;
> }
>
> @@ -154,10 +127,6 @@ static void guc_fini_wq(struct intel_guc *guc)
> {
> struct workqueue_struct *wq;
>
> - wq = fetch_and_zero(&guc->preempt_wq);
> - if (wq)
> - destroy_workqueue(wq);
> -
> wq = fetch_and_zero(&guc->log.relay.flush_wq);
> if (wq)
> destroy_workqueue(wq);
> diff --git a/drivers/gpu/drm/i915/intel_guc.h b/drivers/gpu/drm/i915/intel_guc.h
> index d91c96679dbb..ec1038c1f50e 100644
> --- a/drivers/gpu/drm/i915/intel_guc.h
> +++ b/drivers/gpu/drm/i915/intel_guc.h
> @@ -37,11 +37,6 @@
>
> struct __guc_ads_blob;
>
> -struct guc_preempt_work {
> - struct work_struct work;
> - struct intel_engine_cs *engine;
> -};
> -
> /*
> * Top level structure of GuC. It handles firmware loading and manages client
> * pool and doorbells. intel_guc owns a intel_guc_client to replace the legacy
> @@ -76,10 +71,6 @@ struct intel_guc {
> void *shared_data_vaddr;
>
> struct intel_guc_client *execbuf_client;
> - struct intel_guc_client *preempt_client;
> -
> - struct guc_preempt_work preempt_work[I915_NUM_ENGINES];
> - struct workqueue_struct *preempt_wq;
>
> DECLARE_BITMAP(doorbell_bitmap, GUC_NUM_DOORBELLS);
> /* Cyclic counter mod pagesize */
> diff --git a/drivers/gpu/drm/i915/intel_guc_submission.c b/drivers/gpu/drm/i915/intel_guc_submission.c
> index f104b94c14ef..8520bb224175 100644
> --- a/drivers/gpu/drm/i915/intel_guc_submission.c
> +++ b/drivers/gpu/drm/i915/intel_guc_submission.c
> @@ -46,11 +46,10 @@ enum {
> *
> * GuC client:
> * A intel_guc_client refers to a submission path through GuC. Currently, there
> - * are two clients. One of them (the execbuf_client) is charged with all
> - * submissions to the GuC, the other one (preempt_client) is responsible for
> - * preempting the execbuf_client. This struct is the owner of a doorbell, a
> - * process descriptor and a workqueue (all of them inside a single gem object
> - * that contains all required pages for these elements).
> + * is only one client, which is charged with all submissions to the GuC. This
> + * struct is the owner of a doorbell, a process descriptor and a workqueue (all
> + * of them inside a single gem object that contains all required pages for these
> + * elements).
> *
> * GuC stage descriptor:
> * During initialization, the driver allocates a static pool of 1024 such
> @@ -88,12 +87,6 @@ enum {
> *
> */
>
> -static inline u32 intel_hws_preempt_done_address(struct intel_engine_cs *engine)
> -{
> - return (i915_ggtt_offset(engine->status_page.vma) +
> - I915_GEM_HWS_PREEMPT_ADDR);
> -}
> -
> static inline struct i915_priolist *to_priolist(struct rb_node *rb)
> {
> return rb_entry(rb, struct i915_priolist, node);
> @@ -563,126 +556,6 @@ static void flush_ggtt_writes(struct i915_vma *vma)
> intel_uncore_posting_read_fw(&i915->uncore, GUC_STATUS);
> }
>
> -static void inject_preempt_context(struct work_struct *work)
> -{
> - struct guc_preempt_work *preempt_work =
> - container_of(work, typeof(*preempt_work), work);
> - struct intel_engine_cs *engine = preempt_work->engine;
> - struct intel_guc *guc = container_of(preempt_work, typeof(*guc),
> - preempt_work[engine->id]);
> - struct intel_guc_client *client = guc->preempt_client;
> - struct guc_stage_desc *stage_desc = __get_stage_desc(client);
> - struct intel_context *ce = engine->preempt_context;
> - u32 data[7];
> -
> - if (!ce->ring->emit) { /* recreate upon load/resume */
> - u32 addr = intel_hws_preempt_done_address(engine);
> - u32 *cs;
> -
> - cs = ce->ring->vaddr;
> - if (engine->class == RENDER_CLASS) {
> - cs = gen8_emit_ggtt_write_rcs(cs,
> - GUC_PREEMPT_FINISHED,
> - addr,
> - PIPE_CONTROL_CS_STALL);
> - } else {
> - cs = gen8_emit_ggtt_write(cs,
> - GUC_PREEMPT_FINISHED,
> - addr,
> - 0);
> - *cs++ = MI_NOOP;
> - *cs++ = MI_NOOP;
> - }
> - *cs++ = MI_USER_INTERRUPT;
> - *cs++ = MI_NOOP;
> -
> - ce->ring->emit = GUC_PREEMPT_BREADCRUMB_BYTES;
> - GEM_BUG_ON((void *)cs - ce->ring->vaddr != ce->ring->emit);
> -
> - flush_ggtt_writes(ce->ring->vma);
> - }
> -
> - spin_lock_irq(&client->wq_lock);
> - guc_wq_item_append(client, engine->guc_id, lower_32_bits(ce->lrc_desc),
> - GUC_PREEMPT_BREADCRUMB_BYTES / sizeof(u64), 0);
> - spin_unlock_irq(&client->wq_lock);
> -
> - /*
> - * If GuC firmware performs an engine reset while that engine had
> - * a preemption pending, it will set the terminated attribute bit
> - * on our preemption stage descriptor. GuC firmware retains all
> - * pending work items for a high-priority GuC client, unlike the
> - * normal-priority GuC client where work items are dropped. It
> - * wants to make sure the preempt-to-idle work doesn't run when
> - * scheduling resumes, and uses this bit to inform its scheduler
> - * and presumably us as well. Our job is to clear it for the next
> - * preemption after reset, otherwise that and future preemptions
> - * will never complete. We'll just clear it every time.
> - */
> - stage_desc->attribute &= ~GUC_STAGE_DESC_ATTR_TERMINATED;
> -
> - data[0] = INTEL_GUC_ACTION_REQUEST_PREEMPTION;
> - data[1] = client->stage_id;
> - data[2] = INTEL_GUC_PREEMPT_OPTION_DROP_WORK_Q |
> - INTEL_GUC_PREEMPT_OPTION_DROP_SUBMIT_Q;
> - data[3] = engine->guc_id;
> - data[4] = guc->execbuf_client->priority;
> - data[5] = guc->execbuf_client->stage_id;
> - data[6] = intel_guc_ggtt_offset(guc, guc->shared_data);
> -
> - if (WARN_ON(intel_guc_send(guc, data, ARRAY_SIZE(data)))) {
> - intel_write_status_page(engine,
> - I915_GEM_HWS_PREEMPT,
> - GUC_PREEMPT_NONE);
> - tasklet_schedule(&engine->execlists.tasklet);
> - }
> -
> - (void)I915_SELFTEST_ONLY(engine->execlists.preempt_hang.count++);
> -}
> -
> -/*
> - * We're using user interrupt and HWSP value to mark that preemption has
> - * finished and GPU is idle. Normally, we could unwind and continue similar to
> - * execlists submission path. Unfortunately, with GuC we also need to wait for
> - * it to finish its own postprocessing, before attempting to submit. Otherwise
> - * GuC may silently ignore our submissions, and thus we risk losing request at
> - * best, executing out-of-order and causing kernel panic at worst.
> - */
> -#define GUC_PREEMPT_POSTPROCESS_DELAY_MS 10
> -static void wait_for_guc_preempt_report(struct intel_engine_cs *engine)
> -{
> - struct intel_guc *guc = &engine->i915->guc;
> - struct guc_shared_ctx_data *data = guc->shared_data_vaddr;
> - struct guc_ctx_report *report =
> - &data->preempt_ctx_report[engine->guc_id];
> -
> - if (wait_for_atomic(report->report_return_status ==
> - INTEL_GUC_REPORT_STATUS_COMPLETE,
> - GUC_PREEMPT_POSTPROCESS_DELAY_MS))
> - DRM_ERROR("Timed out waiting for GuC preemption report\n");
> - /*
> - * GuC is expecting that we're also going to clear the affected context
> - * counter, let's also reset the return status to not depend on GuC
> - * resetting it after recieving another preempt action
> - */
> - report->affected_count = 0;
> - report->report_return_status = INTEL_GUC_REPORT_STATUS_UNKNOWN;
> -}
> -
> -static void complete_preempt_context(struct intel_engine_cs *engine)
> -{
> - struct intel_engine_execlists *execlists = &engine->execlists;
> -
> - if (inject_preempt_hang(execlists))
> - return;
> -
> - execlists_cancel_port_requests(execlists);
> - execlists_unwind_incomplete_requests(execlists);
> -
> - wait_for_guc_preempt_report(engine);
> - intel_write_status_page(engine, I915_GEM_HWS_PREEMPT, GUC_PREEMPT_NONE);
> -}
> -
> static void guc_submit(struct intel_engine_cs *engine,
> struct i915_request **out,
> struct i915_request **end)
> @@ -707,16 +580,6 @@ static inline int rq_prio(const struct i915_request *rq)
> return rq->sched.attr.priority | __NO_PREEMPTION;
> }
>
> -static inline int effective_prio(const struct i915_request *rq)
> -{
> - int prio = rq_prio(rq);
> -
> - if (i915_request_has_nopreempt(rq))
> - prio = I915_PRIORITY_UNPREEMPTABLE;
> -
> - return prio;
> -}
> -
> static struct i915_request *schedule_in(struct i915_request *rq, int idx)
> {
> trace_i915_request_in(rq, idx);
> @@ -752,22 +615,6 @@ static void __guc_dequeue(struct intel_engine_cs *engine)
> lockdep_assert_held(&engine->active.lock);
>
> if (last) {
> - if (intel_engine_has_preemption(engine)) {
> - struct guc_preempt_work *preempt_work =
> - &engine->i915->guc.preempt_work[engine->id];
> - int prio = execlists->queue_priority_hint;
> -
> - if (i915_scheduler_need_preempt(prio,
> - effective_prio(last))) {
> - intel_write_status_page(engine,
> - I915_GEM_HWS_PREEMPT,
> - GUC_PREEMPT_INPROGRESS);
> - queue_work(engine->i915->guc.preempt_wq,
> - &preempt_work->work);
> - return;
> - }
> - }
> -
> if (*++first)
> return;
>
> @@ -831,12 +678,7 @@ static void guc_submission_tasklet(unsigned long data)
> memmove(execlists->inflight, port, rem * sizeof(*port));
> }
>
> - if (intel_read_status_page(engine, I915_GEM_HWS_PREEMPT) ==
> - GUC_PREEMPT_FINISHED)
> - complete_preempt_context(engine);
> -
> - if (!intel_read_status_page(engine, I915_GEM_HWS_PREEMPT))
> - __guc_dequeue(engine);
> + __guc_dequeue(engine);
>
> spin_unlock_irqrestore(&engine->active.lock, flags);
> }
> @@ -857,16 +699,6 @@ static void guc_reset_prepare(struct intel_engine_cs *engine)
> * prevents the race.
> */
> __tasklet_disable_sync_once(&execlists->tasklet);
> -
> - /*
> - * We're using worker to queue preemption requests from the tasklet in
> - * GuC submission mode.
> - * Even though tasklet was disabled, we may still have a worker queued.
> - * Let's make sure that all workers scheduled before disabling the
> - * tasklet are completed before continuing with the reset.
> - */
> - if (engine->i915->guc.preempt_wq)
> - flush_workqueue(engine->i915->guc.preempt_wq);
> }
>
> static void guc_reset(struct intel_engine_cs *engine, bool stalled)
> @@ -1123,7 +955,6 @@ static int guc_clients_create(struct intel_guc *guc)
> struct intel_guc_client *client;
>
> GEM_BUG_ON(guc->execbuf_client);
> - GEM_BUG_ON(guc->preempt_client);
>
> client = guc_client_alloc(dev_priv,
> INTEL_INFO(dev_priv)->engine_mask,
> @@ -1135,20 +966,6 @@ static int guc_clients_create(struct intel_guc *guc)
> }
> guc->execbuf_client = client;
>
> - if (dev_priv->preempt_context) {
> - client = guc_client_alloc(dev_priv,
> - INTEL_INFO(dev_priv)->engine_mask,
> - GUC_CLIENT_PRIORITY_KMD_HIGH,
> - dev_priv->preempt_context);
> - if (IS_ERR(client)) {
> - DRM_ERROR("Failed to create GuC client for preemption!\n");
> - guc_client_free(guc->execbuf_client);
> - guc->execbuf_client = NULL;
> - return PTR_ERR(client);
> - }
> - guc->preempt_client = client;
> - }
> -
> return 0;
> }
>
> @@ -1156,10 +973,6 @@ static void guc_clients_destroy(struct intel_guc *guc)
> {
> struct intel_guc_client *client;
>
> - client = fetch_and_zero(&guc->preempt_client);
> - if (client)
> - guc_client_free(client);
> -
> client = fetch_and_zero(&guc->execbuf_client);
> if (client)
> guc_client_free(client);
> @@ -1202,28 +1015,11 @@ static void __guc_client_disable(struct intel_guc_client *client)
>
> static int guc_clients_enable(struct intel_guc *guc)
> {
> - int ret;
> -
> - ret = __guc_client_enable(guc->execbuf_client);
> - if (ret)
> - return ret;
> -
> - if (guc->preempt_client) {
> - ret = __guc_client_enable(guc->preempt_client);
> - if (ret) {
> - __guc_client_disable(guc->execbuf_client);
> - return ret;
> - }
> - }
> -
> - return 0;
> + return __guc_client_enable(guc->execbuf_client);
> }
>
> static void guc_clients_disable(struct intel_guc *guc)
> {
> - if (guc->preempt_client)
> - __guc_client_disable(guc->preempt_client);
> -
> if (guc->execbuf_client)
> __guc_client_disable(guc->execbuf_client);
> }
> @@ -1234,9 +1030,6 @@ static void guc_clients_disable(struct intel_guc *guc)
> */
> int intel_guc_submission_init(struct intel_guc *guc)
> {
> - struct drm_i915_private *dev_priv = guc_to_i915(guc);
> - struct intel_engine_cs *engine;
> - enum intel_engine_id id;
> int ret;
>
> if (guc->stage_desc_pool)
> @@ -1256,11 +1049,6 @@ int intel_guc_submission_init(struct intel_guc *guc)
> if (ret)
> goto err_pool;
>
> - for_each_engine(engine, dev_priv, id) {
> - guc->preempt_work[id].engine = engine;
> - INIT_WORK(&guc->preempt_work[id].work, inject_preempt_context);
> - }
> -
> return 0;
>
> err_pool:
> @@ -1270,13 +1058,6 @@ int intel_guc_submission_init(struct intel_guc *guc)
>
> void intel_guc_submission_fini(struct intel_guc *guc)
> {
> - struct drm_i915_private *dev_priv = guc_to_i915(guc);
> - struct intel_engine_cs *engine;
> - enum intel_engine_id id;
> -
> - for_each_engine(engine, dev_priv, id)
> - cancel_work_sync(&guc->preempt_work[id].work);
> -
> guc_clients_destroy(guc);
> WARN_ON(!guc_verify_doorbells(guc));
>
> diff --git a/drivers/gpu/drm/i915/selftests/intel_guc.c b/drivers/gpu/drm/i915/selftests/intel_guc.c
> index 6ca8584cd64c..1a1915e44f6b 100644
> --- a/drivers/gpu/drm/i915/selftests/intel_guc.c
> +++ b/drivers/gpu/drm/i915/selftests/intel_guc.c
> @@ -103,13 +103,10 @@ static int ring_doorbell_nop(struct intel_guc_client *client)
> /*
> * Basic client sanity check, handy to validate create_clients.
> */
> -static int validate_client(struct intel_guc_client *client,
> - int client_priority,
> - bool is_preempt_client)
> +static int validate_client(struct intel_guc_client *client, int client_priority)
> {
> struct drm_i915_private *dev_priv = guc_to_i915(client->guc);
> - struct i915_gem_context *ctx_owner = is_preempt_client ?
> - dev_priv->preempt_context : dev_priv->kernel_context;
> + struct i915_gem_context *ctx_owner = dev_priv->kernel_context;
>
> if (client->owner != ctx_owner ||
> client->engines != INTEL_INFO(dev_priv)->engine_mask ||
> @@ -163,7 +160,7 @@ static int igt_guc_clients(void *args)
> */
> guc_clients_disable(guc);
> guc_clients_destroy(guc);
> - if (guc->execbuf_client || guc->preempt_client) {
> + if (guc->execbuf_client) {
> pr_err("guc_clients_destroy lied!\n");
> err = -EINVAL;
> goto unlock;
> @@ -177,24 +174,14 @@ static int igt_guc_clients(void *args)
> GEM_BUG_ON(!guc->execbuf_client);
>
> err = validate_client(guc->execbuf_client,
> - GUC_CLIENT_PRIORITY_KMD_NORMAL, false);
> + GUC_CLIENT_PRIORITY_KMD_NORMAL);
> if (err) {
> pr_err("execbug client validation failed\n");
> goto out;
> }
>
> - if (guc->preempt_client) {
> - err = validate_client(guc->preempt_client,
> - GUC_CLIENT_PRIORITY_KMD_HIGH, true);
> - if (err) {
> - pr_err("preempt client validation failed\n");
> - goto out;
> - }
> - }
> -
> - /* each client should now have reserved a doorbell */
> - if (!has_doorbell(guc->execbuf_client) ||
> - (guc->preempt_client && !has_doorbell(guc->preempt_client))) {
> + /* the client should now have reserved a doorbell */
> + if (!has_doorbell(guc->execbuf_client)) {
> pr_err("guc_clients_create didn't reserve doorbells\n");
> err = -EINVAL;
> goto out;
> @@ -204,8 +191,7 @@ static int igt_guc_clients(void *args)
> guc_clients_enable(guc);
>
> /* each client should now have received a doorbell */
> - if (!client_doorbell_in_sync(guc->execbuf_client) ||
> - !client_doorbell_in_sync(guc->preempt_client)) {
> + if (!client_doorbell_in_sync(guc->execbuf_client)) {
> pr_err("failed to initialize the doorbells\n");
> err = -EINVAL;
> goto out;
> @@ -300,8 +286,7 @@ static int igt_guc_doorbells(void *arg)
> goto out;
> }
>
> - err = validate_client(clients[i],
> - i % GUC_CLIENT_PRIORITY_NUM, false);
> + err = validate_client(clients[i], i % GUC_CLIENT_PRIORITY_NUM);
> if (err) {
> pr_err("[%d] client_alloc sanity check failed!\n", i);
> err = -EINVAL;
> --
> 2.20.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH 02/12] drm/i915/guc: simplify guc client
2019-07-10 0:54 ` [PATCH 02/12] drm/i915/guc: simplify guc client Daniele Ceraolo Spurio
@ 2019-07-10 15:52 ` Michał Winiarski
0 siblings, 0 replies; 28+ messages in thread
From: Michał Winiarski @ 2019-07-10 15:52 UTC (permalink / raw)
To: Daniele Ceraolo Spurio; +Cc: Matthew Brost, intel-gfx
On Tue, Jul 09, 2019 at 05:54:27PM -0700, Daniele Ceraolo Spurio wrote:
> We originally added support, in some cases partial, for different modes
> of operations via guc clients:
>
> - proxy vs direct submission;
> - variable engine mask per-client.
>
> We only ever used one flow (all submissions via a single proxy), so the
> other code paths haven't been exercised and are most likely
> non-functional. The guc firmware interface is also in the process of
> being updated to better fit the i915 flow and our client abstraction
> will need to change accordingly (or possibly go away entirely), so these
> old unused paths can be considered dead and removed.
>
> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
> Cc: Matthew Brost <matthew.brost@intel.com>
> Cc: John Harrison <John.C.Harrison@Intel.com>
> Acked-by: Matthew Brost <Matthew Brost <matthew.brost@intel.com>
drm/i915/guc: simplify guc client
^ Sentence case
Reviewed-by: Michał Winiarski <michal.winiarski@intel.com>
-Michał
> ---
> drivers/gpu/drm/i915/i915_debugfs.c | 3 +-
> drivers/gpu/drm/i915/intel_guc_submission.c | 73 ++-------------------
> drivers/gpu/drm/i915/intel_guc_submission.h | 2 -
> drivers/gpu/drm/i915/selftests/intel_guc.c | 12 +---
> 4 files changed, 8 insertions(+), 82 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> index b4d195677877..dc65a6131a5b 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -2021,7 +2021,6 @@ static int i915_guc_stage_pool(struct seq_file *m, void *data)
> struct drm_i915_private *dev_priv = node_to_i915(m->private);
> const struct intel_guc *guc = &dev_priv->guc;
> struct guc_stage_desc *desc = guc->stage_desc_pool_vaddr;
> - struct intel_guc_client *client = guc->execbuf_client;
> intel_engine_mask_t tmp;
> int index;
>
> @@ -2051,7 +2050,7 @@ static int i915_guc_stage_pool(struct seq_file *m, void *data)
> desc->wq_addr, desc->wq_size);
> seq_putc(m, '\n');
>
> - for_each_engine_masked(engine, dev_priv, client->engines, tmp) {
> + for_each_engine(engine, dev_priv, tmp) {
> u32 guc_engine_id = engine->guc_id;
> struct guc_execlist_context *lrc =
> &desc->lrc[guc_engine_id];
> diff --git a/drivers/gpu/drm/i915/intel_guc_submission.c b/drivers/gpu/drm/i915/intel_guc_submission.c
> index 8520bb224175..30692f8289bd 100644
> --- a/drivers/gpu/drm/i915/intel_guc_submission.c
> +++ b/drivers/gpu/drm/i915/intel_guc_submission.c
> @@ -363,10 +363,7 @@ static void guc_stage_desc_pool_destroy(struct intel_guc *guc)
> static void guc_stage_desc_init(struct intel_guc_client *client)
> {
> struct intel_guc *guc = client->guc;
> - struct i915_gem_context *ctx = client->owner;
> - struct i915_gem_engines_iter it;
> struct guc_stage_desc *desc;
> - struct intel_context *ce;
> u32 gfx_addr;
>
> desc = __get_stage_desc(client);
> @@ -380,55 +377,6 @@ static void guc_stage_desc_init(struct intel_guc_client *client)
> desc->priority = client->priority;
> desc->db_id = client->doorbell_id;
>
> - for_each_gem_engine(ce, i915_gem_context_lock_engines(ctx), it) {
> - struct guc_execlist_context *lrc;
> -
> - if (!(ce->engine->mask & client->engines))
> - continue;
> -
> - /* TODO: We have a design issue to be solved here. Only when we
> - * receive the first batch, we know which engine is used by the
> - * user. But here GuC expects the lrc and ring to be pinned. It
> - * is not an issue for default context, which is the only one
> - * for now who owns a GuC client. But for future owner of GuC
> - * client, need to make sure lrc is pinned prior to enter here.
> - */
> - if (!ce->state)
> - break; /* XXX: continue? */
> -
> - /*
> - * XXX: When this is a GUC_STAGE_DESC_ATTR_KERNEL client (proxy
> - * submission or, in other words, not using a direct submission
> - * model) the KMD's LRCA is not used for any work submission.
> - * Instead, the GuC uses the LRCA of the user mode context (see
> - * guc_add_request below).
> - */
> - lrc = &desc->lrc[ce->engine->guc_id];
> - lrc->context_desc = lower_32_bits(ce->lrc_desc);
> -
> - /* The state page is after PPHWSP */
> - lrc->ring_lrca = intel_guc_ggtt_offset(guc, ce->state) +
> - LRC_STATE_PN * PAGE_SIZE;
> -
> - /* XXX: In direct submission, the GuC wants the HW context id
> - * here. In proxy submission, it wants the stage id
> - */
> - lrc->context_id = (client->stage_id << GUC_ELC_CTXID_OFFSET) |
> - (ce->engine->guc_id << GUC_ELC_ENGINE_OFFSET);
> -
> - lrc->ring_begin = intel_guc_ggtt_offset(guc, ce->ring->vma);
> - lrc->ring_end = lrc->ring_begin + ce->ring->size - 1;
> - lrc->ring_next_free_location = lrc->ring_begin;
> - lrc->ring_current_tail_pointer_value = 0;
> -
> - desc->engines_used |= BIT(ce->engine->guc_id);
> - }
> - i915_gem_context_unlock_engines(ctx);
> -
> - DRM_DEBUG_DRIVER("Host engines 0x%x => GuC engines used 0x%x\n",
> - client->engines, desc->engines_used);
> - WARN_ON(desc->engines_used == 0);
> -
> /*
> * The doorbell, process descriptor, and workqueue are all parts
> * of the client object, which the GuC will reference via the GGTT
> @@ -836,8 +784,7 @@ static bool guc_verify_doorbells(struct intel_guc *guc)
>
> /**
> * guc_client_alloc() - Allocate an intel_guc_client
> - * @dev_priv: driver private data structure
> - * @engines: The set of engines to enable for this client
> + * @guc: the intel_guc structure
> * @priority: four levels priority _CRITICAL, _HIGH, _NORMAL and _LOW
> * The kernel client to replace ExecList submission is created with
> * NORMAL priority. Priority of a client for scheduler can be HIGH,
> @@ -848,13 +795,9 @@ static bool guc_verify_doorbells(struct intel_guc *guc)
> * Return: An intel_guc_client object if success, else NULL.
> */
> static struct intel_guc_client *
> -guc_client_alloc(struct drm_i915_private *dev_priv,
> - u32 engines,
> - u32 priority,
> - struct i915_gem_context *ctx)
> +guc_client_alloc(struct intel_guc *guc, u32 priority)
> {
> struct intel_guc_client *client;
> - struct intel_guc *guc = &dev_priv->guc;
> struct i915_vma *vma;
> void *vaddr;
> int ret;
> @@ -864,8 +807,6 @@ guc_client_alloc(struct drm_i915_private *dev_priv,
> return ERR_PTR(-ENOMEM);
>
> client->guc = guc;
> - client->owner = ctx;
> - client->engines = engines;
> client->priority = priority;
> client->doorbell_id = GUC_DOORBELL_INVALID;
> spin_lock_init(&client->wq_lock);
> @@ -910,8 +851,8 @@ guc_client_alloc(struct drm_i915_private *dev_priv,
> else
> client->proc_desc_offset = (GUC_DB_SIZE / 2);
>
> - DRM_DEBUG_DRIVER("new priority %u client %p for engine(s) 0x%x: stage_id %u\n",
> - priority, client, client->engines, client->stage_id);
> + DRM_DEBUG_DRIVER("new priority %u client %p: stage_id %u\n",
> + priority, client, client->stage_id);
> DRM_DEBUG_DRIVER("doorbell id %u, cacheline offset 0x%lx\n",
> client->doorbell_id, client->doorbell_offset);
>
> @@ -951,15 +892,11 @@ static inline bool ctx_save_restore_disabled(struct intel_context *ce)
>
> static int guc_clients_create(struct intel_guc *guc)
> {
> - struct drm_i915_private *dev_priv = guc_to_i915(guc);
> struct intel_guc_client *client;
>
> GEM_BUG_ON(guc->execbuf_client);
>
> - client = guc_client_alloc(dev_priv,
> - INTEL_INFO(dev_priv)->engine_mask,
> - GUC_CLIENT_PRIORITY_KMD_NORMAL,
> - dev_priv->kernel_context);
> + client = guc_client_alloc(guc, GUC_CLIENT_PRIORITY_KMD_NORMAL);
> if (IS_ERR(client)) {
> DRM_ERROR("Failed to create GuC client for submission!\n");
> return PTR_ERR(client);
> diff --git a/drivers/gpu/drm/i915/intel_guc_submission.h b/drivers/gpu/drm/i915/intel_guc_submission.h
> index 7d823a513b9c..87a38cb6faf3 100644
> --- a/drivers/gpu/drm/i915/intel_guc_submission.h
> +++ b/drivers/gpu/drm/i915/intel_guc_submission.h
> @@ -58,11 +58,9 @@ struct drm_i915_private;
> struct intel_guc_client {
> struct i915_vma *vma;
> void *vaddr;
> - struct i915_gem_context *owner;
> struct intel_guc *guc;
>
> /* bitmap of (host) engine ids */
> - u32 engines;
> u32 priority;
> u32 stage_id;
> u32 proc_desc_offset;
> diff --git a/drivers/gpu/drm/i915/selftests/intel_guc.c b/drivers/gpu/drm/i915/selftests/intel_guc.c
> index 1a1915e44f6b..6ca76f5a98d4 100644
> --- a/drivers/gpu/drm/i915/selftests/intel_guc.c
> +++ b/drivers/gpu/drm/i915/selftests/intel_guc.c
> @@ -105,12 +105,7 @@ static int ring_doorbell_nop(struct intel_guc_client *client)
> */
> static int validate_client(struct intel_guc_client *client, int client_priority)
> {
> - struct drm_i915_private *dev_priv = guc_to_i915(client->guc);
> - struct i915_gem_context *ctx_owner = dev_priv->kernel_context;
> -
> - if (client->owner != ctx_owner ||
> - client->engines != INTEL_INFO(dev_priv)->engine_mask ||
> - client->priority != client_priority ||
> + if (client->priority != client_priority ||
> client->doorbell_id == GUC_DOORBELL_INVALID)
> return -EINVAL;
> else
> @@ -247,10 +242,7 @@ static int igt_guc_doorbells(void *arg)
> goto unlock;
>
> for (i = 0; i < ATTEMPTS; i++) {
> - clients[i] = guc_client_alloc(dev_priv,
> - INTEL_INFO(dev_priv)->engine_mask,
> - i % GUC_CLIENT_PRIORITY_NUM,
> - dev_priv->kernel_context);
> + clients[i] = guc_client_alloc(guc, i % GUC_CLIENT_PRIORITY_NUM);
>
> if (!clients[i]) {
> pr_err("[%d] No guc client\n", i);
> --
> 2.20.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH 04/12] drm/i915/uc: introduce intel_uc_fw_supported
2019-07-10 0:54 ` [PATCH 04/12] drm/i915/uc: introduce intel_uc_fw_supported Daniele Ceraolo Spurio
@ 2019-07-10 16:57 ` Michal Wajdeczko
2019-07-10 21:46 ` Daniele Ceraolo Spurio
0 siblings, 1 reply; 28+ messages in thread
From: Michal Wajdeczko @ 2019-07-10 16:57 UTC (permalink / raw)
To: intel-gfx, Daniele Ceraolo Spurio
On Wed, 10 Jul 2019 02:54:29 +0200, Daniele Ceraolo Spurio
<daniele.ceraolospurio@intel.com> wrote:
> Instead of always checking in the device config is GuC and HuC are
s/is/if
> supported or not, we can save the state in the uc_fw structure and
> avoid going through i915 every time from the low-level uc management
> code. while at it FIRMWARE_NONE has been renamed to better indicate that
s/while/While
> we haven't started the fetch/load yet, but we might have already selected
> a blob.
>
> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
> ---
> drivers/gpu/drm/i915/intel_guc_fw.c | 6 +++++-
> drivers/gpu/drm/i915/intel_huc_fw.c | 6 +++++-
> drivers/gpu/drm/i915/intel_uc.c | 25 ++++++++++++------------
> drivers/gpu/drm/i915/intel_uc_fw.c | 4 +++-
> drivers/gpu/drm/i915/intel_uc_fw.h | 30 ++++++++++++++++++++++++-----
> 5 files changed, 51 insertions(+), 20 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_guc_fw.c
> b/drivers/gpu/drm/i915/intel_guc_fw.c
> index db1e0daca7db..ee95d4960c5c 100644
> --- a/drivers/gpu/drm/i915/intel_guc_fw.c
> +++ b/drivers/gpu/drm/i915/intel_guc_fw.c
> @@ -79,8 +79,12 @@ static void guc_fw_select(struct intel_uc_fw *guc_fw)
> GEM_BUG_ON(guc_fw->type != INTEL_UC_FW_TYPE_GUC);
> - if (!HAS_GUC(i915))
> + if (!HAS_GUC(i915)) {
> + guc_fw->fetch_status = INTEL_UC_FIRMWARE_NOT_SUPPORTED;
> return;
> + }
> +
> + guc_fw->fetch_status = INTEL_UC_FIRMWARE_NOT_STARTED;
> if (i915_modparams.guc_firmware_path) {
> guc_fw->path = i915_modparams.guc_firmware_path;
> diff --git a/drivers/gpu/drm/i915/intel_huc_fw.c
> b/drivers/gpu/drm/i915/intel_huc_fw.c
> index 05cbf8338f53..06e726ba9863 100644
> --- a/drivers/gpu/drm/i915/intel_huc_fw.c
> +++ b/drivers/gpu/drm/i915/intel_huc_fw.c
> @@ -73,8 +73,12 @@ static void huc_fw_select(struct intel_uc_fw *huc_fw)
> GEM_BUG_ON(huc_fw->type != INTEL_UC_FW_TYPE_HUC);
> - if (!HAS_HUC(dev_priv))
> + if (!HAS_HUC(dev_priv)) {
> + huc_fw->fetch_status = INTEL_UC_FIRMWARE_NOT_SUPPORTED;
> return;
> + }
> +
> + huc_fw->fetch_status = INTEL_UC_FIRMWARE_NOT_STARTED;
> if (i915_modparams.huc_firmware_path) {
> huc_fw->path = i915_modparams.huc_firmware_path;
> diff --git a/drivers/gpu/drm/i915/intel_uc.c
> b/drivers/gpu/drm/i915/intel_uc.c
> index 789b0bccfb41..ef2a864b8990 100644
> --- a/drivers/gpu/drm/i915/intel_uc.c
> +++ b/drivers/gpu/drm/i915/intel_uc.c
> @@ -71,7 +71,8 @@ static int __get_default_guc_log_level(struct
> drm_i915_private *i915)
> {
> int guc_log_level;
> - if (!HAS_GUC(i915) || !intel_uc_is_using_guc(i915))
> + if (!intel_uc_fw_supported(&i915->guc.fw) ||
this goes too far, we should limit number of direct accesses to .fw
maybe we can have:
inline bool intel_uc_has_guc(i915)
{
return intel_guc_is_present(&i915->guc);
}
inline bool intel_guc_is_present(guc)
{
return intel_uc_fw_is_defined(&guc->fw);
}
> + !intel_uc_is_using_guc(i915))
> guc_log_level = GUC_LOG_LEVEL_DISABLED;
> else if (IS_ENABLED(CONFIG_DRM_I915_DEBUG) ||
> IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM))
> @@ -119,16 +120,16 @@ static void sanitize_options_early(struct
> drm_i915_private *i915)
> if (intel_uc_is_using_guc(i915) && !intel_uc_fw_is_selected(guc_fw)) {
> DRM_WARN("Incompatible option detected: %s=%d, %s!\n",
> "enable_guc", i915_modparams.enable_guc,
> - !HAS_GUC(i915) ? "no GuC hardware" :
> - "no GuC firmware");
> + !intel_uc_fw_supported(guc_fw) ?
> + "no GuC hardware" : "no GuC firmware");
> }
> /* Verify HuC firmware availability */
> if (intel_uc_is_using_huc(i915) && !intel_uc_fw_is_selected(huc_fw)) {
> DRM_WARN("Incompatible option detected: %s=%d, %s!\n",
> "enable_guc", i915_modparams.enable_guc,
> - !HAS_HUC(i915) ? "no HuC hardware" :
> - "no HuC firmware");
> + !intel_uc_fw_supported(huc_fw) ?
> + "no HuC hardware" : "no HuC firmware");
> }
> /* XXX: GuC submission is unavailable for now */
> @@ -148,8 +149,8 @@ static void sanitize_options_early(struct
> drm_i915_private *i915)
> if (i915_modparams.guc_log_level > 0 && !intel_uc_is_using_guc(i915)) {
> DRM_WARN("Incompatible option detected: %s=%d, %s!\n",
> "guc_log_level", i915_modparams.guc_log_level,
> - !HAS_GUC(i915) ? "no GuC hardware" :
> - "GuC not enabled");
> + !intel_uc_fw_supported(guc_fw) ?
> + "no GuC hardware" : "GuC not enabled");
> i915_modparams.guc_log_level = 0;
> }
> @@ -376,7 +377,7 @@ int intel_uc_init(struct drm_i915_private *i915)
> if (!USES_GUC(i915))
> return 0;
> - if (!HAS_GUC(i915))
> + if (!intel_uc_fw_supported(&guc->fw))
> return -ENODEV;
> /* XXX: GuC submission is unavailable for now */
> @@ -419,7 +420,7 @@ void intel_uc_fini(struct drm_i915_private *i915)
> if (!USES_GUC(i915))
> return;
> - GEM_BUG_ON(!HAS_GUC(i915));
> + GEM_BUG_ON(!intel_uc_fw_supported(&guc->fw));
> if (USES_GUC_SUBMISSION(i915))
> intel_guc_submission_fini(guc);
> @@ -435,7 +436,7 @@ static void __uc_sanitize(struct drm_i915_private
> *i915)
> struct intel_guc *guc = &i915->guc;
> struct intel_huc *huc = &i915->huc;
> - GEM_BUG_ON(!HAS_GUC(i915));
> + GEM_BUG_ON(!intel_uc_fw_supported(&guc->fw));
> intel_huc_sanitize(huc);
> intel_guc_sanitize(guc);
> @@ -460,7 +461,7 @@ int intel_uc_init_hw(struct drm_i915_private *i915)
> if (!USES_GUC(i915))
> return 0;
> - GEM_BUG_ON(!HAS_GUC(i915));
> + GEM_BUG_ON(!intel_uc_fw_supported(&guc->fw));
> guc_reset_interrupts(guc);
> @@ -557,7 +558,7 @@ void intel_uc_fini_hw(struct drm_i915_private *i915)
> if (!intel_guc_is_loaded(guc))
> return;
> - GEM_BUG_ON(!HAS_GUC(i915));
> + GEM_BUG_ON(!intel_uc_fw_supported(&guc->fw));
> if (USES_GUC_SUBMISSION(i915))
> intel_guc_submission_disable(guc);
> diff --git a/drivers/gpu/drm/i915/intel_uc_fw.c
> b/drivers/gpu/drm/i915/intel_uc_fw.c
> index f342ddd47df8..8ce7210907c0 100644
> --- a/drivers/gpu/drm/i915/intel_uc_fw.c
> +++ b/drivers/gpu/drm/i915/intel_uc_fw.c
> @@ -47,6 +47,8 @@ void intel_uc_fw_fetch(struct drm_i915_private
> *dev_priv,
> size_t size;
> int err;
> + GEM_BUG_ON(!intel_uc_fw_supported(uc_fw));
> +
> if (!uc_fw->path) {
> dev_info(dev_priv->drm.dev,
> "%s: No firmware was defined for %s!\n",
> @@ -328,7 +330,7 @@ void intel_uc_fw_cleanup_fetch(struct intel_uc_fw
> *uc_fw)
> if (obj)
> i915_gem_object_put(obj);
> - uc_fw->fetch_status = INTEL_UC_FIRMWARE_NONE;
> + uc_fw->fetch_status = INTEL_UC_FIRMWARE_NOT_STARTED;
> }
> /**
> diff --git a/drivers/gpu/drm/i915/intel_uc_fw.h
> b/drivers/gpu/drm/i915/intel_uc_fw.h
> index 24e66469153c..833d04d06576 100644
> --- a/drivers/gpu/drm/i915/intel_uc_fw.h
> +++ b/drivers/gpu/drm/i915/intel_uc_fw.h
> @@ -26,6 +26,7 @@
> #define _INTEL_UC_FW_H_
> #include <linux/types.h>
> +#include "i915_gem.h"
> struct drm_printer;
> struct drm_i915_private;
> @@ -34,8 +35,10 @@ struct drm_i915_private;
> #define INTEL_UC_FIRMWARE_URL
> "https://git.kernel.org/pub/scm/linux/kernel/git/firmware/linux-firmware.git/tree/i915"
> enum intel_uc_fw_status {
> + INTEL_UC_FIRMWARE_NOT_SUPPORTED = -2, /* no uc HW */
> INTEL_UC_FIRMWARE_FAIL = -1,
> - INTEL_UC_FIRMWARE_NONE = 0,
> + INTEL_UC_FIRMWARE_UNINITIALIZED = 0, /* used to catch checks done too
> early */
> + INTEL_UC_FIRMWARE_NOT_STARTED = 1,
> INTEL_UC_FIRMWARE_PENDING,
> INTEL_UC_FIRMWARE_SUCCESS
> };
> @@ -79,10 +82,14 @@ static inline
> const char *intel_uc_fw_status_repr(enum intel_uc_fw_status status)
> {
> switch (status) {
> + case INTEL_UC_FIRMWARE_NOT_SUPPORTED:
maybe INTEL_UC_FIRMWARE_NOT_APPLICABLE, as used in string below?
> + return "N/A - uc HW not available";
note that other states have short strings, so just "N/A" ?
> case INTEL_UC_FIRMWARE_FAIL:
> return "FAIL";
> - case INTEL_UC_FIRMWARE_NONE:
> - return "NONE";
> + case INTEL_UC_FIRMWARE_UNINITIALIZED:
> + return "UNINITIALIZED";
> + case INTEL_UC_FIRMWARE_NOT_STARTED:
> + return "NOT_STARTED";
NOT_STARTED and PENDING are not that much different,
see below
> case INTEL_UC_FIRMWARE_PENDING:
> return "PENDING";
> case INTEL_UC_FIRMWARE_SUCCESS:
maybe we should drop split on fetch/load and use
single status, something like:
UNINITIALIZED --> N/A (no HW)
|
DEFINED ----> MISSING (no valid fw)
|
-> FETCHED/UNLOADED <-
/ | \
\ LOADING /
\ / \ /
\- READY FAILED -/
> @@ -106,9 +113,15 @@ static inline
> void intel_uc_fw_init_early(struct intel_uc_fw *uc_fw,
> enum intel_uc_fw_type type)
> {
> + /*
> + * we use FIRMWARE_UNINITIALIZED to detect checks against fetch_status
> + * before we're looked at the HW caps to see if we have uc support
> + */
> + BUILD_BUG_ON(INTEL_UC_FIRMWARE_UNINITIALIZED);
> +
> uc_fw->path = NULL;
> - uc_fw->fetch_status = INTEL_UC_FIRMWARE_NONE;
> - uc_fw->load_status = INTEL_UC_FIRMWARE_NONE;
> + uc_fw->fetch_status = INTEL_UC_FIRMWARE_UNINITIALIZED;
> + uc_fw->load_status = INTEL_UC_FIRMWARE_NOT_STARTED;
> uc_fw->type = type;
> }
> @@ -122,6 +135,13 @@ static inline bool intel_uc_fw_is_loaded(struct
> intel_uc_fw *uc_fw)
> return uc_fw->load_status == INTEL_UC_FIRMWARE_SUCCESS;
> }
> +static inline bool intel_uc_fw_supported(struct intel_uc_fw *uc_fw)
returning "supported" in case of "no blob/no defs" might be misleading
maybe "defined" will clearer ?
> +{
> + /* shouldn't call this before checking hw/blob availability */
> + GEM_BUG_ON(uc_fw->fetch_status == INTEL_UC_FIRMWARE_UNINITIALIZED);
> + return uc_fw->fetch_status != INTEL_UC_FIRMWARE_NOT_SUPPORTED;
> +}
> +
> static inline void intel_uc_fw_sanitize(struct intel_uc_fw *uc_fw)
> {
> if (intel_uc_fw_is_loaded(uc_fw))
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH 06/12] drm/i915/guc: unify guc irq handling
2019-07-10 0:54 ` [PATCH 06/12] drm/i915/guc: unify guc irq handling Daniele Ceraolo Spurio
@ 2019-07-10 17:04 ` Michal Wajdeczko
0 siblings, 0 replies; 28+ messages in thread
From: Michal Wajdeczko @ 2019-07-10 17:04 UTC (permalink / raw)
To: intel-gfx, Daniele Ceraolo Spurio
On Wed, 10 Jul 2019 02:54:31 +0200, Daniele Ceraolo Spurio
<daniele.ceraolospurio@intel.com> wrote:
> The 16-bit guc irq vector is unchanged across gens, the only thing that
> moved is its position (from the upper 16 bits of the PM regs to its own
> register). Instead of duplicating all defines and functions to handle
> the 2 different positions, we can work on the vector and shift it as
> appropriate. While at it, update the handler to work on intel_guc.
>
> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
> ---
> drivers/gpu/drm/i915/i915_irq.c | 24 ++++++++-------------
> drivers/gpu/drm/i915/i915_reg.h | 10 ---------
> drivers/gpu/drm/i915/intel_guc_reg.h | 32 ++++++++++++++--------------
> 3 files changed, 25 insertions(+), 41 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_irq.c
> b/drivers/gpu/drm/i915/i915_irq.c
> index 831d185c07d2..42d6d8bfac70 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -264,7 +264,7 @@ static void gen2_irq_init(struct intel_uncore
> *uncore,
> gen2_irq_init((uncore), imr_val, ier_val)
> static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32
> pm_iir);
> -static void gen9_guc_irq_handler(struct drm_i915_private *dev_priv, u32
> pm_iir);
> +static void guc_irq_handler(struct intel_guc *guc, u16 guc_iir);
> /* For display hotplug interrupt */
> static inline void
> @@ -658,8 +658,7 @@ void gen11_enable_guc_interrupts(struct intel_guc
> *guc)
> spin_lock_irq(&dev_priv->irq_lock);
> if (!guc->interrupts.enabled) {
> - u32 events = REG_FIELD_PREP(ENGINE1_MASK,
> - GEN11_GUC_INTR_GUC2HOST);
> + u32 events = REG_FIELD_PREP(ENGINE1_MASK, GUC_INTR_GUC2HOST);
> WARN_ON_ONCE(gen11_reset_one_iir(&dev_priv->gt, 0, GEN11_GUC));
> I915_WRITE(GEN11_GUC_SG_INTR_ENABLE, events);
> @@ -1656,7 +1655,7 @@ static void gen8_gt_irq_handler(struct
> drm_i915_private *i915,
> if (master_ctl & (GEN8_GT_PM_IRQ | GEN8_GT_GUC_IRQ)) {
> gen6_rps_irq_handler(i915, gt_iir[2]);
> - gen9_guc_irq_handler(i915, gt_iir[2]);
> + guc_irq_handler(&i915->guc, gt_iir[2] >> 16);
> }
> }
> @@ -1955,16 +1954,10 @@ static void gen6_rps_irq_handler(struct
> drm_i915_private *dev_priv, u32 pm_iir)
> DRM_DEBUG("Command parser error, pm_iir 0x%08x\n", pm_iir);
> }
> -static void gen9_guc_irq_handler(struct drm_i915_private *dev_priv, u32
> gt_iir)
> +static void guc_irq_handler(struct intel_guc *guc, u16 iir)
maybe it's the good time to move this handler out to intel_guc.c ?
> {
> - if (gt_iir & GEN9_GUC_TO_HOST_INT_EVENT)
> - intel_guc_to_host_event_handler(&dev_priv->guc);
> -}
> -
> -static void gen11_guc_irq_handler(struct drm_i915_private *i915, u16
> iir)
> -{
> - if (iir & GEN11_GUC_INTR_GUC2HOST)
> - intel_guc_to_host_event_handler(&i915->guc);
> + if (iir & GUC_INTR_GUC2HOST)
> + intel_guc_to_host_event_handler(guc);
> }
> static void i9xx_pipestat_irq_reset(struct drm_i915_private *dev_priv)
> @@ -3092,7 +3085,7 @@ gen11_other_irq_handler(struct intel_gt *gt, const
> u8 instance,
> struct drm_i915_private *i915 = gt->i915;
> if (instance == OTHER_GUC_INSTANCE)
> - return gen11_guc_irq_handler(i915, iir);
> + return guc_irq_handler(&i915->guc, iir);
> if (instance == OTHER_GTPM_INSTANCE)
> return gen11_rps_irq_handler(gt, iir);
> @@ -4764,8 +4757,9 @@ void intel_irq_init(struct drm_i915_private
> *dev_priv)
> for (i = 0; i < MAX_L3_SLICES; ++i)
> dev_priv->l3_parity.remap_info[i] = NULL;
> + /* pre-gen11 the guc irqs bits are in the upper 16 bits of the pm reg
> */
s/gen11/Gen11
s/guc/GuC
> if (HAS_GUC_SCHED(dev_priv) && INTEL_GEN(dev_priv) < 11)
> - dev_priv->pm_guc_events = GEN9_GUC_TO_HOST_INT_EVENT;
> + dev_priv->pm_guc_events = GUC_INTR_GUC2HOST << 16;
maybe we should add definition for this mask in PM register
#define GEN8_PM_IIR_GUC_MASK 0xFFFF0000
and then
dev_priv->pm_guc_events = REG_FIELD_PREP(GEN8_PM_IIR_GUC_MASK,
GUC_INTR_GUC2HOST)
and in gen8_gt_irq_handler() earlier above
guc_irq_handler(&i915->guc, REG_FIELD_GET(GEN8_PM_IIR_GUC_MASK,
gt_iir[2]));
> /* Let's track the enabled rps events */
> if (IS_VALLEYVIEW(dev_priv))
> diff --git a/drivers/gpu/drm/i915/i915_reg.h
> b/drivers/gpu/drm/i915/i915_reg.h
> index 5898f59e3dd7..4dc31e488b80 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7342,16 +7342,6 @@ enum {
> #define GEN8_GT_IIR(which) _MMIO(0x44308 + (0x10 * (which)))
> #define GEN8_GT_IER(which) _MMIO(0x4430c + (0x10 * (which)))
> -#define GEN9_GUC_TO_HOST_INT_EVENT (1 << 31)
> -#define GEN9_GUC_EXEC_ERROR_EVENT (1 << 30)
> -#define GEN9_GUC_DISPLAY_EVENT (1 << 29)
> -#define GEN9_GUC_SEMA_SIGNAL_EVENT (1 << 28)
> -#define GEN9_GUC_IOMMU_MSG_EVENT (1 << 27)
> -#define GEN9_GUC_DB_RING_EVENT (1 << 26)
> -#define GEN9_GUC_DMA_DONE_EVENT (1 << 25)
> -#define GEN9_GUC_FATAL_ERROR_EVENT (1 << 24)
> -#define GEN9_GUC_NOTIFICATION_EVENT (1 << 23)
> -
> #define GEN8_RCS_IRQ_SHIFT 0
> #define GEN8_BCS_IRQ_SHIFT 16
> #define GEN8_VCS0_IRQ_SHIFT 0 /* NB: VCS1 in bspec! */
> diff --git a/drivers/gpu/drm/i915/intel_guc_reg.h
> b/drivers/gpu/drm/i915/intel_guc_reg.h
> index a5ab7bc5504c..e3cbb23299ce 100644
> --- a/drivers/gpu/drm/i915/intel_guc_reg.h
> +++ b/drivers/gpu/drm/i915/intel_guc_reg.h
> @@ -141,21 +141,21 @@ struct guc_doorbell_info {
> #define GUC_PM_P24C_IER _MMIO(0xC55C)
> /* GuC Interrupt Vector */
> -#define GEN11_GUC_INTR_GUC2HOST (1 << 15)
> -#define GEN11_GUC_INTR_EXEC_ERROR (1 << 14)
> -#define GEN11_GUC_INTR_DISPLAY_EVENT (1 << 13)
> -#define GEN11_GUC_INTR_SEM_SIG (1 << 12)
> -#define GEN11_GUC_INTR_IOMMU2GUC (1 << 11)
> -#define GEN11_GUC_INTR_DOORBELL_RANG (1 << 10)
> -#define GEN11_GUC_INTR_DMA_DONE (1 << 9)
> -#define GEN11_GUC_INTR_FATAL_ERROR (1 << 8)
> -#define GEN11_GUC_INTR_NOTIF_ERROR (1 << 7)
> -#define GEN11_GUC_INTR_SW_INT_6 (1 << 6)
> -#define GEN11_GUC_INTR_SW_INT_5 (1 << 5)
> -#define GEN11_GUC_INTR_SW_INT_4 (1 << 4)
> -#define GEN11_GUC_INTR_SW_INT_3 (1 << 3)
> -#define GEN11_GUC_INTR_SW_INT_2 (1 << 2)
> -#define GEN11_GUC_INTR_SW_INT_1 (1 << 1)
> -#define GEN11_GUC_INTR_SW_INT_0 (1 << 0)
> +#define GUC_INTR_GUC2HOST BIT(15)
> +#define GUC_INTR_EXEC_ERROR BIT(14)
> +#define GUC_INTR_DISPLAY_EVENT BIT(13)
> +#define GUC_INTR_SEM_SIG BIT(12)
> +#define GUC_INTR_IOMMU2GUC BIT(11)
> +#define GUC_INTR_DOORBELL_RANG BIT(10)
> +#define GUC_INTR_DMA_DONE BIT(9)
> +#define GUC_INTR_FATAL_ERROR BIT(8)
> +#define GUC_INTR_NOTIF_ERROR BIT(7)
> +#define GUC_INTR_SW_INT_6 BIT(6)
> +#define GUC_INTR_SW_INT_5 BIT(5)
> +#define GUC_INTR_SW_INT_4 BIT(4)
> +#define GUC_INTR_SW_INT_3 BIT(3)
> +#define GUC_INTR_SW_INT_2 BIT(2)
> +#define GUC_INTR_SW_INT_1 BIT(1)
> +#define GUC_INTR_SW_INT_0 BIT(0)
shouldn't we use REG_BIT here?
with/without above nits,
Reviewed-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH 07/12] drm/i915/uc: move GuC and HuC files under gt/uc/
2019-07-10 0:54 ` [PATCH 07/12] drm/i915/uc: move GuC and HuC files under gt/uc/ Daniele Ceraolo Spurio
@ 2019-07-10 17:52 ` Michal Wajdeczko
0 siblings, 0 replies; 28+ messages in thread
From: Michal Wajdeczko @ 2019-07-10 17:52 UTC (permalink / raw)
To: intel-gfx, Daniele Ceraolo Spurio
On Wed, 10 Jul 2019 02:54:32 +0200, Daniele Ceraolo Spurio
<daniele.ceraolospurio@intel.com> wrote:
> Both microcontrollers are part of the GT HW and are closely related to
> GT operations. To keep all the files cleanly together, they've been
> placed in their own subdir inside the gt/ folder
>
> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> ---
Acked-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
with some nits below
<snap>
> diff --git a/drivers/gpu/drm/i915/Makefile
> b/drivers/gpu/drm/i915/Makefile
> index 5266dbeab01f..524516251a40 100644
> --- a/drivers/gpu/drm/i915/Makefile
> +++ b/drivers/gpu/drm/i915/Makefile
> @@ -139,16 +139,17 @@ i915-y += \
> intel_wopcm.o
> # general-purpose microcontroller (GuC) support
> -i915-y += intel_uc.o \
> - intel_uc_fw.o \
> - intel_guc.o \
> - intel_guc_ads.o \
> - intel_guc_ct.o \
> - intel_guc_fw.o \
> - intel_guc_log.o \
> - intel_guc_submission.o \
> - intel_huc.o \
> - intel_huc_fw.o
> +obj-y += gt/uc/
> +i915-y += gt/uc/intel_uc.o \
nit: can we put first file on separate line as well, so
i915-y += \
> + gt/uc/intel_uc_fw.o \
> + gt/uc/intel_guc.o \
> + gt/uc/intel_guc_ads.o \
> + gt/uc/intel_guc_ct.o \
> + gt/uc/intel_guc_fw.o \
> + gt/uc/intel_guc_log.o \
> + gt/uc/intel_guc_submission.o \
> + gt/uc/intel_huc.o \
> + gt/uc/intel_huc_fw.o
and iirc bkm is to order all files by name, so uc* should be last
_______________________________________________
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Intel-gfx@lists.freedesktop.org
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^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH 08/12] drm/i915/uc: move GuC/HuC inside intel_gt under a new intel_uc
2019-07-10 0:54 ` [PATCH 08/12] drm/i915/uc: move GuC/HuC inside intel_gt under a new intel_uc Daniele Ceraolo Spurio
@ 2019-07-10 18:22 ` Michal Wajdeczko
0 siblings, 0 replies; 28+ messages in thread
From: Michal Wajdeczko @ 2019-07-10 18:22 UTC (permalink / raw)
To: intel-gfx, Daniele Ceraolo Spurio
On Wed, 10 Jul 2019 02:54:33 +0200, Daniele Ceraolo Spurio
<daniele.ceraolospurio@intel.com> wrote:
> Being part of the GT HW, it make sense to keep the guc/huc structures
> inside the GT structure. To help with the encapsulation work done by the
> following patches, both structures are placed inside a new intel_uc
> container. Although this results in code with ugly nested dereferences
> (i915->gt.uc.guc...), it saves us the extra work required in moving
> the structures twice (i915 -> gt -> uc). The following patches will
> reduce the number of places where we try to access the guc/huc
> structures directly from i915 and reduce the ugliness.
>
> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> ---
> drivers/gpu/drm/i915/gt/intel_gt_types.h | 4 ++
> drivers/gpu/drm/i915/gt/intel_reset.c | 6 +--
> .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 2 +-
> drivers/gpu/drm/i915/gt/uc/intel_huc.c | 4 +-
> drivers/gpu/drm/i915/gt/uc/intel_uc.c | 52 +++++++++----------
> drivers/gpu/drm/i915/gt/uc/intel_uc.h | 5 ++
> drivers/gpu/drm/i915/gt/uc/selftest_guc.c | 4 +-
> drivers/gpu/drm/i915/i915_debugfs.c | 26 +++++-----
> drivers/gpu/drm/i915/i915_drv.c | 2 +-
> drivers/gpu/drm/i915/i915_drv.h | 7 +--
> drivers/gpu/drm/i915/i915_gpu_error.c | 11 ++--
> drivers/gpu/drm/i915/i915_irq.c | 6 +--
> drivers/gpu/drm/i915/intel_wopcm.c | 4 +-
> 13 files changed, 69 insertions(+), 64 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_types.h
> b/drivers/gpu/drm/i915/gt/intel_gt_types.h
> index 3563ce970102..b711252ff427 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_types.h
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h
> @@ -13,6 +13,8 @@
> #include <linux/spinlock.h>
> #include <linux/types.h>
> +#include "uc/intel_uc.h"
> +
> #include "i915_vma.h"
> #include "intel_wakeref.h"
> @@ -25,6 +27,8 @@ struct intel_gt {
> struct intel_uncore *uncore;
> struct i915_ggtt *ggtt;
> + struct intel_uc uc;
> +
> struct intel_gt_timelines {
> struct mutex mutex; /* protects list */
> struct list_head active_list;
> diff --git a/drivers/gpu/drm/i915/gt/intel_reset.c
> b/drivers/gpu/drm/i915/gt/intel_reset.c
> index 9abfa28c3020..ccedea636ba3 100644
> --- a/drivers/gpu/drm/i915/gt/intel_reset.c
> +++ b/drivers/gpu/drm/i915/gt/intel_reset.c
> @@ -1109,14 +1109,14 @@ int i915_reset_engine(struct intel_engine_cs
> *engine, const char *msg)
> "Resetting %s for %s\n", engine->name, msg);
> error->reset_engine_count[engine->id]++;
> - if (!engine->i915->guc.execbuf_client)
> + if (!engine->gt->uc.guc.execbuf_client)
> ret = intel_gt_reset_engine(engine->i915, engine);
> else
> - ret = intel_guc_reset_engine(&engine->i915->guc, engine);
> + ret = intel_guc_reset_engine(&engine->gt->uc.guc, engine);
> if (ret) {
> /* If we fail here, we expect to fallback to a global reset */
> DRM_DEBUG_DRIVER("%sFailed to reset %s, ret=%d\n",
> - engine->i915->guc.execbuf_client ? "GuC " : "",
> + engine->gt->uc.guc.execbuf_client ? "GuC " : "",
maybe instead of doing 3x same deref, just add at the start:
struct intel_guc *guc = &engine->gt->uc.guc;
> engine->name, ret);
> goto out;
> }
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> index f015f7dee453..23906228b9b4 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> @@ -509,7 +509,7 @@ static void guc_submit(struct intel_engine_cs
> *engine,
> struct i915_request **out,
> struct i915_request **end)
> {
> - struct intel_guc *guc = &engine->i915->guc;
> + struct intel_guc *guc = &engine->gt->uc.guc;
> struct intel_guc_client *client = guc->execbuf_client;
> spin_lock(&client->wq_lock);
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_huc.c
> b/drivers/gpu/drm/i915/gt/uc/intel_huc.c
> index 2a41ee89a16d..581c9c3d4fc0 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_huc.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_huc.c
> @@ -47,7 +47,7 @@ void intel_huc_init_early(struct intel_huc *huc)
> static int intel_huc_rsa_data_create(struct intel_huc *huc)
> {
> struct drm_i915_private *i915 = huc_to_i915(huc);
> - struct intel_guc *guc = &i915->guc;
> + struct intel_guc *guc = &i915->gt.uc.guc;
maybe we can avoid i915/gt dance with:
struct intel_guc *guc = huc_to_uc(huc)->guc;
> struct i915_vma *vma;
> void *vaddr;
> @@ -113,7 +113,7 @@ void intel_huc_fini(struct intel_huc *huc)
> int intel_huc_auth(struct intel_huc *huc)
> {
> struct drm_i915_private *i915 = huc_to_i915(huc);
> - struct intel_guc *guc = &i915->guc;
> + struct intel_guc *guc = &i915->gt.uc.guc;
> int ret;
> if (huc->fw.load_status != INTEL_UC_FIRMWARE_SUCCESS)
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc.c
> b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
> index 6193b87855e0..e2080da2e1e4 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_uc.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
> @@ -54,8 +54,8 @@ static int __intel_uc_reset_hw(struct drm_i915_private
> *dev_priv)
> static int __get_platform_enable_guc(struct drm_i915_private *i915)
> {
> - struct intel_uc_fw *guc_fw = &i915->guc.fw;
> - struct intel_uc_fw *huc_fw = &i915->huc.fw;
> + struct intel_uc_fw *guc_fw = &i915->gt.uc.guc.fw;
> + struct intel_uc_fw *huc_fw = &i915->gt.uc.huc.fw;
maybe first add:
struct intel_uc *uc = &i915->gt.uc;
then
struct intel_uc_fw *guc_fw = &uc->guc.fw;
struct intel_uc_fw *huc_fw = &uc->huc.fw;
> int enable_guc = 0;
> /* Default is to use HuC if we know GuC and HuC firmwares */
> @@ -71,7 +71,7 @@ static int __get_default_guc_log_level(struct
> drm_i915_private *i915)
> {
> int guc_log_level;
> - if (!intel_uc_fw_supported(&i915->guc.fw) ||
> + if (!intel_uc_fw_supported(&i915->gt.uc.guc.fw) ||
> !intel_uc_is_using_guc(i915))
> guc_log_level = GUC_LOG_LEVEL_DISABLED;
> else if (IS_ENABLED(CONFIG_DRM_I915_DEBUG) ||
> @@ -104,8 +104,8 @@ static int __get_default_guc_log_level(struct
> drm_i915_private *i915)
> */
> static void sanitize_options_early(struct drm_i915_private *i915)
> {
> - struct intel_uc_fw *guc_fw = &i915->guc.fw;
> - struct intel_uc_fw *huc_fw = &i915->huc.fw;
> + struct intel_uc_fw *guc_fw = &i915->gt.uc.guc.fw;
> + struct intel_uc_fw *huc_fw = &i915->gt.uc.huc.fw;
same here
> /* A negative value means "use platform default" */
> if (i915_modparams.enable_guc < 0)
> @@ -174,8 +174,8 @@ static void sanitize_options_early(struct
> drm_i915_private *i915)
> void intel_uc_init_early(struct drm_i915_private *i915)
> {
> - struct intel_guc *guc = &i915->guc;
> - struct intel_huc *huc = &i915->huc;
> + struct intel_guc *guc = &i915->gt.uc.guc;
> + struct intel_huc *huc = &i915->gt.uc.huc;
and here
and in all other uc functions
> intel_guc_init_early(guc);
> intel_huc_init_early(huc);
> @@ -185,7 +185,7 @@ void intel_uc_init_early(struct drm_i915_private
> *i915)
> void intel_uc_cleanup_early(struct drm_i915_private *i915)
> {
> - struct intel_guc *guc = &i915->guc;
> + struct intel_guc *guc = &i915->gt.uc.guc;
> guc_free_load_err_log(guc);
> }
> @@ -199,7 +199,7 @@ void intel_uc_cleanup_early(struct drm_i915_private
> *i915)
> */
> void intel_uc_init_mmio(struct drm_i915_private *i915)
> {
> - intel_guc_init_send_regs(&i915->guc);
> + intel_guc_init_send_regs(&i915->gt.uc.guc);
> }
> static void guc_capture_load_err_log(struct intel_guc *guc)
> @@ -351,10 +351,10 @@ void intel_uc_fetch_firmwares(struct
> drm_i915_private *i915)
> if (!USES_GUC(i915))
> return;
> - intel_uc_fw_fetch(i915, &i915->guc.fw);
> + intel_uc_fw_fetch(i915, &i915->gt.uc.guc.fw);
> if (USES_HUC(i915))
> - intel_uc_fw_fetch(i915, &i915->huc.fw);
> + intel_uc_fw_fetch(i915, &i915->gt.uc.huc.fw);
> }
> void intel_uc_cleanup_firmwares(struct drm_i915_private *i915)
> @@ -363,15 +363,15 @@ void intel_uc_cleanup_firmwares(struct
> drm_i915_private *i915)
> return;
> if (USES_HUC(i915))
> - intel_uc_fw_cleanup_fetch(&i915->huc.fw);
> + intel_uc_fw_cleanup_fetch(&i915->gt.uc.huc.fw);
> - intel_uc_fw_cleanup_fetch(&i915->guc.fw);
> + intel_uc_fw_cleanup_fetch(&i915->gt.uc.guc.fw);
> }
> int intel_uc_init(struct drm_i915_private *i915)
> {
> - struct intel_guc *guc = &i915->guc;
> - struct intel_huc *huc = &i915->huc;
> + struct intel_guc *guc = &i915->gt.uc.guc;
> + struct intel_huc *huc = &i915->gt.uc.huc;
> int ret;
> if (!USES_GUC(i915))
> @@ -415,7 +415,7 @@ int intel_uc_init(struct drm_i915_private *i915)
> void intel_uc_fini(struct drm_i915_private *i915)
> {
> - struct intel_guc *guc = &i915->guc;
> + struct intel_guc *guc = &i915->gt.uc.guc;
> if (!USES_GUC(i915))
> return;
> @@ -426,15 +426,15 @@ void intel_uc_fini(struct drm_i915_private *i915)
> intel_guc_submission_fini(guc);
> if (USES_HUC(i915))
> - intel_huc_fini(&i915->huc);
> + intel_huc_fini(&i915->gt.uc.huc);
> intel_guc_fini(guc);
> }
> static void __uc_sanitize(struct drm_i915_private *i915)
> {
> - struct intel_guc *guc = &i915->guc;
> - struct intel_huc *huc = &i915->huc;
> + struct intel_guc *guc = &i915->gt.uc.guc;
> + struct intel_huc *huc = &i915->gt.uc.huc;
> GEM_BUG_ON(!intel_uc_fw_supported(&guc->fw));
> @@ -454,8 +454,8 @@ void intel_uc_sanitize(struct drm_i915_private *i915)
> int intel_uc_init_hw(struct drm_i915_private *i915)
> {
> - struct intel_guc *guc = &i915->guc;
> - struct intel_huc *huc = &i915->huc;
> + struct intel_guc *guc = &i915->gt.uc.guc;
> + struct intel_huc *huc = &i915->gt.uc.huc;
> int ret, attempts;
> if (!USES_GUC(i915))
> @@ -553,7 +553,7 @@ int intel_uc_init_hw(struct drm_i915_private *i915)
> void intel_uc_fini_hw(struct drm_i915_private *i915)
> {
> - struct intel_guc *guc = &i915->guc;
> + struct intel_guc *guc = &i915->gt.uc.guc;
> if (!intel_guc_is_loaded(guc))
> return;
> @@ -575,7 +575,7 @@ void intel_uc_fini_hw(struct drm_i915_private *i915)
> */
> void intel_uc_reset_prepare(struct drm_i915_private *i915)
> {
> - struct intel_guc *guc = &i915->guc;
> + struct intel_guc *guc = &i915->gt.uc.guc;
> if (!intel_guc_is_loaded(guc))
> return;
> @@ -586,7 +586,7 @@ void intel_uc_reset_prepare(struct drm_i915_private
> *i915)
> void intel_uc_runtime_suspend(struct drm_i915_private *i915)
> {
> - struct intel_guc *guc = &i915->guc;
> + struct intel_guc *guc = &i915->gt.uc.guc;
> int err;
> if (!intel_guc_is_loaded(guc))
> @@ -601,7 +601,7 @@ void intel_uc_runtime_suspend(struct
> drm_i915_private *i915)
> void intel_uc_suspend(struct drm_i915_private *i915)
> {
> - struct intel_guc *guc = &i915->guc;
> + struct intel_guc *guc = &i915->gt.uc.guc;
> intel_wakeref_t wakeref;
> if (!intel_guc_is_loaded(guc))
> @@ -613,7 +613,7 @@ void intel_uc_suspend(struct drm_i915_private *i915)
> int intel_uc_resume(struct drm_i915_private *i915)
> {
> - struct intel_guc *guc = &i915->guc;
> + struct intel_guc *guc = &i915->gt.uc.guc;
> int err;
> if (!intel_guc_is_loaded(guc))
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc.h
> b/drivers/gpu/drm/i915/gt/uc/intel_uc.h
> index 5a1383e192dd..a2fdc84afff2 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_uc.h
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_uc.h
> @@ -28,6 +28,11 @@
> #include "intel_huc.h"
> #include "i915_params.h"
> +struct intel_uc {
> + struct intel_guc guc;
> + struct intel_huc huc;
> +};
> +
> void intel_uc_init_early(struct drm_i915_private *dev_priv);
> void intel_uc_cleanup_early(struct drm_i915_private *dev_priv);
> void intel_uc_init_mmio(struct drm_i915_private *dev_priv);
> diff --git a/drivers/gpu/drm/i915/gt/uc/selftest_guc.c
> b/drivers/gpu/drm/i915/gt/uc/selftest_guc.c
> index 6ca76f5a98d4..93f7c930ab18 100644
> --- a/drivers/gpu/drm/i915/gt/uc/selftest_guc.c
> +++ b/drivers/gpu/drm/i915/gt/uc/selftest_guc.c
> @@ -138,7 +138,7 @@ static int igt_guc_clients(void *args)
> mutex_lock(&dev_priv->drm.struct_mutex);
> wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm);
> - guc = &dev_priv->guc;
> + guc = &dev_priv->gt.uc.guc;
> if (!guc) {
> pr_err("No guc object!\n");
> err = -EINVAL;
> @@ -230,7 +230,7 @@ static int igt_guc_doorbells(void *arg)
> mutex_lock(&dev_priv->drm.struct_mutex);
> wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm);
> - guc = &dev_priv->guc;
> + guc = &dev_priv->gt.uc.guc;
> if (!guc) {
> pr_err("No guc object!\n");
> err = -EINVAL;
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
> b/drivers/gpu/drm/i915/i915_debugfs.c
> index c00ccd736dea..f082d54b0b75 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -1885,7 +1885,7 @@ static int i915_huc_load_status_info(struct
> seq_file *m, void *data)
> return -ENODEV;
> p = drm_seq_file_printer(m);
> - intel_uc_fw_dump(&dev_priv->huc.fw, &p);
> + intel_uc_fw_dump(&dev_priv->gt.uc.huc.fw, &p);
> with_intel_runtime_pm(&dev_priv->runtime_pm, wakeref)
> seq_printf(m, "\nHuC status 0x%08x:\n", I915_READ(HUC_STATUS2));
> @@ -1903,7 +1903,7 @@ static int i915_guc_load_status_info(struct
> seq_file *m, void *data)
> return -ENODEV;
> p = drm_seq_file_printer(m);
> - intel_uc_fw_dump(&dev_priv->guc.fw, &p);
> + intel_uc_fw_dump(&dev_priv->gt.uc.guc.fw, &p);
> with_intel_runtime_pm(&dev_priv->runtime_pm, wakeref) {
> u32 tmp = I915_READ(GUC_STATUS);
> @@ -1946,7 +1946,7 @@ stringify_guc_log_type(enum guc_log_buffer_type
> type)
> static void i915_guc_log_info(struct seq_file *m,
> struct drm_i915_private *dev_priv)
> {
> - struct intel_guc_log *log = &dev_priv->guc.log;
> + struct intel_guc_log *log = &dev_priv->gt.uc.guc.log;
> enum guc_log_buffer_type type;
> if (!intel_guc_log_relay_enabled(log)) {
> @@ -1992,7 +1992,7 @@ static void i915_guc_client_info(struct seq_file
> *m,
> static int i915_guc_info(struct seq_file *m, void *data)
> {
> struct drm_i915_private *dev_priv = node_to_i915(m->private);
> - const struct intel_guc *guc = &dev_priv->guc;
> + const struct intel_guc *guc = &dev_priv->gt.uc.guc;
> if (!USES_GUC(dev_priv))
> return -ENODEV;
> @@ -2019,7 +2019,7 @@ static int i915_guc_info(struct seq_file *m, void
> *data)
> static int i915_guc_stage_pool(struct seq_file *m, void *data)
> {
> struct drm_i915_private *dev_priv = node_to_i915(m->private);
> - const struct intel_guc *guc = &dev_priv->guc;
> + const struct intel_guc *guc = &dev_priv->gt.uc.guc;
> struct guc_stage_desc *desc = guc->stage_desc_pool_vaddr;
> intel_engine_mask_t tmp;
> int index;
> @@ -2082,9 +2082,9 @@ static int i915_guc_log_dump(struct seq_file *m,
> void *data)
> return -ENODEV;
> if (dump_load_err)
> - obj = dev_priv->guc.load_err_log;
> - else if (dev_priv->guc.log.vma)
> - obj = dev_priv->guc.log.vma->obj;
> + obj = dev_priv->gt.uc.guc.load_err_log;
> + else if (dev_priv->gt.uc.guc.log.vma)
> + obj = dev_priv->gt.uc.guc.log.vma->obj;
> if (!obj)
> return 0;
> @@ -2115,7 +2115,7 @@ static int i915_guc_log_level_get(void *data, u64
> *val)
> if (!USES_GUC(dev_priv))
> return -ENODEV;
> - *val = intel_guc_log_get_level(&dev_priv->guc.log);
> + *val = intel_guc_log_get_level(&dev_priv->gt.uc.guc.log);
> return 0;
> }
> @@ -2127,7 +2127,7 @@ static int i915_guc_log_level_set(void *data, u64
> val)
> if (!USES_GUC(dev_priv))
> return -ENODEV;
> - return intel_guc_log_set_level(&dev_priv->guc.log, val);
> + return intel_guc_log_set_level(&dev_priv->gt.uc.guc.log, val);
> }
> DEFINE_SIMPLE_ATTRIBUTE(i915_guc_log_level_fops,
> @@ -2141,9 +2141,9 @@ static int i915_guc_log_relay_open(struct inode
> *inode, struct file *file)
> if (!USES_GUC(dev_priv))
> return -ENODEV;
> - file->private_data = &dev_priv->guc.log;
> + file->private_data = &dev_priv->gt.uc.guc.log;
> - return intel_guc_log_relay_open(&dev_priv->guc.log);
> + return intel_guc_log_relay_open(&dev_priv->gt.uc.guc.log);
> }
> static ssize_t
> @@ -2163,7 +2163,7 @@ static int i915_guc_log_relay_release(struct inode
> *inode, struct file *file)
> {
> struct drm_i915_private *dev_priv = inode->i_private;
> - intel_guc_log_relay_close(&dev_priv->guc.log);
> + intel_guc_log_relay_close(&dev_priv->gt.uc.guc.log);
> return 0;
> }
> diff --git a/drivers/gpu/drm/i915/i915_drv.c
> b/drivers/gpu/drm/i915/i915_drv.c
> index 4a8d90304e21..e7c89d320375 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -420,7 +420,7 @@ static int i915_getparam_ioctl(struct drm_device
> *dev, void *data,
> value = sseu->min_eu_in_pool;
> break;
> case I915_PARAM_HUC_STATUS:
> - value = intel_huc_check_status(&dev_priv->huc);
> + value = intel_huc_check_status(&dev_priv->gt.uc.huc);
> if (value < 0)
> return value;
> break;
> diff --git a/drivers/gpu/drm/i915/i915_drv.h
> b/drivers/gpu/drm/i915/i915_drv.h
> index b172d9ee3041..c4757cbf9a33 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1348,9 +1348,6 @@ struct drm_i915_private {
> struct intel_wopcm wopcm;
> - struct intel_huc huc;
> - struct intel_guc guc;
> -
> struct intel_csr csr;
> struct intel_gmbus gmbus[GMBUS_NUM_PINS];
> @@ -1907,12 +1904,12 @@ static inline struct drm_i915_private
> *wopcm_to_i915(struct intel_wopcm *wopcm)
> static inline struct drm_i915_private *guc_to_i915(struct intel_guc *guc)
> {
> - return container_of(guc, struct drm_i915_private, guc);
> + return container_of(guc, struct drm_i915_private, gt.uc.guc);
> }
> static inline struct drm_i915_private *huc_to_i915(struct intel_huc *huc)
> {
> - return container_of(huc, struct drm_i915_private, huc);
> + return container_of(huc, struct drm_i915_private, gt.uc.huc);
> }
> /* Simple iterator over all initialised engines */
> diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c
> b/drivers/gpu/drm/i915/i915_gpu_error.c
> index 5489cd879315..78e388fa059c 100644
> --- a/drivers/gpu/drm/i915/i915_gpu_error.c
> +++ b/drivers/gpu/drm/i915/i915_gpu_error.c
> @@ -1552,21 +1552,22 @@ static void capture_uc_state(struct
> i915_gpu_state *error)
> {
> struct drm_i915_private *i915 = error->i915;
> struct i915_error_uc *error_uc = &error->uc;
> + struct intel_uc *uc = &i915->gt.uc;
> /* Capturing uC state won't be useful if there is no GuC */
> if (!error->device_info.has_guc)
> return;
> - error_uc->guc_fw = i915->guc.fw;
> - error_uc->huc_fw = i915->huc.fw;
> + error_uc->guc_fw = uc->guc.fw;
> + error_uc->huc_fw = uc->huc.fw;
> /* Non-default firmware paths will be specified by the modparam.
> * As modparams are generally accesible from the userspace make
> * explicit copies of the firmware paths.
> */
> - error_uc->guc_fw.path = kstrdup(i915->guc.fw.path, GFP_ATOMIC);
> - error_uc->huc_fw.path = kstrdup(i915->huc.fw.path, GFP_ATOMIC);
> - error_uc->guc_log = i915_error_object_create(i915, i915->guc.log.vma);
> + error_uc->guc_fw.path = kstrdup(uc->guc.fw.path, GFP_ATOMIC);
> + error_uc->huc_fw.path = kstrdup(uc->huc.fw.path, GFP_ATOMIC);
> + error_uc->guc_log = i915_error_object_create(i915, uc->guc.log.vma);
> }
> /* Capture all registers which don't fit into another category. */
> diff --git a/drivers/gpu/drm/i915/i915_irq.c
> b/drivers/gpu/drm/i915/i915_irq.c
> index 42d6d8bfac70..78c748cb9df8 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -1655,7 +1655,7 @@ static void gen8_gt_irq_handler(struct
> drm_i915_private *i915,
> if (master_ctl & (GEN8_GT_PM_IRQ | GEN8_GT_GUC_IRQ)) {
> gen6_rps_irq_handler(i915, gt_iir[2]);
> - guc_irq_handler(&i915->guc, gt_iir[2] >> 16);
> + guc_irq_handler(&i915->gt.uc.guc, gt_iir[2] >> 16);
> }
> }
> @@ -3082,10 +3082,8 @@ static void
> gen11_other_irq_handler(struct intel_gt *gt, const u8 instance,
> const u16 iir)
> {
> - struct drm_i915_private *i915 = gt->i915;
> -
> if (instance == OTHER_GUC_INSTANCE)
> - return guc_irq_handler(&i915->guc, iir);
> + return guc_irq_handler(>->uc.guc, iir);
> if (instance == OTHER_GTPM_INSTANCE)
> return gen11_rps_irq_handler(gt, iir);
> diff --git a/drivers/gpu/drm/i915/intel_wopcm.c
> b/drivers/gpu/drm/i915/intel_wopcm.c
> index 8c850785e4b4..0c05c5e6c7be 100644
> --- a/drivers/gpu/drm/i915/intel_wopcm.c
> +++ b/drivers/gpu/drm/i915/intel_wopcm.c
> @@ -164,8 +164,8 @@ static inline int check_hw_restriction(struct
> drm_i915_private *i915,
> int intel_wopcm_init(struct intel_wopcm *wopcm)
> {
> struct drm_i915_private *i915 = wopcm_to_i915(wopcm);
> - u32 guc_fw_size = intel_uc_fw_get_upload_size(&i915->guc.fw);
> - u32 huc_fw_size = intel_uc_fw_get_upload_size(&i915->huc.fw);
> + u32 guc_fw_size = intel_uc_fw_get_upload_size(&i915->gt.uc.guc.fw);
> + u32 huc_fw_size = intel_uc_fw_get_upload_size(&i915->gt.uc.huc.fw);
> u32 ctx_rsvd = context_reserved_size(i915);
> u32 guc_wopcm_base;
> u32 guc_wopcm_size;
_______________________________________________
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Intel-gfx@lists.freedesktop.org
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^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH 09/12] drm/i915/uc: Move intel functions to intel_uc
2019-07-10 0:54 ` [PATCH 09/12] drm/i915/uc: Move intel functions to intel_uc Daniele Ceraolo Spurio
@ 2019-07-10 18:26 ` Michal Wajdeczko
0 siblings, 0 replies; 28+ messages in thread
From: Michal Wajdeczko @ 2019-07-10 18:26 UTC (permalink / raw)
To: intel-gfx, Daniele Ceraolo Spurio
On Wed, 10 Jul 2019 02:54:34 +0200, Daniele Ceraolo Spurio
<daniele.ceraolospurio@intel.com> wrote:
> All the intel_uc_* can now be moved to work on the intel_uc structure
> for better encapsulation of uc-related actions.
>
> Note: I've introduced uc_to_gt instead of uc_to_i915 because the aim is
> to move everything to be gt-focused in the medium term, so we would've
> had to replace it soon anyway.
>
> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
> ---
> drivers/gpu/drm/i915/gem/i915_gem_pm.c | 6 +-
> drivers/gpu/drm/i915/gt/intel_gt.h | 5 +
> drivers/gpu/drm/i915/gt/intel_reset.c | 2 +-
> drivers/gpu/drm/i915/gt/uc/intel_uc.c | 184 ++++++++++++-------------
> drivers/gpu/drm/i915/gt/uc/intel_uc.h | 34 ++---
> drivers/gpu/drm/i915/i915_drv.c | 14 +-
> drivers/gpu/drm/i915/i915_drv.h | 6 +-
> drivers/gpu/drm/i915/i915_gem.c | 18 +--
> 8 files changed, 137 insertions(+), 132 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_pm.c
> b/drivers/gpu/drm/i915/gem/i915_gem_pm.c
> index 4d774376f5b8..3c674c952a78 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_pm.c
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_pm.c
> @@ -173,7 +173,7 @@ void i915_gem_suspend(struct drm_i915_private *i915)
> i915_gem_drain_freed_objects(i915);
> - intel_uc_suspend(i915);
> + intel_uc_suspend(&i915->gt.uc);
> }
> static struct drm_i915_gem_object *first_mm_object(struct list_head
> *list)
> @@ -238,7 +238,7 @@ void i915_gem_suspend_late(struct drm_i915_private
> *i915)
> }
> spin_unlock_irqrestore(&i915->mm.obj_lock, flags);
> - intel_uc_sanitize(i915);
> + intel_uc_sanitize(&i915->gt.uc);
> i915_gem_sanitize(i915);
> }
> @@ -265,7 +265,7 @@ void i915_gem_resume(struct drm_i915_private *i915)
> if (intel_gt_resume(&i915->gt))
> goto err_wedged;
> - intel_uc_resume(i915);
> + intel_uc_resume(&i915->gt.uc);
> /* Always reload a context for powersaving. */
> if (!i915_gem_load_power_context(i915))
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt.h
> b/drivers/gpu/drm/i915/gt/intel_gt.h
> index 1093dcf36f63..880be05a3f4a 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt.h
> +++ b/drivers/gpu/drm/i915/gt/intel_gt.h
> @@ -11,6 +11,11 @@
> struct drm_i915_private;
> +static inline struct intel_gt *uc_to_gt(struct intel_uc *uc)
> +{
> + return container_of(uc, struct intel_gt, uc);
> +}
> +
> void intel_gt_init_early(struct intel_gt *gt, struct drm_i915_private
> *i915);
> void intel_gt_init_hw(struct drm_i915_private *i915);
> diff --git a/drivers/gpu/drm/i915/gt/intel_reset.c
> b/drivers/gpu/drm/i915/gt/intel_reset.c
> index ccedea636ba3..be23f4557111 100644
> --- a/drivers/gpu/drm/i915/gt/intel_reset.c
> +++ b/drivers/gpu/drm/i915/gt/intel_reset.c
> @@ -720,7 +720,7 @@ static intel_engine_mask_t reset_prepare(struct
> drm_i915_private *i915)
> reset_prepare_engine(engine);
> }
> - intel_uc_reset_prepare(i915);
> + intel_uc_reset_prepare(&i915->gt.uc);
> return awake;
> }
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc.c
> b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
> index e2080da2e1e4..2062e7ff05e8 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_uc.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
> @@ -22,19 +22,22 @@
> *
> */
> +#include "gt/intel_gt.h"
> #include "gt/intel_reset.h"
> -#include "intel_uc.h"
> #include "intel_guc.h"
we don't need this, it's included by "intel_uc.h"
> #include "intel_guc_ads.h"
> #include "intel_guc_submission.h"
> +#include "intel_uc.h"
> +
> #include "i915_drv.h"
> static void guc_free_load_err_log(struct intel_guc *guc);
> /* Reset GuC providing us with fresh state for both GuC and HuC.
> */
> -static int __intel_uc_reset_hw(struct drm_i915_private *dev_priv)
> +static int __intel_uc_reset_hw(struct intel_uc *uc)
> {
> + struct drm_i915_private *dev_priv = uc_to_gt(uc)->i915;
> int ret;
> u32 guc_status;
> @@ -52,10 +55,10 @@ static int __intel_uc_reset_hw(struct
> drm_i915_private *dev_priv)
> return ret;
> }
> -static int __get_platform_enable_guc(struct drm_i915_private *i915)
> +static int __get_platform_enable_guc(struct intel_uc *uc)
> {
> - struct intel_uc_fw *guc_fw = &i915->gt.uc.guc.fw;
> - struct intel_uc_fw *huc_fw = &i915->gt.uc.huc.fw;
> + struct intel_uc_fw *guc_fw = &uc->guc.fw;
> + struct intel_uc_fw *huc_fw = &uc->huc.fw;
> int enable_guc = 0;
> /* Default is to use HuC if we know GuC and HuC firmwares */
> @@ -67,12 +70,11 @@ static int __get_platform_enable_guc(struct
> drm_i915_private *i915)
> return enable_guc;
> }
> -static int __get_default_guc_log_level(struct drm_i915_private *i915)
> +static int __get_default_guc_log_level(struct intel_uc *uc)
> {
> int guc_log_level;
> - if (!intel_uc_fw_supported(&i915->gt.uc.guc.fw) ||
> - !intel_uc_is_using_guc(i915))
> + if (!intel_uc_fw_supported(&uc->guc.fw) || !intel_uc_is_using_guc(uc))
> guc_log_level = GUC_LOG_LEVEL_DISABLED;
> else if (IS_ENABLED(CONFIG_DRM_I915_DEBUG) ||
> IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM))
> @@ -87,7 +89,7 @@ static int __get_default_guc_log_level(struct
> drm_i915_private *i915)
> /**
> * sanitize_options_early - sanitize uC related modparam options
> - * @i915: device private
> + * @uc: the intel_uc structure
> *
> * In case of "enable_guc" option this function will attempt to modify
> * it only if it was initially set to "auto(-1)". Default value for this
> @@ -102,22 +104,22 @@ static int __get_default_guc_log_level(struct
> drm_i915_private *i915)
> * unless GuC is enabled on given platform and the driver is compiled
> with
> * debug config when this modparam will default to "enable(1..4)".
> */
> -static void sanitize_options_early(struct drm_i915_private *i915)
> +static void sanitize_options_early(struct intel_uc *uc)
> {
> - struct intel_uc_fw *guc_fw = &i915->gt.uc.guc.fw;
> - struct intel_uc_fw *huc_fw = &i915->gt.uc.huc.fw;
> + struct intel_uc_fw *guc_fw = &uc->guc.fw;
> + struct intel_uc_fw *huc_fw = &uc->huc.fw;
> /* A negative value means "use platform default" */
> if (i915_modparams.enable_guc < 0)
> - i915_modparams.enable_guc = __get_platform_enable_guc(i915);
> + i915_modparams.enable_guc = __get_platform_enable_guc(uc);
> DRM_DEBUG_DRIVER("enable_guc=%d (submission:%s huc:%s)\n",
> i915_modparams.enable_guc,
> - yesno(intel_uc_is_using_guc_submission(i915)),
> - yesno(intel_uc_is_using_huc(i915)));
> + yesno(intel_uc_is_using_guc_submission(uc)),
> + yesno(intel_uc_is_using_huc(uc)));
> /* Verify GuC firmware availability */
> - if (intel_uc_is_using_guc(i915) && !intel_uc_fw_is_selected(guc_fw)) {
> + if (intel_uc_is_using_guc(uc) && !intel_uc_fw_is_selected(guc_fw)) {
> DRM_WARN("Incompatible option detected: %s=%d, %s!\n",
> "enable_guc", i915_modparams.enable_guc,
> !intel_uc_fw_supported(guc_fw) ?
> @@ -125,7 +127,7 @@ static void sanitize_options_early(struct
> drm_i915_private *i915)
> }
> /* Verify HuC firmware availability */
> - if (intel_uc_is_using_huc(i915) && !intel_uc_fw_is_selected(huc_fw)) {
> + if (intel_uc_is_using_huc(uc) && !intel_uc_fw_is_selected(huc_fw)) {
> DRM_WARN("Incompatible option detected: %s=%d, %s!\n",
> "enable_guc", i915_modparams.enable_guc,
> !intel_uc_fw_supported(huc_fw) ?
> @@ -133,7 +135,7 @@ static void sanitize_options_early(struct
> drm_i915_private *i915)
> }
> /* XXX: GuC submission is unavailable for now */
> - if (intel_uc_is_using_guc_submission(i915)) {
> + if (intel_uc_is_using_guc_submission(uc)) {
> DRM_INFO("Incompatible option detected: %s=%d, %s!\n",
> "enable_guc", i915_modparams.enable_guc,
> "GuC submission not supported");
> @@ -144,9 +146,9 @@ static void sanitize_options_early(struct
> drm_i915_private *i915)
> /* A negative value means "use platform/config default" */
> if (i915_modparams.guc_log_level < 0)
> i915_modparams.guc_log_level =
> - __get_default_guc_log_level(i915);
> + __get_default_guc_log_level(uc);
> - if (i915_modparams.guc_log_level > 0 && !intel_uc_is_using_guc(i915)) {
> + if (i915_modparams.guc_log_level > 0 && !intel_uc_is_using_guc(uc)) {
> DRM_WARN("Incompatible option detected: %s=%d, %s!\n",
> "guc_log_level", i915_modparams.guc_log_level,
> !intel_uc_fw_supported(guc_fw) ?
> @@ -172,34 +174,29 @@ static void sanitize_options_early(struct
> drm_i915_private *i915)
> GEM_BUG_ON(i915_modparams.guc_log_level < 0);
> }
> -void intel_uc_init_early(struct drm_i915_private *i915)
> +void intel_uc_init_early(struct intel_uc *uc)
> {
> - struct intel_guc *guc = &i915->gt.uc.guc;
> - struct intel_huc *huc = &i915->gt.uc.huc;
> + intel_guc_init_early(&uc->guc);
> + intel_huc_init_early(&uc->huc);
> - intel_guc_init_early(guc);
> - intel_huc_init_early(huc);
> -
> - sanitize_options_early(i915);
> + sanitize_options_early(uc);
> }
> -void intel_uc_cleanup_early(struct drm_i915_private *i915)
> +void intel_uc_cleanup_early(struct intel_uc *uc)
> {
> - struct intel_guc *guc = &i915->gt.uc.guc;
> -
> - guc_free_load_err_log(guc);
> + guc_free_load_err_log(&uc->guc);
> }
> /**
> * intel_uc_init_mmio - setup uC MMIO access
> - * @i915: device private
> + * @uc: the intel_uc structure
> *
> * Setup minimal state necessary for MMIO accesses later in the
> * initialization sequence.
> */
> -void intel_uc_init_mmio(struct drm_i915_private *i915)
> +void intel_uc_init_mmio(struct intel_uc *uc)
> {
> - intel_guc_init_send_regs(&i915->gt.uc.guc);
> + intel_guc_init_send_regs(&uc->guc);
> }
> static void guc_capture_load_err_log(struct intel_guc *guc)
> @@ -346,54 +343,56 @@ static void guc_disable_communication(struct
> intel_guc *guc)
> DRM_INFO("GuC communication disabled\n");
> }
> -void intel_uc_fetch_firmwares(struct drm_i915_private *i915)
> +void intel_uc_fetch_firmwares(struct intel_uc *uc)
> {
> - if (!USES_GUC(i915))
> + struct drm_i915_private *i915 = uc_to_gt(uc)->i915;
> +
> + if (!intel_uc_is_using_guc(uc))
> return;
> - intel_uc_fw_fetch(i915, &i915->gt.uc.guc.fw);
> + intel_uc_fw_fetch(i915, &uc->guc.fw);
> - if (USES_HUC(i915))
> - intel_uc_fw_fetch(i915, &i915->gt.uc.huc.fw);
> + if (intel_uc_is_using_huc(uc))
> + intel_uc_fw_fetch(i915, &uc->huc.fw);
> }
> -void intel_uc_cleanup_firmwares(struct drm_i915_private *i915)
> +void intel_uc_cleanup_firmwares(struct intel_uc *uc)
> {
> - if (!USES_GUC(i915))
> + if (!intel_uc_is_using_guc(uc))
> return;
> - if (USES_HUC(i915))
> - intel_uc_fw_cleanup_fetch(&i915->gt.uc.huc.fw);
> + if (intel_uc_is_using_huc(uc))
> + intel_uc_fw_cleanup_fetch(&uc->huc.fw);
> - intel_uc_fw_cleanup_fetch(&i915->gt.uc.guc.fw);
> + intel_uc_fw_cleanup_fetch(&uc->guc.fw);
> }
> -int intel_uc_init(struct drm_i915_private *i915)
> +int intel_uc_init(struct intel_uc *uc)
> {
> - struct intel_guc *guc = &i915->gt.uc.guc;
> - struct intel_huc *huc = &i915->gt.uc.huc;
> + struct intel_guc *guc = &uc->guc;
> + struct intel_huc *huc = &uc->huc;
> int ret;
> - if (!USES_GUC(i915))
> + if (!intel_uc_is_using_guc(uc))
> return 0;
> if (!intel_uc_fw_supported(&guc->fw))
> return -ENODEV;
> /* XXX: GuC submission is unavailable for now */
> - GEM_BUG_ON(USES_GUC_SUBMISSION(i915));
> + GEM_BUG_ON(intel_uc_is_using_guc_submission(uc));
> ret = intel_guc_init(guc);
> if (ret)
> return ret;
> - if (USES_HUC(i915)) {
> + if (intel_uc_is_using_huc(uc)) {
> ret = intel_huc_init(huc);
> if (ret)
> goto err_guc;
> }
> - if (USES_GUC_SUBMISSION(i915)) {
> + if (intel_uc_is_using_guc_submission(uc)) {
> /*
> * This is stuff we need to have available at fw load time
> * if we are planning to enable submission later
> @@ -406,59 +405,60 @@ int intel_uc_init(struct drm_i915_private *i915)
> return 0;
> err_huc:
> - if (USES_HUC(i915))
> + if (intel_uc_is_using_huc(uc))
> intel_huc_fini(huc);
> err_guc:
> intel_guc_fini(guc);
> return ret;
> }
> -void intel_uc_fini(struct drm_i915_private *i915)
> +void intel_uc_fini(struct intel_uc *uc)
> {
> - struct intel_guc *guc = &i915->gt.uc.guc;
> + struct intel_guc *guc = &uc->guc;
> - if (!USES_GUC(i915))
> + if (!intel_uc_is_using_guc(uc))
> return;
> GEM_BUG_ON(!intel_uc_fw_supported(&guc->fw));
> - if (USES_GUC_SUBMISSION(i915))
> + if (intel_uc_is_using_guc_submission(uc))
> intel_guc_submission_fini(guc);
> - if (USES_HUC(i915))
> - intel_huc_fini(&i915->gt.uc.huc);
> + if (intel_uc_is_using_huc(uc))
> + intel_huc_fini(&uc->huc);
> intel_guc_fini(guc);
> }
> -static void __uc_sanitize(struct drm_i915_private *i915)
> +static void __uc_sanitize(struct intel_uc *uc)
> {
> - struct intel_guc *guc = &i915->gt.uc.guc;
> - struct intel_huc *huc = &i915->gt.uc.huc;
> + struct intel_guc *guc = &uc->guc;
> + struct intel_huc *huc = &uc->huc;
> GEM_BUG_ON(!intel_uc_fw_supported(&guc->fw));
> intel_huc_sanitize(huc);
> intel_guc_sanitize(guc);
> - __intel_uc_reset_hw(i915);
> + __intel_uc_reset_hw(uc);
> }
> -void intel_uc_sanitize(struct drm_i915_private *i915)
> +void intel_uc_sanitize(struct intel_uc *uc)
> {
> - if (!USES_GUC(i915))
> + if (!intel_uc_is_using_guc(uc))
> return;
> - __uc_sanitize(i915);
> + __uc_sanitize(uc);
> }
> -int intel_uc_init_hw(struct drm_i915_private *i915)
> +int intel_uc_init_hw(struct intel_uc *uc)
> {
> - struct intel_guc *guc = &i915->gt.uc.guc;
> - struct intel_huc *huc = &i915->gt.uc.huc;
> + struct drm_i915_private *i915 = uc_to_gt(uc)->i915;
> + struct intel_guc *guc = &uc->guc;
> + struct intel_huc *huc = &uc->huc;
> int ret, attempts;
> - if (!USES_GUC(i915))
> + if (!intel_uc_is_using_guc(uc))
> return 0;
> GEM_BUG_ON(!intel_uc_fw_supported(&guc->fw));
> @@ -477,11 +477,11 @@ int intel_uc_init_hw(struct drm_i915_private *i915)
> * Always reset the GuC just before (re)loading, so
> * that the state and timing are fairly predictable
> */
> - ret = __intel_uc_reset_hw(i915);
> + ret = __intel_uc_reset_hw(uc);
> if (ret)
> goto err_out;
> - if (USES_HUC(i915)) {
> + if (intel_uc_is_using_huc(uc)) {
> ret = intel_huc_fw_upload(huc);
> if (ret)
> goto err_out;
> @@ -505,7 +505,7 @@ int intel_uc_init_hw(struct drm_i915_private *i915)
> if (ret)
> goto err_log_capture;
> - if (USES_HUC(i915)) {
> + if (intel_uc_is_using_huc(uc)) {
> ret = intel_huc_auth(huc);
> if (ret)
> goto err_communication;
> @@ -515,7 +515,7 @@ int intel_uc_init_hw(struct drm_i915_private *i915)
> if (ret)
> goto err_communication;
> - if (USES_GUC_SUBMISSION(i915)) {
> + if (intel_uc_is_using_guc_submission(uc)) {
> ret = intel_guc_submission_enable(guc);
> if (ret)
> goto err_communication;
> @@ -524,9 +524,9 @@ int intel_uc_init_hw(struct drm_i915_private *i915)
> dev_info(i915->drm.dev, "GuC firmware version %u.%u\n",
> guc->fw.major_ver_found, guc->fw.minor_ver_found);
> dev_info(i915->drm.dev, "GuC submission %s\n",
> - enableddisabled(USES_GUC_SUBMISSION(i915)));
> + enableddisabled(intel_uc_is_using_guc_submission(uc)));
> dev_info(i915->drm.dev, "HuC %s\n",
> - enableddisabled(USES_HUC(i915)));
> + enableddisabled(intel_uc_is_using_huc(uc)));
> return 0;
> @@ -538,7 +538,7 @@ int intel_uc_init_hw(struct drm_i915_private *i915)
> err_log_capture:
> guc_capture_load_err_log(guc);
> err_out:
> - __uc_sanitize(i915);
> + __uc_sanitize(uc);
> /*
> * Note that there is no fallback as either user explicitly asked for
> @@ -551,42 +551,42 @@ int intel_uc_init_hw(struct drm_i915_private *i915)
> return ret;
> }
> -void intel_uc_fini_hw(struct drm_i915_private *i915)
> +void intel_uc_fini_hw(struct intel_uc *uc)
> {
> - struct intel_guc *guc = &i915->gt.uc.guc;
> + struct intel_guc *guc = &uc->guc;
> if (!intel_guc_is_loaded(guc))
> return;
> GEM_BUG_ON(!intel_uc_fw_supported(&guc->fw));
> - if (USES_GUC_SUBMISSION(i915))
> + if (intel_uc_is_using_guc_submission(uc))
> intel_guc_submission_disable(guc);
> guc_disable_communication(guc);
> - __uc_sanitize(i915);
> + __uc_sanitize(uc);
> }
> /**
> * intel_uc_reset_prepare - Prepare for reset
> - * @i915: device private
> + * @uc: the intel_uc structure
> *
> * Preparing for full gpu reset.
> */
> -void intel_uc_reset_prepare(struct drm_i915_private *i915)
> +void intel_uc_reset_prepare(struct intel_uc *uc)
> {
> - struct intel_guc *guc = &i915->gt.uc.guc;
> + struct intel_guc *guc = &uc->guc;
> if (!intel_guc_is_loaded(guc))
> return;
> guc_stop_communication(guc);
> - __uc_sanitize(i915);
> + __uc_sanitize(uc);
> }
> -void intel_uc_runtime_suspend(struct drm_i915_private *i915)
> +void intel_uc_runtime_suspend(struct intel_uc *uc)
> {
> - struct intel_guc *guc = &i915->gt.uc.guc;
> + struct intel_guc *guc = &uc->guc;
> int err;
> if (!intel_guc_is_loaded(guc))
> @@ -599,21 +599,21 @@ void intel_uc_runtime_suspend(struct
> drm_i915_private *i915)
> guc_disable_communication(guc);
> }
> -void intel_uc_suspend(struct drm_i915_private *i915)
> +void intel_uc_suspend(struct intel_uc *uc)
> {
> - struct intel_guc *guc = &i915->gt.uc.guc;
> + struct intel_guc *guc = &uc->guc;
> intel_wakeref_t wakeref;
> if (!intel_guc_is_loaded(guc))
> return;
> - with_intel_runtime_pm(&i915->runtime_pm, wakeref)
> - intel_uc_runtime_suspend(i915);
> + with_intel_runtime_pm(&uc_to_gt(uc)->i915->runtime_pm, wakeref)
> + intel_uc_runtime_suspend(uc);
> }
> -int intel_uc_resume(struct drm_i915_private *i915)
> +int intel_uc_resume(struct intel_uc *uc)
> {
> - struct intel_guc *guc = &i915->gt.uc.guc;
> + struct intel_guc *guc = &uc->guc;
> int err;
> if (!intel_guc_is_loaded(guc))
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc.h
> b/drivers/gpu/drm/i915/gt/uc/intel_uc.h
> index a2fdc84afff2..fe3362fd7706 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_uc.h
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_uc.h
> @@ -33,34 +33,34 @@ struct intel_uc {
> struct intel_huc huc;
> };
> -void intel_uc_init_early(struct drm_i915_private *dev_priv);
> -void intel_uc_cleanup_early(struct drm_i915_private *dev_priv);
> -void intel_uc_init_mmio(struct drm_i915_private *dev_priv);
> -void intel_uc_fetch_firmwares(struct drm_i915_private *dev_priv);
> -void intel_uc_cleanup_firmwares(struct drm_i915_private *dev_priv);
> -void intel_uc_sanitize(struct drm_i915_private *dev_priv);
> -int intel_uc_init_hw(struct drm_i915_private *dev_priv);
> -void intel_uc_fini_hw(struct drm_i915_private *dev_priv);
> -int intel_uc_init(struct drm_i915_private *dev_priv);
> -void intel_uc_fini(struct drm_i915_private *dev_priv);
> -void intel_uc_reset_prepare(struct drm_i915_private *i915);
> -void intel_uc_suspend(struct drm_i915_private *i915);
> -void intel_uc_runtime_suspend(struct drm_i915_private *i915);
> -int intel_uc_resume(struct drm_i915_private *dev_priv);
> +void intel_uc_init_early(struct intel_uc *uc);
> +void intel_uc_cleanup_early(struct intel_uc *uc);
> +void intel_uc_init_mmio(struct intel_uc *uc);
> +void intel_uc_fetch_firmwares(struct intel_uc *uc);
> +void intel_uc_cleanup_firmwares(struct intel_uc *uc);
> +void intel_uc_sanitize(struct intel_uc *uc);
> +int intel_uc_init_hw(struct intel_uc *uc);
> +void intel_uc_fini_hw(struct intel_uc *uc);
> +int intel_uc_init(struct intel_uc *uc);
> +void intel_uc_fini(struct intel_uc *uc);
> +void intel_uc_reset_prepare(struct intel_uc *uc);
> +void intel_uc_suspend(struct intel_uc *uc);
> +void intel_uc_runtime_suspend(struct intel_uc *uc);
> +int intel_uc_resume(struct intel_uc *uc);
> -static inline bool intel_uc_is_using_guc(struct drm_i915_private *i915)
> +static inline bool intel_uc_is_using_guc(struct intel_uc *uc)
> {
> GEM_BUG_ON(i915_modparams.enable_guc < 0);
> return i915_modparams.enable_guc > 0;
> }
> -static inline bool intel_uc_is_using_guc_submission(struct
> drm_i915_private *i915)
> +static inline bool intel_uc_is_using_guc_submission(struct intel_uc *uc)
> {
> GEM_BUG_ON(i915_modparams.enable_guc < 0);
> return i915_modparams.enable_guc & ENABLE_GUC_SUBMISSION;
> }
> -static inline bool intel_uc_is_using_huc(struct drm_i915_private *i915)
> +static inline bool intel_uc_is_using_huc(struct intel_uc *uc)
> {
> GEM_BUG_ON(i915_modparams.enable_guc < 0);
> return i915_modparams.enable_guc & ENABLE_GUC_LOAD_HUC;
> diff --git a/drivers/gpu/drm/i915/i915_drv.c
> b/drivers/gpu/drm/i915/i915_drv.c
> index e7c89d320375..f594e74f097d 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -934,7 +934,7 @@ static int i915_driver_init_early(struct
> drm_i915_private *dev_priv)
> intel_detect_pch(dev_priv);
> intel_wopcm_init_early(&dev_priv->wopcm);
> - intel_uc_init_early(dev_priv);
> + intel_uc_init_early(&dev_priv->gt.uc);
> intel_pm_setup(dev_priv);
> intel_init_dpio(dev_priv);
> ret = intel_power_domains_init(dev_priv);
> @@ -952,7 +952,7 @@ static int i915_driver_init_early(struct
> drm_i915_private *dev_priv)
> return 0;
> err_uc:
> - intel_uc_cleanup_early(dev_priv);
> + intel_uc_cleanup_early(&dev_priv->gt.uc);
> i915_gem_cleanup_early(dev_priv);
> err_workqueues:
> i915_workqueues_cleanup(dev_priv);
> @@ -969,7 +969,7 @@ static void i915_driver_cleanup_early(struct
> drm_i915_private *dev_priv)
> {
> intel_irq_fini(dev_priv);
> intel_power_domains_cleanup(dev_priv);
> - intel_uc_cleanup_early(dev_priv);
> + intel_uc_cleanup_early(&dev_priv->gt.uc);
> i915_gem_cleanup_early(dev_priv);
> i915_workqueues_cleanup(dev_priv);
> i915_engines_cleanup(dev_priv);
> @@ -1008,7 +1008,7 @@ static int i915_driver_init_mmio(struct
> drm_i915_private *dev_priv)
> intel_uncore_prune_mmio_domains(&dev_priv->uncore);
> - intel_uc_init_mmio(dev_priv);
> + intel_uc_init_mmio(&dev_priv->gt.uc);
> ret = intel_engines_init_mmio(dev_priv);
> if (ret)
> @@ -2933,7 +2933,7 @@ static int intel_runtime_suspend(struct device
> *kdev)
> */
> i915_gem_runtime_suspend(dev_priv);
> - intel_uc_runtime_suspend(dev_priv);
> + intel_uc_runtime_suspend(&dev_priv->gt.uc);
> intel_runtime_pm_disable_interrupts(dev_priv);
> @@ -2958,7 +2958,7 @@ static int intel_runtime_suspend(struct device
> *kdev)
> intel_runtime_pm_enable_interrupts(dev_priv);
> - intel_uc_resume(dev_priv);
> + intel_uc_resume(&dev_priv->gt.uc);
> intel_gt_init_swizzling(&dev_priv->gt);
> i915_gem_restore_fences(dev_priv);
> @@ -3056,7 +3056,7 @@ static int intel_runtime_resume(struct device
> *kdev)
> intel_runtime_pm_enable_interrupts(dev_priv);
> - intel_uc_resume(dev_priv);
> + intel_uc_resume(&dev_priv->gt.uc);
> /*
> * No point of rolling back things in case of an error, as the best
> diff --git a/drivers/gpu/drm/i915/i915_drv.h
> b/drivers/gpu/drm/i915/i915_drv.h
> index c4757cbf9a33..99004c8b833f 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -2293,9 +2293,9 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
> #define HAS_HUC_UCODE(dev_priv) (HAS_GUC(dev_priv))
> /* Having a GuC is not the same as using a GuC */
> -#define USES_GUC(dev_priv) intel_uc_is_using_guc(dev_priv)
> -#define
> USES_GUC_SUBMISSION(dev_priv) intel_uc_is_using_guc_submission(dev_priv)
> -#define USES_HUC(dev_priv) intel_uc_is_using_huc(dev_priv)
> +#define USES_GUC(dev_priv) intel_uc_is_using_guc(&(dev_priv)->gt.uc)
> +#define
> USES_GUC_SUBMISSION(dev_priv) intel_uc_is_using_guc_submission(&(dev_priv)->gt.uc)
> +#define USES_HUC(dev_priv) intel_uc_is_using_huc(&(dev_priv)->gt.uc)
> #define HAS_POOLED_EU(dev_priv) (INTEL_INFO(dev_priv)->has_pooled_eu)
> diff --git a/drivers/gpu/drm/i915/i915_gem.c
> b/drivers/gpu/drm/i915/i915_gem.c
> index e6e8e4d5ebb1..b792e85b8c2b 100644
> --- a/drivers/gpu/drm/i915/i915_gem.c
> +++ b/drivers/gpu/drm/i915/i915_gem.c
> @@ -1248,7 +1248,7 @@ int i915_gem_init_hw(struct drm_i915_private *i915)
> }
> /* We can't enable contexts until all firmware is loaded */
> - ret = intel_uc_init_hw(i915);
> + ret = intel_uc_init_hw(&i915->gt.uc);
> if (ret) {
> DRM_ERROR("Enabling uc failed (%d)\n", ret);
> goto out;
> @@ -1433,7 +1433,7 @@ int i915_gem_init(struct drm_i915_private
> *dev_priv)
> if (ret)
> return ret;
> - intel_uc_fetch_firmwares(dev_priv);
> + intel_uc_fetch_firmwares(&dev_priv->gt.uc);
> ret = intel_wopcm_init(&dev_priv->wopcm);
> if (ret)
> @@ -1481,7 +1481,7 @@ int i915_gem_init(struct drm_i915_private
> *dev_priv)
> intel_init_gt_powersave(dev_priv);
> - ret = intel_uc_init(dev_priv);
> + ret = intel_uc_init(&dev_priv->gt.uc);
> if (ret)
> goto err_pm;
> @@ -1545,9 +1545,9 @@ int i915_gem_init(struct drm_i915_private
> *dev_priv)
> mutex_lock(&dev_priv->drm.struct_mutex);
> err_init_hw:
> - intel_uc_fini_hw(dev_priv);
> + intel_uc_fini_hw(&dev_priv->gt.uc);
> err_uc_init:
> - intel_uc_fini(dev_priv);
> + intel_uc_fini(&dev_priv->gt.uc);
> err_pm:
> if (ret != -EIO) {
> intel_cleanup_gt_powersave(dev_priv);
> @@ -1564,7 +1564,7 @@ int i915_gem_init(struct drm_i915_private
> *dev_priv)
> mutex_unlock(&dev_priv->drm.struct_mutex);
> err_uc_fw:
> - intel_uc_cleanup_firmwares(dev_priv);
> + intel_uc_cleanup_firmwares(&dev_priv->gt.uc);
> if (ret != -EIO) {
> i915_gem_cleanup_userptr(dev_priv);
> @@ -1611,8 +1611,8 @@ void i915_gem_fini_hw(struct drm_i915_private
> *dev_priv)
> i915_gem_drain_workqueue(dev_priv);
> mutex_lock(&dev_priv->drm.struct_mutex);
> - intel_uc_fini_hw(dev_priv);
> - intel_uc_fini(dev_priv);
> + intel_uc_fini_hw(&dev_priv->gt.uc);
> + intel_uc_fini(&dev_priv->gt.uc);
> mutex_unlock(&dev_priv->drm.struct_mutex);
> i915_gem_drain_freed_objects(dev_priv);
> @@ -1630,7 +1630,7 @@ void i915_gem_fini(struct drm_i915_private
> *dev_priv)
> intel_cleanup_gt_powersave(dev_priv);
> - intel_uc_cleanup_firmwares(dev_priv);
> + intel_uc_cleanup_firmwares(&dev_priv->gt.uc);
> i915_gem_cleanup_userptr(dev_priv);
> intel_timelines_fini(dev_priv);
>
patch will likely be further simplified after applying nits to 8/12,
but in the meantime
Acked-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH 10/12] drm/i915/uc: prefer intel_gt over i915 in GuC/HuC paths
2019-07-10 0:54 ` [PATCH 10/12] drm/i915/uc: prefer intel_gt over i915 in GuC/HuC paths Daniele Ceraolo Spurio
@ 2019-07-10 18:35 ` Michal Wajdeczko
0 siblings, 0 replies; 28+ messages in thread
From: Michal Wajdeczko @ 2019-07-10 18:35 UTC (permalink / raw)
To: intel-gfx, Daniele Ceraolo Spurio
On Wed, 10 Jul 2019 02:54:35 +0200, Daniele Ceraolo Spurio
<daniele.ceraolospurio@intel.com> wrote:
> With our HW interface logic moving from i915 to gt and with GuC and HuC
> being part of the gt HW, it makes sense to use the intel_gt structure
> instead of i915 as our reference object in GuC/HuC paths.
>
> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
> ---
> drivers/gpu/drm/i915/gt/intel_gt.h | 10 +++
> drivers/gpu/drm/i915/gt/uc/intel_guc.c | 52 ++++++------
> drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c | 81 ++++++++++---------
> .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 43 +++++-----
> drivers/gpu/drm/i915/gt/uc/intel_huc.c | 22 ++---
> drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c | 4 +-
> drivers/gpu/drm/i915/gt/uc/intel_uc.c | 4 +-
> drivers/gpu/drm/i915/i915_gem_gtt.c | 8 +-
> drivers/gpu/drm/i915/i915_gem_gtt.h | 4 +-
> 9 files changed, 120 insertions(+), 108 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt.h
> b/drivers/gpu/drm/i915/gt/intel_gt.h
> index 880be05a3f4a..e182509d44ba 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt.h
> +++ b/drivers/gpu/drm/i915/gt/intel_gt.h
> @@ -16,6 +16,16 @@ static inline struct intel_gt *uc_to_gt(struct
> intel_uc *uc)
> return container_of(uc, struct intel_gt, uc);
> }
> +static inline struct intel_gt *guc_to_gt(struct intel_guc *guc)
> +{
> + return container_of(guc, struct intel_gt, uc.guc);
> +}
> +
> +static inline struct intel_gt *huc_to_gt(struct intel_huc *huc)
> +{
> + return container_of(huc, struct intel_gt, uc.huc);
> +}
> +
> void intel_gt_init_early(struct intel_gt *gt, struct drm_i915_private
> *i915);
> void intel_gt_init_hw(struct drm_i915_private *i915);
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
> b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
> index 4173b35bf104..6b56f39072b1 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
> @@ -22,6 +22,7 @@
> *
> */
> +#include "gt/intel_gt.h"
> #include "intel_guc.h"
> #include "intel_guc_ads.h"
> #include "intel_guc_submission.h"
> @@ -29,16 +30,16 @@
> static void gen8_guc_raise_irq(struct intel_guc *guc)
> {
> - struct drm_i915_private *dev_priv = guc_to_i915(guc);
> + struct intel_gt *gt = guc_to_gt(guc);
> - I915_WRITE(GUC_SEND_INTERRUPT, GUC_SEND_TRIGGER);
> + intel_uncore_write(gt->uncore, GUC_SEND_INTERRUPT, GUC_SEND_TRIGGER);
> }
> static void gen11_guc_raise_irq(struct intel_guc *guc)
> {
> - struct drm_i915_private *dev_priv = guc_to_i915(guc);
> + struct intel_gt *gt = guc_to_gt(guc);
> - I915_WRITE(GEN11_GUC_HOST_INTERRUPT, 0);
> + intel_uncore_write(gt->uncore, GEN11_GUC_HOST_INTERRUPT, 0);
> }
> static inline i915_reg_t guc_send_reg(struct intel_guc *guc, u32 i)
> @@ -52,11 +53,11 @@ static inline i915_reg_t guc_send_reg(struct
> intel_guc *guc, u32 i)
> void intel_guc_init_send_regs(struct intel_guc *guc)
> {
> - struct drm_i915_private *dev_priv = guc_to_i915(guc);
> + struct intel_gt *gt = guc_to_gt(guc);
> enum forcewake_domains fw_domains = 0;
> unsigned int i;
> - if (INTEL_GEN(dev_priv) >= 11) {
> + if (INTEL_GEN(gt->i915) >= 11) {
> guc->send_regs.base =
> i915_mmio_reg_offset(GEN11_SOFT_SCRATCH(0));
> guc->send_regs.count = GEN11_SOFT_SCRATCH_COUNT;
> @@ -67,7 +68,7 @@ void intel_guc_init_send_regs(struct intel_guc *guc)
> }
> for (i = 0; i < guc->send_regs.count; i++) {
> - fw_domains |= intel_uncore_forcewake_for_reg(&dev_priv->uncore,
> + fw_domains |= intel_uncore_forcewake_for_reg(gt->uncore,
> guc_send_reg(guc, i),
> FW_REG_READ | FW_REG_WRITE);
> }
> @@ -127,7 +128,7 @@ static void guc_shared_data_destroy(struct intel_guc
> *guc)
> int intel_guc_init(struct intel_guc *guc)
> {
> - struct drm_i915_private *dev_priv = guc_to_i915(guc);
> + struct intel_gt *gt = guc_to_gt(guc);
> int ret;
> ret = intel_uc_fw_init(&guc->fw);
> @@ -153,7 +154,7 @@ int intel_guc_init(struct intel_guc *guc)
> goto err_ads;
> /* We need to notify the guc whenever we change the GGTT */
> - i915_ggtt_enable_guc(dev_priv);
> + i915_ggtt_enable_guc(gt->ggtt);
> return 0;
> @@ -172,9 +173,9 @@ int intel_guc_init(struct intel_guc *guc)
> void intel_guc_fini(struct intel_guc *guc)
> {
> - struct drm_i915_private *dev_priv = guc_to_i915(guc);
> + struct intel_gt *gt = guc_to_gt(guc);
> - i915_ggtt_disable_guc(dev_priv);
> + i915_ggtt_disable_guc(gt->ggtt);
> intel_guc_ct_fini(&guc->ct);
> @@ -282,7 +283,7 @@ static u32 guc_ctl_ads_flags(struct intel_guc *guc)
> */
> void intel_guc_init_params(struct intel_guc *guc)
> {
> - struct drm_i915_private *dev_priv = guc_to_i915(guc);
> + struct intel_uncore *uncore = guc_to_gt(guc)->uncore;
> u32 params[GUC_CTL_MAX_DWORDS];
> int i;
> @@ -302,14 +303,14 @@ void intel_guc_init_params(struct intel_guc *guc)
> * they are power context saved so it's ok to release forcewake
> * when we are done here and take it again at xfer time.
> */
> - intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_BLITTER);
> + intel_uncore_forcewake_get(uncore, FORCEWAKE_BLITTER);
> - I915_WRITE(SOFT_SCRATCH(0), 0);
> + intel_uncore_write(uncore, SOFT_SCRATCH(0), 0);
> for (i = 0; i < GUC_CTL_MAX_DWORDS; i++)
> - I915_WRITE(SOFT_SCRATCH(1 + i), params[i]);
> + intel_uncore_write(uncore, SOFT_SCRATCH(1 + i), params[i]);
> - intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_BLITTER);
> + intel_uncore_forcewake_put(uncore, FORCEWAKE_BLITTER);
> }
> int intel_guc_send_nop(struct intel_guc *guc, const u32 *action, u32 len,
> @@ -330,8 +331,7 @@ void intel_guc_to_host_event_handler_nop(struct
> intel_guc *guc)
> int intel_guc_send_mmio(struct intel_guc *guc, const u32 *action, u32
> len,
> u32 *response_buf, u32 response_buf_size)
> {
> - struct drm_i915_private *dev_priv = guc_to_i915(guc);
> - struct intel_uncore *uncore = &dev_priv->uncore;
> + struct intel_uncore *uncore = guc_to_gt(guc)->uncore;
> u32 status;
> int i;
> int ret;
> @@ -380,7 +380,8 @@ int intel_guc_send_mmio(struct intel_guc *guc, const
> u32 *action, u32 len,
> int count = min(response_buf_size, guc->send_regs.count - 1);
> for (i = 0; i < count; i++)
> - response_buf[i] = I915_READ(guc_send_reg(guc, i + 1));
> + response_buf[i] = intel_uncore_read(uncore,
> + guc_send_reg(guc, i + 1));
> }
> /* Use data from the GuC response as our return value */
> @@ -454,7 +455,7 @@ int intel_guc_auth_huc(struct intel_guc *guc, u32
> rsa_offset)
> */
> int intel_guc_suspend(struct intel_guc *guc)
> {
> - struct drm_i915_private *dev_priv = guc_to_i915(guc);
> + struct intel_uncore *uncore = guc_to_gt(guc)->uncore;
> int ret;
> u32 status;
> u32 action[] = {
> @@ -472,13 +473,14 @@ int intel_guc_suspend(struct intel_guc *guc)
> * in progress so we need to take care of that ourselves as well.
> */
> - I915_WRITE(SOFT_SCRATCH(14), INTEL_GUC_SLEEP_STATE_INVALID_MASK);
> + intel_uncore_write(uncore, SOFT_SCRATCH(14),
> + INTEL_GUC_SLEEP_STATE_INVALID_MASK);
> ret = intel_guc_send(guc, action, ARRAY_SIZE(action));
> if (ret)
> return ret;
> - ret = __intel_wait_for_register(&dev_priv->uncore, SOFT_SCRATCH(14),
> + ret = __intel_wait_for_register(uncore, SOFT_SCRATCH(14),
> INTEL_GUC_SLEEP_STATE_INVALID_MASK,
> 0, 0, 10, &status);
> if (ret)
> @@ -574,17 +576,17 @@ int intel_guc_resume(struct intel_guc *guc)
> */
> struct i915_vma *intel_guc_allocate_vma(struct intel_guc *guc, u32 size)
> {
> - struct drm_i915_private *dev_priv = guc_to_i915(guc);
> + struct intel_gt *gt = guc_to_gt(guc);
> struct drm_i915_gem_object *obj;
> struct i915_vma *vma;
> u64 flags;
> int ret;
> - obj = i915_gem_object_create_shmem(dev_priv, size);
> + obj = i915_gem_object_create_shmem(gt->i915, size);
> if (IS_ERR(obj))
> return ERR_CAST(obj);
> - vma = i915_vma_instance(obj, &dev_priv->ggtt.vm, NULL);
> + vma = i915_vma_instance(obj, >->ggtt->vm, NULL);
> if (IS_ERR(vma))
> goto err;
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c
> b/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c
> index ee95d4960c5c..98305e3fd42c 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c
> @@ -27,6 +27,7 @@
> * Alex Dai <yu.dai@intel.com>
> */
> +#include "gt/intel_gt.h"
> #include "intel_guc_fw.h"
> #include "i915_drv.h"
> @@ -129,35 +130,37 @@ void intel_guc_fw_init_early(struct intel_guc *guc)
> static void guc_prepare_xfer(struct intel_guc *guc)
> {
> - struct drm_i915_private *dev_priv = guc_to_i915(guc);
> + struct intel_gt *gt = guc_to_gt(guc);
> + struct intel_uncore *uncore = gt->uncore;
> + u32 shim_flags = GUC_DISABLE_SRAM_INIT_TO_ZEROES |
> + GUC_ENABLE_READ_CACHE_LOGIC |
> + GUC_ENABLE_MIA_CACHING |
> + GUC_ENABLE_READ_CACHE_FOR_SRAM_DATA |
> + GUC_ENABLE_READ_CACHE_FOR_WOPCM_DATA |
> + GUC_ENABLE_MIA_CLOCK_GATING;
> /* Must program this register before loading the ucode with DMA */
> - I915_WRITE(GUC_SHIM_CONTROL, GUC_DISABLE_SRAM_INIT_TO_ZEROES |
> - GUC_ENABLE_READ_CACHE_LOGIC |
> - GUC_ENABLE_MIA_CACHING |
> - GUC_ENABLE_READ_CACHE_FOR_SRAM_DATA |
> - GUC_ENABLE_READ_CACHE_FOR_WOPCM_DATA |
> - GUC_ENABLE_MIA_CLOCK_GATING);
> -
> - if (IS_GEN9_LP(dev_priv))
> - I915_WRITE(GEN9LP_GT_PM_CONFIG, GT_DOORBELL_ENABLE);
> + intel_uncore_write(uncore, GUC_SHIM_CONTROL, shim_flags);
> +
> + if (IS_GEN9_LP(gt->i915))
> + intel_uncore_write(uncore, GEN9LP_GT_PM_CONFIG, GT_DOORBELL_ENABLE);
> else
> - I915_WRITE(GEN9_GT_PM_CONFIG, GT_DOORBELL_ENABLE);
> + intel_uncore_write(uncore, GEN9_GT_PM_CONFIG, GT_DOORBELL_ENABLE);
> - if (IS_GEN(dev_priv, 9)) {
> + if (IS_GEN(gt->i915, 9)) {
> /* DOP Clock Gating Enable for GuC clocks */
> - I915_WRITE(GEN7_MISCCPCTL, (GEN8_DOP_CLOCK_GATE_GUC_ENABLE |
> - I915_READ(GEN7_MISCCPCTL)));
> + intel_uncore_rmw(uncore, GEN7_MISCCPCTL,
> + 0, GEN8_DOP_CLOCK_GATE_GUC_ENABLE);
> /* allows for 5us (in 10ns units) before GT can go to RC6 */
> - I915_WRITE(GUC_ARAT_C6DIS, 0x1FF);
> + intel_uncore_write(uncore, GUC_ARAT_C6DIS, 0x1FF);
> }
> }
> /* Copy RSA signature from the fw image to HW for verification */
> static void guc_xfer_rsa(struct intel_guc *guc)
> {
> - struct drm_i915_private *dev_priv = guc_to_i915(guc);
> + struct intel_uncore *uncore = guc_to_gt(guc)->uncore;
> struct intel_uc_fw *fw = &guc->fw;
> struct sg_table *pages = fw->obj->mm.pages;
> u32 rsa[UOS_RSA_SCRATCH_COUNT];
> @@ -167,15 +170,13 @@ static void guc_xfer_rsa(struct intel_guc *guc)
> rsa, sizeof(rsa), fw->rsa_offset);
> for (i = 0; i < UOS_RSA_SCRATCH_COUNT; i++)
> - I915_WRITE(UOS_RSA_SCRATCH(i), rsa[i]);
> + intel_uncore_write(uncore, UOS_RSA_SCRATCH(i), rsa[i]);
> }
> -static bool guc_xfer_completed(struct intel_guc *guc, u32 *status)
> +static bool guc_xfer_completed(struct intel_uncore *uncore, u32 *status)
> {
> - struct drm_i915_private *dev_priv = guc_to_i915(guc);
> -
> /* Did we complete the xfer? */
> - *status = I915_READ(DMA_CTRL);
> + *status = intel_uncore_read(uncore, DMA_CTRL);
> return !(*status & START_DMA);
> }
> @@ -188,10 +189,9 @@ static bool guc_xfer_completed(struct intel_guc
> *guc, u32 *status)
> * This is used for polling the GuC status in a wait_for()
> * loop below.
> */
> -static inline bool guc_ready(struct intel_guc *guc, u32 *status)
> +static inline bool guc_ready(struct intel_uncore *uncore, u32 *status)
> {
> - struct drm_i915_private *dev_priv = guc_to_i915(guc);
> - u32 val = I915_READ(GUC_STATUS);
> + u32 val = intel_uncore_read(uncore, GUC_STATUS);
> u32 uk_val = val & GS_UKERNEL_MASK;
> *status = val;
> @@ -199,9 +199,8 @@ static inline bool guc_ready(struct intel_guc *guc,
> u32 *status)
> ((val & GS_MIA_CORE_STATE) && (uk_val == GS_UKERNEL_LAPIC_DONE));
> }
> -static int guc_wait_ucode(struct intel_guc *guc)
> +static int guc_wait_ucode(struct intel_uncore *uncore)
> {
> - struct drm_i915_private *i915 = guc_to_i915(guc);
> u32 status;
> int ret;
> @@ -213,7 +212,7 @@ static int guc_wait_ucode(struct intel_guc *guc)
> * (Higher levels of the driver may decide to reset the GuC and
> * attempt the ucode load again if this happens.)
> */
> - ret = wait_for(guc_ready(guc, &status), 100);
> + ret = wait_for(guc_ready(uncore, &status), 100);
> DRM_DEBUG_DRIVER("GuC status %#x\n", status);
> if ((status & GS_BOOTROM_MASK) == GS_BOOTROM_RSA_FAILED) {
> @@ -223,11 +222,11 @@ static int guc_wait_ucode(struct intel_guc *guc)
> if ((status & GS_UKERNEL_MASK) == GS_UKERNEL_EXCEPTION) {
> DRM_ERROR("GuC firmware exception. EIP: %#x\n",
> - intel_uncore_read(&i915->uncore, SOFT_SCRATCH(13)));
> + intel_uncore_read(uncore, SOFT_SCRATCH(13)));
> ret = -ENXIO;
> }
> - if (ret == 0 && !guc_xfer_completed(guc, &status)) {
> + if (ret == 0 && !guc_xfer_completed(uncore, &status)) {
> DRM_ERROR("GuC is ready, but the xfer %08x is incomplete\n",
> status);
> ret = -ENXIO;
> @@ -245,7 +244,7 @@ static int guc_wait_ucode(struct intel_guc *guc)
> */
> static int guc_xfer_ucode(struct intel_guc *guc)
> {
> - struct drm_i915_private *dev_priv = guc_to_i915(guc);
> + struct intel_uncore *uncore = guc_to_gt(guc)->uncore;
> struct intel_uc_fw *guc_fw = &guc->fw;
> unsigned long offset;
> @@ -253,24 +252,26 @@ static int guc_xfer_ucode(struct intel_guc *guc)
> * The header plus uCode will be copied to WOPCM via DMA, excluding any
> * other components
> */
> - I915_WRITE(DMA_COPY_SIZE, guc_fw->header_size + guc_fw->ucode_size);
> + intel_uncore_write(uncore, DMA_COPY_SIZE,
> + guc_fw->header_size + guc_fw->ucode_size);
> /* Set the source address for the new blob */
> offset = intel_uc_fw_ggtt_offset(guc_fw) + guc_fw->header_offset;
> - I915_WRITE(DMA_ADDR_0_LOW, lower_32_bits(offset));
> - I915_WRITE(DMA_ADDR_0_HIGH, upper_32_bits(offset) & 0xFFFF);
> + intel_uncore_write(uncore, DMA_ADDR_0_LOW, lower_32_bits(offset));
> + intel_uncore_write(uncore, DMA_ADDR_0_HIGH, upper_32_bits(offset) &
> 0xFFFF);
> /*
> * Set the DMA destination. Current uCode expects the code to be
> * loaded at 8k; locations below this are used for the stack.
> */
> - I915_WRITE(DMA_ADDR_1_LOW, 0x2000);
> - I915_WRITE(DMA_ADDR_1_HIGH, DMA_ADDRESS_SPACE_WOPCM);
> + intel_uncore_write(uncore, DMA_ADDR_1_LOW, 0x2000);
> + intel_uncore_write(uncore, DMA_ADDR_1_HIGH, DMA_ADDRESS_SPACE_WOPCM);
> /* Finally start the DMA */
> - I915_WRITE(DMA_CTRL, _MASKED_BIT_ENABLE(UOS_MOVE | START_DMA));
> + intel_uncore_write(uncore, DMA_CTRL,
> + _MASKED_BIT_ENABLE(UOS_MOVE | START_DMA));
> - return guc_wait_ucode(guc);
> + return guc_wait_ucode(uncore);
> }
> /*
> * Load the GuC firmware blob into the MinuteIA.
> @@ -278,12 +279,12 @@ static int guc_xfer_ucode(struct intel_guc *guc)
> static int guc_fw_xfer(struct intel_uc_fw *guc_fw)
> {
> struct intel_guc *guc = container_of(guc_fw, struct intel_guc, fw);
> - struct drm_i915_private *dev_priv = guc_to_i915(guc);
> + struct intel_uncore *uncore = guc_to_gt(guc)->uncore;
> int ret;
> GEM_BUG_ON(guc_fw->type != INTEL_UC_FW_TYPE_GUC);
> - intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_ALL);
> + intel_uncore_forcewake_get(uncore, FORCEWAKE_ALL);
> guc_prepare_xfer(guc);
> @@ -296,7 +297,7 @@ static int guc_fw_xfer(struct intel_uc_fw *guc_fw)
> ret = guc_xfer_ucode(guc);
> - intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL);
> + intel_uncore_forcewake_put(uncore, FORCEWAKE_ALL);
> return ret;
> }
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> index 23906228b9b4..9ec6eb71f37d 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> @@ -28,6 +28,7 @@
> #include "gt/intel_context.h"
> #include "gt/intel_engine_pm.h"
> +#include "gt/intel_gt.h"
> #include "gt/intel_lrc_reg.h"
> #include "intel_guc_submission.h"
> @@ -201,10 +202,10 @@ static struct guc_doorbell_info
> *__get_doorbell(struct intel_guc_client *client)
> static bool __doorbell_valid(struct intel_guc *guc, u16 db_id)
> {
> - struct drm_i915_private *dev_priv = guc_to_i915(guc);
> + struct intel_uncore *uncore = guc_to_gt(guc)->uncore;
> GEM_BUG_ON(db_id >= GUC_NUM_DOORBELLS);
> - return I915_READ(GEN8_DRBREGL(db_id)) & GEN8_DRB_VALID;
> + return intel_uncore_read(uncore, GEN8_DRBREGL(db_id)) & GEN8_DRB_VALID;
> }
> static void __init_doorbell(struct intel_guc_client *client)
> @@ -1003,9 +1004,10 @@ void intel_guc_submission_fini(struct intel_guc
> *guc)
> guc_stage_desc_pool_destroy(guc);
> }
> -static void guc_interrupts_capture(struct drm_i915_private *dev_priv)
> +static void guc_interrupts_capture(struct intel_gt *gt)
maybe for guc_interrupts_capture|release() we can pass guc instead of gt
and derive gt inside function using guc_to_gt() ?
then finally naming of guc_interrupts_* functions and 1st param will match
> {
> - struct intel_rps *rps = &dev_priv->gt_pm.rps;
> + struct intel_rps *rps = >->i915->gt_pm.rps;
> + struct intel_uncore *uncore = gt->uncore;
> struct intel_engine_cs *engine;
> enum intel_engine_id id;
> int irqs;
> @@ -1014,16 +1016,16 @@ static void guc_interrupts_capture(struct
> drm_i915_private *dev_priv)
> * to GuC
> */
> irqs = _MASKED_BIT_ENABLE(GFX_INTERRUPT_STEERING);
> - for_each_engine(engine, dev_priv, id)
> + for_each_engine(engine, gt->i915, id)
> ENGINE_WRITE(engine, RING_MODE_GEN7, irqs);
> /* route USER_INTERRUPT to Host, all others are sent to GuC. */
> irqs = GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT |
> GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT;
> /* These three registers have the same bit definitions */
> - I915_WRITE(GUC_BCS_RCS_IER, ~irqs);
> - I915_WRITE(GUC_VCS2_VCS1_IER, ~irqs);
> - I915_WRITE(GUC_WD_VECS_IER, ~irqs);
> + intel_uncore_write(uncore, GUC_BCS_RCS_IER, ~irqs);
> + intel_uncore_write(uncore, GUC_VCS2_VCS1_IER, ~irqs);
> + intel_uncore_write(uncore, GUC_WD_VECS_IER, ~irqs);
> /*
> * The REDIRECT_TO_GUC bit of the PMINTRMSK register directs all
> @@ -1048,9 +1050,10 @@ static void guc_interrupts_capture(struct
> drm_i915_private *dev_priv)
> rps->pm_intrmsk_mbz &= ~GEN8_PMINTR_DISABLE_REDIRECT_TO_GUC;
> }
> -static void guc_interrupts_release(struct drm_i915_private *dev_priv)
> +static void guc_interrupts_release(struct intel_gt *gt)
> {
> - struct intel_rps *rps = &dev_priv->gt_pm.rps;
> + struct intel_rps *rps = >->i915->gt_pm.rps;
> + struct intel_uncore *uncore = gt->uncore;
> struct intel_engine_cs *engine;
> enum intel_engine_id id;
> int irqs;
> @@ -1061,13 +1064,13 @@ static void guc_interrupts_release(struct
> drm_i915_private *dev_priv)
> */
> irqs = _MASKED_FIELD(GFX_FORWARD_VBLANK_MASK,
> GFX_FORWARD_VBLANK_NEVER);
> irqs |= _MASKED_BIT_DISABLE(GFX_INTERRUPT_STEERING);
> - for_each_engine(engine, dev_priv, id)
> + for_each_engine(engine, gt->i915, id)
> ENGINE_WRITE(engine, RING_MODE_GEN7, irqs);
> /* route all GT interrupts to the host */
> - I915_WRITE(GUC_BCS_RCS_IER, 0);
> - I915_WRITE(GUC_VCS2_VCS1_IER, 0);
> - I915_WRITE(GUC_WD_VECS_IER, 0);
> + intel_uncore_write(uncore, GUC_BCS_RCS_IER, 0);
> + intel_uncore_write(uncore, GUC_VCS2_VCS1_IER, 0);
> + intel_uncore_write(uncore, GUC_WD_VECS_IER, 0);
> rps->pm_intrmsk_mbz |= GEN8_PMINTR_DISABLE_REDIRECT_TO_GUC;
> rps->pm_intrmsk_mbz &= ~ARAT_EXPIRED_INTRMSK;
> @@ -1117,7 +1120,7 @@ static void guc_set_default_submission(struct
> intel_engine_cs *engine)
> int intel_guc_submission_enable(struct intel_guc *guc)
> {
> - struct drm_i915_private *dev_priv = guc_to_i915(guc);
> + struct intel_gt *gt = guc_to_gt(guc);
> struct intel_engine_cs *engine;
> enum intel_engine_id id;
> int err;
> @@ -1142,9 +1145,9 @@ int intel_guc_submission_enable(struct intel_guc
> *guc)
> return err;
> /* Take over from manual control of ELSP (execlists) */
> - guc_interrupts_capture(dev_priv);
> + guc_interrupts_capture(gt);
> - for_each_engine(engine, dev_priv, id) {
> + for_each_engine(engine, gt->i915, id) {
> engine->set_default_submission = guc_set_default_submission;
> engine->set_default_submission(engine);
> }
> @@ -1154,11 +1157,11 @@ int intel_guc_submission_enable(struct intel_guc
> *guc)
> void intel_guc_submission_disable(struct intel_guc *guc)
> {
> - struct drm_i915_private *dev_priv = guc_to_i915(guc);
> + struct intel_gt *gt = guc_to_gt(guc);
> - GEM_BUG_ON(dev_priv->gt.awake); /* GT should be parked first */
> + GEM_BUG_ON(gt->awake); /* GT should be parked first */
> - guc_interrupts_release(dev_priv);
> + guc_interrupts_release(gt);
> guc_clients_disable(guc);
> }
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_huc.c
> b/drivers/gpu/drm/i915/gt/uc/intel_huc.c
> index 581c9c3d4fc0..99f0fa2e8ff5 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_huc.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_huc.c
> @@ -24,6 +24,7 @@
> #include <linux/types.h>
> +#include "gt/intel_gt.h"
> #include "intel_huc.h"
> #include "i915_drv.h"
> @@ -46,8 +47,8 @@ void intel_huc_init_early(struct intel_huc *huc)
> static int intel_huc_rsa_data_create(struct intel_huc *huc)
> {
> - struct drm_i915_private *i915 = huc_to_i915(huc);
> - struct intel_guc *guc = &i915->gt.uc.guc;
> + struct intel_gt *gt = huc_to_gt(huc);
> + struct intel_guc *guc = >->uc.guc;
> struct i915_vma *vma;
> void *vaddr;
> @@ -112,8 +113,8 @@ void intel_huc_fini(struct intel_huc *huc)
> */
> int intel_huc_auth(struct intel_huc *huc)
> {
> - struct drm_i915_private *i915 = huc_to_i915(huc);
> - struct intel_guc *guc = &i915->gt.uc.guc;
> + struct intel_gt *gt = huc_to_gt(huc);
> + struct intel_guc *guc = >->uc.guc;
> int ret;
> if (huc->fw.load_status != INTEL_UC_FIRMWARE_SUCCESS)
> @@ -127,7 +128,7 @@ int intel_huc_auth(struct intel_huc *huc)
> }
> /* Check authentication status, it should be done by now */
> - ret = __intel_wait_for_register(&i915->uncore,
> + ret = __intel_wait_for_register(gt->uncore,
> huc->status.reg,
> huc->status.mask,
> huc->status.value,
> @@ -159,16 +160,15 @@ int intel_huc_auth(struct intel_huc *huc)
> */
> int intel_huc_check_status(struct intel_huc *huc)
> {
> - struct drm_i915_private *dev_priv = huc_to_i915(huc);
> + struct intel_gt *gt = huc_to_gt(huc);
> intel_wakeref_t wakeref;
> bool status = false;
> - if (!HAS_HUC(dev_priv))
> + if (!intel_uc_is_using_huc(>->uc))
> return -ENODEV;
> - with_intel_runtime_pm(&dev_priv->runtime_pm, wakeref)
> - status = (I915_READ(huc->status.reg) & huc->status.mask) ==
> - huc->status.value;
> + with_intel_runtime_pm(>->i915->runtime_pm, wakeref)
> + status = intel_uncore_read(gt->uncore, huc->status.reg);
> - return status;
> + return (status & huc->status.mask) == huc->status.value;
> }
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c
> b/drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c
> index 06e726ba9863..becfd34a26c1 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c
> @@ -4,6 +4,7 @@
> * Copyright © 2014-2018 Intel Corporation
> */
> +#include "gt/intel_gt.h"
> #include "intel_huc_fw.h"
> #include "i915_drv.h"
> @@ -139,8 +140,7 @@ static void huc_xfer_rsa(struct intel_huc *huc)
> static int huc_xfer_ucode(struct intel_huc *huc)
> {
> struct intel_uc_fw *huc_fw = &huc->fw;
> - struct drm_i915_private *dev_priv = huc_to_i915(huc);
> - struct intel_uncore *uncore = &dev_priv->uncore;
> + struct intel_uncore *uncore = huc_to_gt(huc)->uncore;
> unsigned long offset = 0;
> u32 size;
> int ret;
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc.c
> b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
> index 2062e7ff05e8..3fead2dc9d32 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_uc.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
> @@ -224,7 +224,7 @@ static void guc_free_load_err_log(struct intel_guc
> *guc)
> */
> static void guc_clear_mmio_msg(struct intel_guc *guc)
> {
> - intel_uncore_write(&guc_to_i915(guc)->uncore, SOFT_SCRATCH(15), 0);
> + intel_uncore_write(guc_to_gt(guc)->uncore, SOFT_SCRATCH(15), 0);
> }
> static void guc_get_mmio_msg(struct intel_guc *guc)
> @@ -233,7 +233,7 @@ static void guc_get_mmio_msg(struct intel_guc *guc)
> spin_lock_irq(&guc->irq_lock);
> - val = intel_uncore_read(&guc_to_i915(guc)->uncore, SOFT_SCRATCH(15));
> + val = intel_uncore_read(guc_to_gt(guc)->uncore, SOFT_SCRATCH(15));
> guc->mmio_msg |= val & guc->msg_enabled_mask;
> /*
> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
> b/drivers/gpu/drm/i915/i915_gem_gtt.c
> index 236c964dd761..4d694bff08ce 100644
> --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
hmm, this chunk below, maybe it should be in separate patch ?
> @@ -3395,10 +3395,8 @@ int i915_ggtt_enable_hw(struct drm_i915_private
> *dev_priv)
> return 0;
> }
> -void i915_ggtt_enable_guc(struct drm_i915_private *i915)
> +void i915_ggtt_enable_guc(struct i915_ggtt *ggtt)
> {
> - struct i915_ggtt *ggtt = &i915->ggtt;
> -
> GEM_BUG_ON(ggtt->invalidate != gen6_ggtt_invalidate);
> ggtt->invalidate = guc_ggtt_invalidate;
> @@ -3406,10 +3404,8 @@ void i915_ggtt_enable_guc(struct drm_i915_private
> *i915)
> ggtt->invalidate(ggtt);
> }
> -void i915_ggtt_disable_guc(struct drm_i915_private *i915)
> +void i915_ggtt_disable_guc(struct i915_ggtt *ggtt)
> {
> - struct i915_ggtt *ggtt = &i915->ggtt;
> -
> /* XXX Temporary pardon for error unload */
> if (ggtt->invalidate == gen6_ggtt_invalidate)
> return;
> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.h
> b/drivers/gpu/drm/i915/i915_gem_gtt.h
> index 57a68ef4eda7..666cd505c99b 100644
> --- a/drivers/gpu/drm/i915/i915_gem_gtt.h
> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.h
> @@ -614,8 +614,8 @@ i915_vm_to_ppgtt(struct i915_address_space *vm)
> int i915_ggtt_probe_hw(struct drm_i915_private *dev_priv);
> int i915_ggtt_init_hw(struct drm_i915_private *dev_priv);
> int i915_ggtt_enable_hw(struct drm_i915_private *dev_priv);
> -void i915_ggtt_enable_guc(struct drm_i915_private *i915);
> -void i915_ggtt_disable_guc(struct drm_i915_private *i915);
> +void i915_ggtt_enable_guc(struct i915_ggtt *ggtt);
> +void i915_ggtt_disable_guc(struct i915_ggtt *ggtt);
> int i915_init_ggtt(struct drm_i915_private *dev_priv);
> void i915_ggtt_cleanup_hw(struct drm_i915_private *dev_priv);
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH 12/12] drm/i915/uc: kill <g,h>uc_to_i915
2019-07-10 0:54 ` [PATCH 12/12] drm/i915/uc: kill <g,h>uc_to_i915 Daniele Ceraolo Spurio
@ 2019-07-10 18:37 ` Michal Wajdeczko
0 siblings, 0 replies; 28+ messages in thread
From: Michal Wajdeczko @ 2019-07-10 18:37 UTC (permalink / raw)
To: intel-gfx, Daniele Ceraolo Spurio
On Wed, 10 Jul 2019 02:54:37 +0200, Daniele Ceraolo Spurio
<daniele.ceraolospurio@intel.com> wrote:
> Get rid of them to avoid more users being added while the guc code
> transitions to use gt more than i915.
>
> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
> ---
Acked-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
> drivers/gpu/drm/i915/gt/uc/intel_guc.c | 8 ++++----
> drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c | 3 ++-
> drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c | 2 +-
> drivers/gpu/drm/i915/gt/uc/intel_guc_log.c | 13 +++++++------
> drivers/gpu/drm/i915/gt/uc/intel_huc.c | 2 +-
> drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c | 2 +-
> drivers/gpu/drm/i915/gt/uc/intel_uc.c | 4 ++--
> drivers/gpu/drm/i915/i915_drv.h | 10 ----------
> 8 files changed, 18 insertions(+), 26 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
> b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
> index 6b56f39072b1..83f2c197375f 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
> @@ -77,7 +77,7 @@ void intel_guc_init_send_regs(struct intel_guc *guc)
> void intel_guc_init_early(struct intel_guc *guc)
> {
> - struct drm_i915_private *i915 = guc_to_i915(guc);
> + struct drm_i915_private *i915 = guc_to_gt(guc)->i915;
> intel_guc_fw_init_early(guc);
> intel_guc_ct_init_early(&guc->ct);
> @@ -204,7 +204,7 @@ static u32 guc_ctl_feature_flags(struct intel_guc
> *guc)
> {
> u32 flags = 0;
> - if (!USES_GUC_SUBMISSION(guc_to_i915(guc)))
> + if (!intel_uc_is_using_guc_submission(&guc_to_gt(guc)->uc))
> flags |= GUC_CTL_DISABLE_SCHEDULER;
> return flags;
> @@ -214,7 +214,7 @@ static u32 guc_ctl_ctxinfo_flags(struct intel_guc
> *guc)
> {
> u32 flags = 0;
> - if (USES_GUC_SUBMISSION(guc_to_i915(guc))) {
> + if (intel_uc_is_using_guc_submission(&guc_to_gt(guc)->uc)) {
> u32 ctxnum, base;
> base = intel_guc_ggtt_offset(guc, guc->stage_desc_pool);
> @@ -414,7 +414,7 @@ int intel_guc_to_host_process_recv_msg(struct
> intel_guc *guc,
> int intel_guc_sample_forcewake(struct intel_guc *guc)
> {
> - struct drm_i915_private *dev_priv = guc_to_i915(guc);
> + struct drm_i915_private *dev_priv = guc_to_gt(guc)->i915;
> u32 action[2];
> action[0] = INTEL_GUC_ACTION_SAMPLE_FORCEWAKE;
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
> b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
> index 69859d1e047f..a0da80241f22 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
> @@ -22,6 +22,7 @@
> *
> */
> +#include "gt/intel_gt.h"
> #include "intel_guc_ads.h"
> #include "intel_uc.h"
> #include "i915_drv.h"
> @@ -85,7 +86,7 @@ struct __guc_ads_blob {
> static void __guc_ads_init(struct intel_guc *guc)
> {
> - struct drm_i915_private *dev_priv = guc_to_i915(guc);
> + struct drm_i915_private *dev_priv = guc_to_gt(guc)->i915;
> struct __guc_ads_blob *blob = guc->ads_blob;
> const u32 skipped_size = LRC_PPHWSP_SZ * PAGE_SIZE +
> LR_HW_CONTEXT_SIZE;
> u32 base;
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c
> b/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c
> index 98305e3fd42c..3dfa40fdbe99 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c
> @@ -76,7 +76,7 @@ MODULE_FIRMWARE(ICL_GUC_FIRMWARE_PATH);
> static void guc_fw_select(struct intel_uc_fw *guc_fw)
> {
> struct intel_guc *guc = container_of(guc_fw, struct intel_guc, fw);
> - struct drm_i915_private *i915 = guc_to_i915(guc);
> + struct drm_i915_private *i915 = guc_to_gt(guc)->i915;
> GEM_BUG_ON(guc_fw->type != INTEL_UC_FW_TYPE_GUC);
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_log.c
> b/drivers/gpu/drm/i915/gt/uc/intel_guc_log.c
> index 0355724ee997..52f814704d8e 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_log.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_log.c
> @@ -24,6 +24,7 @@
> #include <linux/debugfs.h>
> +#include "gt/intel_gt.h"
> #include "intel_guc_log.h"
> #include "i915_drv.h"
> @@ -215,7 +216,7 @@ static bool guc_check_log_buf_overflow(struct
> intel_guc_log *log,
> log->stats[type].sampled_overflow += 16;
> }
> - dev_notice_ratelimited(guc_to_i915(log_to_guc(log))->drm.dev,
> + dev_notice_ratelimited(guc_to_gt(log_to_guc(log))->i915->drm.dev,
> "GuC log buffer overflow\n");
> }
> @@ -389,7 +390,7 @@ void intel_guc_log_init_early(struct intel_guc_log
> *log)
> static int guc_log_relay_create(struct intel_guc_log *log)
> {
> struct intel_guc *guc = log_to_guc(log);
> - struct drm_i915_private *dev_priv = guc_to_i915(guc);
> + struct drm_i915_private *dev_priv = guc_to_gt(guc)->i915;
> struct rchan *guc_log_relay_chan;
> size_t n_subbufs, subbuf_size;
> int ret;
> @@ -435,7 +436,7 @@ static void guc_log_relay_destroy(struct
> intel_guc_log *log)
> static void guc_log_capture_logs(struct intel_guc_log *log)
> {
> struct intel_guc *guc = log_to_guc(log);
> - struct drm_i915_private *dev_priv = guc_to_i915(guc);
> + struct drm_i915_private *dev_priv = guc_to_gt(guc)->i915;
> intel_wakeref_t wakeref;
> guc_read_update_log_buffer(log);
> @@ -504,7 +505,7 @@ void intel_guc_log_destroy(struct intel_guc_log *log)
> int intel_guc_log_set_level(struct intel_guc_log *log, u32 level)
> {
> struct intel_guc *guc = log_to_guc(log);
> - struct drm_i915_private *dev_priv = guc_to_i915(guc);
> + struct drm_i915_private *dev_priv = guc_to_gt(guc)->i915;
> intel_wakeref_t wakeref;
> int ret = 0;
> @@ -621,7 +622,7 @@ int intel_guc_log_relay_open(struct intel_guc_log
> *log)
> void intel_guc_log_relay_flush(struct intel_guc_log *log)
> {
> struct intel_guc *guc = log_to_guc(log);
> - struct drm_i915_private *i915 = guc_to_i915(guc);
> + struct drm_i915_private *i915 = guc_to_gt(guc)->i915;
> intel_wakeref_t wakeref;
> /*
> @@ -640,7 +641,7 @@ void intel_guc_log_relay_flush(struct intel_guc_log
> *log)
> void intel_guc_log_relay_close(struct intel_guc_log *log)
> {
> struct intel_guc *guc = log_to_guc(log);
> - struct drm_i915_private *i915 = guc_to_i915(guc);
> + struct drm_i915_private *i915 = guc_to_gt(guc)->i915;
> guc_log_disable_flush_events(log);
> intel_synchronize_irq(i915);
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_huc.c
> b/drivers/gpu/drm/i915/gt/uc/intel_huc.c
> index 99f0fa2e8ff5..bc14439173d7 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_huc.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_huc.c
> @@ -30,7 +30,7 @@
> void intel_huc_init_early(struct intel_huc *huc)
> {
> - struct drm_i915_private *i915 = huc_to_i915(huc);
> + struct drm_i915_private *i915 = huc_to_gt(huc)->i915;
> intel_huc_fw_init_early(huc);
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c
> b/drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c
> index becfd34a26c1..543854c42d9d 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c
> @@ -70,7 +70,7 @@ MODULE_FIRMWARE(I915_ICL_HUC_UCODE);
> static void huc_fw_select(struct intel_uc_fw *huc_fw)
> {
> struct intel_huc *huc = container_of(huc_fw, struct intel_huc, fw);
> - struct drm_i915_private *dev_priv = huc_to_i915(huc);
> + struct drm_i915_private *dev_priv = huc_to_gt(huc)->i915;
> GEM_BUG_ON(huc_fw->type != INTEL_UC_FW_TYPE_HUC);
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc.c
> b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
> index 3fead2dc9d32..be0f8deba2cb 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_uc.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
> @@ -248,7 +248,7 @@ static void guc_get_mmio_msg(struct intel_guc *guc)
> static void guc_handle_mmio_msg(struct intel_guc *guc)
> {
> - struct drm_i915_private *i915 = guc_to_i915(guc);
> + struct drm_i915_private *i915 = guc_to_gt(guc)->i915;
> /* we need communication to be enabled to reply to GuC */
> GEM_BUG_ON(guc->handler == intel_guc_to_host_event_handler_nop);
> @@ -280,7 +280,7 @@ static void guc_disable_interrupts(struct intel_guc
> *guc)
> static int guc_enable_communication(struct intel_guc *guc)
> {
> - struct drm_i915_private *i915 = guc_to_i915(guc);
> + struct drm_i915_private *i915 = guc_to_gt(guc)->i915;
> int ret;
> ret = intel_guc_ct_enable(&guc->ct);
> diff --git a/drivers/gpu/drm/i915/i915_drv.h
> b/drivers/gpu/drm/i915/i915_drv.h
> index 2ace1ad173ad..1dbc4f5c8661 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1901,16 +1901,6 @@ static inline struct drm_i915_private
> *wopcm_to_i915(struct intel_wopcm *wopcm)
> return container_of(wopcm, struct drm_i915_private, wopcm);
> }
> -static inline struct drm_i915_private *guc_to_i915(struct intel_guc
> *guc)
> -{
> - return container_of(guc, struct drm_i915_private, gt.uc.guc);
> -}
> -
> -static inline struct drm_i915_private *huc_to_i915(struct intel_huc
> *huc)
> -{
> - return container_of(huc, struct drm_i915_private, gt.uc.huc);
> -}
> -
> /* Simple iterator over all initialised engines */
> #define for_each_engine(engine__, dev_priv__, id__) \
> for ((id__) = 0; \
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH 04/12] drm/i915/uc: introduce intel_uc_fw_supported
2019-07-10 16:57 ` Michal Wajdeczko
@ 2019-07-10 21:46 ` Daniele Ceraolo Spurio
2019-07-11 12:48 ` Michal Wajdeczko
0 siblings, 1 reply; 28+ messages in thread
From: Daniele Ceraolo Spurio @ 2019-07-10 21:46 UTC (permalink / raw)
To: Michal Wajdeczko, intel-gfx
On 7/10/19 9:57 AM, Michal Wajdeczko wrote:
> On Wed, 10 Jul 2019 02:54:29 +0200, Daniele Ceraolo Spurio
> <daniele.ceraolospurio@intel.com> wrote:
>
>> Instead of always checking in the device config is GuC and HuC are
>
> s/is/if
>
>> supported or not, we can save the state in the uc_fw structure and
>> avoid going through i915 every time from the low-level uc management
>> code. while at it FIRMWARE_NONE has been renamed to better indicate that
>
> s/while/While
>
>> we haven't started the fetch/load yet, but we might have already selected
>> a blob.
>>
>> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
>> Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
>> ---
>> drivers/gpu/drm/i915/intel_guc_fw.c | 6 +++++-
>> drivers/gpu/drm/i915/intel_huc_fw.c | 6 +++++-
>> drivers/gpu/drm/i915/intel_uc.c | 25 ++++++++++++------------
>> drivers/gpu/drm/i915/intel_uc_fw.c | 4 +++-
>> drivers/gpu/drm/i915/intel_uc_fw.h | 30 ++++++++++++++++++++++++-----
>> 5 files changed, 51 insertions(+), 20 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/intel_guc_fw.c
>> b/drivers/gpu/drm/i915/intel_guc_fw.c
>> index db1e0daca7db..ee95d4960c5c 100644
>> --- a/drivers/gpu/drm/i915/intel_guc_fw.c
>> +++ b/drivers/gpu/drm/i915/intel_guc_fw.c
>> @@ -79,8 +79,12 @@ static void guc_fw_select(struct intel_uc_fw *guc_fw)
>> GEM_BUG_ON(guc_fw->type != INTEL_UC_FW_TYPE_GUC);
>> - if (!HAS_GUC(i915))
>> + if (!HAS_GUC(i915)) {
>> + guc_fw->fetch_status = INTEL_UC_FIRMWARE_NOT_SUPPORTED;
>> return;
>> + }
>> +
>> + guc_fw->fetch_status = INTEL_UC_FIRMWARE_NOT_STARTED;
>> if (i915_modparams.guc_firmware_path) {
>> guc_fw->path = i915_modparams.guc_firmware_path;
>> diff --git a/drivers/gpu/drm/i915/intel_huc_fw.c
>> b/drivers/gpu/drm/i915/intel_huc_fw.c
>> index 05cbf8338f53..06e726ba9863 100644
>> --- a/drivers/gpu/drm/i915/intel_huc_fw.c
>> +++ b/drivers/gpu/drm/i915/intel_huc_fw.c
>> @@ -73,8 +73,12 @@ static void huc_fw_select(struct intel_uc_fw *huc_fw)
>> GEM_BUG_ON(huc_fw->type != INTEL_UC_FW_TYPE_HUC);
>> - if (!HAS_HUC(dev_priv))
>> + if (!HAS_HUC(dev_priv)) {
>> + huc_fw->fetch_status = INTEL_UC_FIRMWARE_NOT_SUPPORTED;
>> return;
>> + }
>> +
>> + huc_fw->fetch_status = INTEL_UC_FIRMWARE_NOT_STARTED;
>> if (i915_modparams.huc_firmware_path) {
>> huc_fw->path = i915_modparams.huc_firmware_path;
>> diff --git a/drivers/gpu/drm/i915/intel_uc.c
>> b/drivers/gpu/drm/i915/intel_uc.c
>> index 789b0bccfb41..ef2a864b8990 100644
>> --- a/drivers/gpu/drm/i915/intel_uc.c
>> +++ b/drivers/gpu/drm/i915/intel_uc.c
>> @@ -71,7 +71,8 @@ static int __get_default_guc_log_level(struct
>> drm_i915_private *i915)
>> {
>> int guc_log_level;
>> - if (!HAS_GUC(i915) || !intel_uc_is_using_guc(i915))
>> + if (!intel_uc_fw_supported(&i915->guc.fw) ||
>
> this goes too far, we should limit number of direct accesses to .fw
> maybe we can have:
>
> inline bool intel_uc_has_guc(i915)
> {
> return intel_guc_is_present(&i915->guc);
> }
>
> inline bool intel_guc_is_present(guc)
> {
> return intel_uc_fw_is_defined(&guc->fw);
> }
>
Maybe instead of saving this info in the uc_fw it'd be better to just
change guc_init_early to not do anything if !HAS_GUC and then do
something like:
bool intel_guc_is_present(guc)
{
return !!guc->send;
}
What do you think? otherwise I'll split it like you suggested
>> + !intel_uc_is_using_guc(i915))
>> guc_log_level = GUC_LOG_LEVEL_DISABLED;
>> else if (IS_ENABLED(CONFIG_DRM_I915_DEBUG) ||
>> IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM))
>> @@ -119,16 +120,16 @@ static void sanitize_options_early(struct
>> drm_i915_private *i915)
>> if (intel_uc_is_using_guc(i915) &&
>> !intel_uc_fw_is_selected(guc_fw)) {
>> DRM_WARN("Incompatible option detected: %s=%d, %s!\n",
>> "enable_guc", i915_modparams.enable_guc,
>> - !HAS_GUC(i915) ? "no GuC hardware" :
>> - "no GuC firmware");
>> + !intel_uc_fw_supported(guc_fw) ?
>> + "no GuC hardware" : "no GuC firmware");
>> }
>> /* Verify HuC firmware availability */
>> if (intel_uc_is_using_huc(i915) &&
>> !intel_uc_fw_is_selected(huc_fw)) {
>> DRM_WARN("Incompatible option detected: %s=%d, %s!\n",
>> "enable_guc", i915_modparams.enable_guc,
>> - !HAS_HUC(i915) ? "no HuC hardware" :
>> - "no HuC firmware");
>> + !intel_uc_fw_supported(huc_fw) ?
>> + "no HuC hardware" : "no HuC firmware");
>> }
>> /* XXX: GuC submission is unavailable for now */
>> @@ -148,8 +149,8 @@ static void sanitize_options_early(struct
>> drm_i915_private *i915)
>> if (i915_modparams.guc_log_level > 0 &&
>> !intel_uc_is_using_guc(i915)) {
>> DRM_WARN("Incompatible option detected: %s=%d, %s!\n",
>> "guc_log_level", i915_modparams.guc_log_level,
>> - !HAS_GUC(i915) ? "no GuC hardware" :
>> - "GuC not enabled");
>> + !intel_uc_fw_supported(guc_fw) ?
>> + "no GuC hardware" : "GuC not enabled");
>> i915_modparams.guc_log_level = 0;
>> }
>> @@ -376,7 +377,7 @@ int intel_uc_init(struct drm_i915_private *i915)
>> if (!USES_GUC(i915))
>> return 0;
>> - if (!HAS_GUC(i915))
>> + if (!intel_uc_fw_supported(&guc->fw))
>> return -ENODEV;
>> /* XXX: GuC submission is unavailable for now */
>> @@ -419,7 +420,7 @@ void intel_uc_fini(struct drm_i915_private *i915)
>> if (!USES_GUC(i915))
>> return;
>> - GEM_BUG_ON(!HAS_GUC(i915));
>> + GEM_BUG_ON(!intel_uc_fw_supported(&guc->fw));
>> if (USES_GUC_SUBMISSION(i915))
>> intel_guc_submission_fini(guc);
>> @@ -435,7 +436,7 @@ static void __uc_sanitize(struct drm_i915_private
>> *i915)
>> struct intel_guc *guc = &i915->guc;
>> struct intel_huc *huc = &i915->huc;
>> - GEM_BUG_ON(!HAS_GUC(i915));
>> + GEM_BUG_ON(!intel_uc_fw_supported(&guc->fw));
>> intel_huc_sanitize(huc);
>> intel_guc_sanitize(guc);
>> @@ -460,7 +461,7 @@ int intel_uc_init_hw(struct drm_i915_private *i915)
>> if (!USES_GUC(i915))
>> return 0;
>> - GEM_BUG_ON(!HAS_GUC(i915));
>> + GEM_BUG_ON(!intel_uc_fw_supported(&guc->fw));
>> guc_reset_interrupts(guc);
>> @@ -557,7 +558,7 @@ void intel_uc_fini_hw(struct drm_i915_private *i915)
>> if (!intel_guc_is_loaded(guc))
>> return;
>> - GEM_BUG_ON(!HAS_GUC(i915));
>> + GEM_BUG_ON(!intel_uc_fw_supported(&guc->fw));
>> if (USES_GUC_SUBMISSION(i915))
>> intel_guc_submission_disable(guc);
>> diff --git a/drivers/gpu/drm/i915/intel_uc_fw.c
>> b/drivers/gpu/drm/i915/intel_uc_fw.c
>> index f342ddd47df8..8ce7210907c0 100644
>> --- a/drivers/gpu/drm/i915/intel_uc_fw.c
>> +++ b/drivers/gpu/drm/i915/intel_uc_fw.c
>> @@ -47,6 +47,8 @@ void intel_uc_fw_fetch(struct drm_i915_private
>> *dev_priv,
>> size_t size;
>> int err;
>> + GEM_BUG_ON(!intel_uc_fw_supported(uc_fw));
>> +
>> if (!uc_fw->path) {
>> dev_info(dev_priv->drm.dev,
>> "%s: No firmware was defined for %s!\n",
>> @@ -328,7 +330,7 @@ void intel_uc_fw_cleanup_fetch(struct intel_uc_fw
>> *uc_fw)
>> if (obj)
>> i915_gem_object_put(obj);
>> - uc_fw->fetch_status = INTEL_UC_FIRMWARE_NONE;
>> + uc_fw->fetch_status = INTEL_UC_FIRMWARE_NOT_STARTED;
>> }
>> /**
>> diff --git a/drivers/gpu/drm/i915/intel_uc_fw.h
>> b/drivers/gpu/drm/i915/intel_uc_fw.h
>> index 24e66469153c..833d04d06576 100644
>> --- a/drivers/gpu/drm/i915/intel_uc_fw.h
>> +++ b/drivers/gpu/drm/i915/intel_uc_fw.h
>> @@ -26,6 +26,7 @@
>> #define _INTEL_UC_FW_H_
>> #include <linux/types.h>
>> +#include "i915_gem.h"
>> struct drm_printer;
>> struct drm_i915_private;
>> @@ -34,8 +35,10 @@ struct drm_i915_private;
>> #define INTEL_UC_FIRMWARE_URL
>> "https://git.kernel.org/pub/scm/linux/kernel/git/firmware/linux-firmware.git/tree/i915"
>>
>> enum intel_uc_fw_status {
>> + INTEL_UC_FIRMWARE_NOT_SUPPORTED = -2, /* no uc HW */
>> INTEL_UC_FIRMWARE_FAIL = -1,
>> - INTEL_UC_FIRMWARE_NONE = 0,
>> + INTEL_UC_FIRMWARE_UNINITIALIZED = 0, /* used to catch checks done
>> too early */
>> + INTEL_UC_FIRMWARE_NOT_STARTED = 1,
>> INTEL_UC_FIRMWARE_PENDING,
>> INTEL_UC_FIRMWARE_SUCCESS
>> };
>> @@ -79,10 +82,14 @@ static inline
>> const char *intel_uc_fw_status_repr(enum intel_uc_fw_status status)
>> {
>> switch (status) {
>> + case INTEL_UC_FIRMWARE_NOT_SUPPORTED:
>
> maybe INTEL_UC_FIRMWARE_NOT_APPLICABLE, as used in string below?
ok
>
>> + return "N/A - uc HW not available";
>
> note that other states have short strings, so just "N/A" ?
ok
>
>> case INTEL_UC_FIRMWARE_FAIL:
>> return "FAIL";
>> - case INTEL_UC_FIRMWARE_NONE:
>> - return "NONE";
>> + case INTEL_UC_FIRMWARE_UNINITIALIZED:
>> + return "UNINITIALIZED";
>> + case INTEL_UC_FIRMWARE_NOT_STARTED:
>> + return "NOT_STARTED";
>
> NOT_STARTED and PENDING are not that much different,
> see below
NOT_STARTED is not a new case I've added, I've just renamed the NONE
case to indicate that we hadn't even started the fetch process, but we
might be past the FW selection.
>
>> case INTEL_UC_FIRMWARE_PENDING:
>> return "PENDING";
>> case INTEL_UC_FIRMWARE_SUCCESS:
>
> maybe we should drop split on fetch/load and use
> single status, something like:
>
> UNINITIALIZED --> N/A (no HW)
> |
> DEFINED ----> MISSING (no valid fw)
> |
> -> FETCHED/UNLOADED <-
> / | \
> \ LOADING /
> \ / \ /
> \- READY FAILED -/
>
>
Nothing against this, but I don't think it belongs in this series.
>> @@ -106,9 +113,15 @@ static inline
>> void intel_uc_fw_init_early(struct intel_uc_fw *uc_fw,
>> enum intel_uc_fw_type type)
>> {
>> + /*
>> + * we use FIRMWARE_UNINITIALIZED to detect checks against
>> fetch_status
>> + * before we're looked at the HW caps to see if we have uc support
>> + */
>> + BUILD_BUG_ON(INTEL_UC_FIRMWARE_UNINITIALIZED);
>> +
>> uc_fw->path = NULL;
>> - uc_fw->fetch_status = INTEL_UC_FIRMWARE_NONE;
>> - uc_fw->load_status = INTEL_UC_FIRMWARE_NONE;
>> + uc_fw->fetch_status = INTEL_UC_FIRMWARE_UNINITIALIZED;
>> + uc_fw->load_status = INTEL_UC_FIRMWARE_NOT_STARTED;
>> uc_fw->type = type;
>> }
>> @@ -122,6 +135,13 @@ static inline bool intel_uc_fw_is_loaded(struct
>> intel_uc_fw *uc_fw)
>> return uc_fw->load_status == INTEL_UC_FIRMWARE_SUCCESS;
>> }
>> +static inline bool intel_uc_fw_supported(struct intel_uc_fw *uc_fw)
>
> returning "supported" in case of "no blob/no defs" might be misleading
> maybe "defined" will clearer ?
>
My idea was to track if the HW had support for FW loading (i.e. if there
is a guc/huc in the GT), independently from us defining or finding a
firmware for it or not. hw_supported?
Daniele
>> +{
>> + /* shouldn't call this before checking hw/blob availability */
>> + GEM_BUG_ON(uc_fw->fetch_status == INTEL_UC_FIRMWARE_UNINITIALIZED);
>> + return uc_fw->fetch_status != INTEL_UC_FIRMWARE_NOT_SUPPORTED;
>> +}
>> +
>> static inline void intel_uc_fw_sanitize(struct intel_uc_fw *uc_fw)
>> {
>> if (intel_uc_fw_is_loaded(uc_fw))
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^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH 04/12] drm/i915/uc: introduce intel_uc_fw_supported
2019-07-10 21:46 ` Daniele Ceraolo Spurio
@ 2019-07-11 12:48 ` Michal Wajdeczko
0 siblings, 0 replies; 28+ messages in thread
From: Michal Wajdeczko @ 2019-07-11 12:48 UTC (permalink / raw)
To: intel-gfx, Daniele Ceraolo Spurio
On Wed, 10 Jul 2019 23:46:25 +0200, Daniele Ceraolo Spurio
<daniele.ceraolospurio@intel.com> wrote:
>
> Maybe instead of saving this info in the uc_fw it'd be better to just
> change guc_init_early to not do anything if !HAS_GUC and then do
> something like:
>
> bool intel_guc_is_present(guc)
> {
> return !!guc->send;
> }
>
> What do you think? otherwise I'll split it like you suggested
Yes, we can check send instead (but without !! to avoid complains from
Chris, and maybe with some extra comments/GEM_BUG_ON in init_early to
not missed that dual role)
intel_uc_has_guc() will still be there as top level helper, right ?
Thanks,
Michal
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^ permalink raw reply [flat|nested] 28+ messages in thread
end of thread, other threads:[~2019-07-11 12:48 UTC | newest]
Thread overview: 28+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-07-10 0:54 [PATCH 00/12] GT-fy the uc code Daniele Ceraolo Spurio
2019-07-10 0:54 ` [PATCH 01/12] drm/i915/guc: Remove preemption support for current fw Daniele Ceraolo Spurio
2019-07-10 15:45 ` Michał Winiarski
2019-07-10 0:54 ` [PATCH 02/12] drm/i915/guc: simplify guc client Daniele Ceraolo Spurio
2019-07-10 15:52 ` Michał Winiarski
2019-07-10 0:54 ` [PATCH 03/12] drm/i915/uc: replace uc init/fini misc Daniele Ceraolo Spurio
2019-07-10 0:54 ` [PATCH 04/12] drm/i915/uc: introduce intel_uc_fw_supported Daniele Ceraolo Spurio
2019-07-10 16:57 ` Michal Wajdeczko
2019-07-10 21:46 ` Daniele Ceraolo Spurio
2019-07-11 12:48 ` Michal Wajdeczko
2019-07-10 0:54 ` [PATCH 05/12] drm/i915/guc: move guc irq functions to intel_guc parameter Daniele Ceraolo Spurio
2019-07-10 0:54 ` [PATCH 06/12] drm/i915/guc: unify guc irq handling Daniele Ceraolo Spurio
2019-07-10 17:04 ` Michal Wajdeczko
2019-07-10 0:54 ` [PATCH 07/12] drm/i915/uc: move GuC and HuC files under gt/uc/ Daniele Ceraolo Spurio
2019-07-10 17:52 ` Michal Wajdeczko
2019-07-10 0:54 ` [PATCH 08/12] drm/i915/uc: move GuC/HuC inside intel_gt under a new intel_uc Daniele Ceraolo Spurio
2019-07-10 18:22 ` Michal Wajdeczko
2019-07-10 0:54 ` [PATCH 09/12] drm/i915/uc: Move intel functions to intel_uc Daniele Ceraolo Spurio
2019-07-10 18:26 ` Michal Wajdeczko
2019-07-10 0:54 ` [PATCH 10/12] drm/i915/uc: prefer intel_gt over i915 in GuC/HuC paths Daniele Ceraolo Spurio
2019-07-10 18:35 ` Michal Wajdeczko
2019-07-10 0:54 ` [PATCH 11/12] drm/i915/guc: prefer intel_gt in guc interrupt functions Daniele Ceraolo Spurio
2019-07-10 0:54 ` [PATCH 12/12] drm/i915/uc: kill <g,h>uc_to_i915 Daniele Ceraolo Spurio
2019-07-10 18:37 ` Michal Wajdeczko
2019-07-10 1:12 ` ✗ Fi.CI.CHECKPATCH: warning for GT-fy the uc code Patchwork
2019-07-10 1:19 ` ✗ Fi.CI.SPARSE: " Patchwork
2019-07-10 1:35 ` ✗ Fi.CI.BAT: failure " Patchwork
2019-07-10 13:02 ` [PATCH 00/12] " Chris Wilson
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