From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E24BEC71142 for ; Thu, 11 Jul 2019 17:35:22 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id BCABD2084B for ; Thu, 11 Jul 2019 17:35:22 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org BCABD2084B Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=redhat.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Received: from localhost ([::1]:44034 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hlcyX-0000O7-Iy for qemu-devel@archiver.kernel.org; Thu, 11 Jul 2019 13:35:21 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:35160) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hlcvt-0007bM-AH for qemu-devel@nongnu.org; Thu, 11 Jul 2019 13:32:39 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hlcvr-0004ow-5d for qemu-devel@nongnu.org; Thu, 11 Jul 2019 13:32:37 -0400 Received: from mx1.redhat.com ([209.132.183.28]:59052) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1hlcve-0004h5-S8; Thu, 11 Jul 2019 13:32:23 -0400 Received: from smtp.corp.redhat.com (int-mx06.intmail.prod.int.phx2.redhat.com [10.5.11.16]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 21D7F309174E; Thu, 11 Jul 2019 17:32:22 +0000 (UTC) Received: from laptop.redhat.com (ovpn-116-46.ams2.redhat.com [10.36.116.46]) by smtp.corp.redhat.com (Postfix) with ESMTP id 41B7B5C8B9; Thu, 11 Jul 2019 17:32:16 +0000 (UTC) From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, peter.maydell@linaro.org Date: Thu, 11 Jul 2019 19:28:42 +0200 Message-Id: <20190711172845.31035-27-eric.auger@redhat.com> In-Reply-To: <20190711172845.31035-1-eric.auger@redhat.com> References: <20190711172845.31035-1-eric.auger@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.16 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.41]); Thu, 11 Jul 2019 17:32:22 +0000 (UTC) Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 209.132.183.28 Subject: [Qemu-devel] [RFC v4 26/29] hw/arm/smmuv3: Fill the IOTLBEntry leaf field on NH_VA invalidation X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: drjones@redhat.com, yi.l.liu@intel.com, mst@redhat.com, jean-philippe.brucker@arm.com, zhangfei.gao@foxmail.com, peterx@redhat.com, alex.williamson@redhat.com, vincent.stehle@arm.com Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Let's propagate the leaf attribute throughout the invalidation path. This hint is used to reduce the scope of the invalidations to the last level of translation. Not enforcing it induces large performance penalties in nested mode. Signed-off-by: Eric Auger --- hw/arm/smmuv3.c | 16 +++++++++------- hw/arm/trace-events | 2 +- 2 files changed, 10 insertions(+), 8 deletions(-) diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c index 8c88923f73..2a6bf78a8e 100644 --- a/hw/arm/smmuv3.c +++ b/hw/arm/smmuv3.c @@ -797,8 +797,7 @@ epilogue: */ static void smmuv3_notify_iova(IOMMUMemoryRegion *mr, IOMMUNotifier *n, - int asid, - dma_addr_t iova) + int asid, dma_addr_t iova, bool leaf) { SMMUDevice *sdev =3D container_of(mr, SMMUDevice, iommu); SMMUEventInfo event =3D {.inval_ste_allowed =3D true}; @@ -825,12 +824,14 @@ static void smmuv3_notify_iova(IOMMUMemoryRegion *m= r, entry.addr_mask =3D (1 << tt->granule_sz) - 1; entry.perm =3D IOMMU_NONE; entry.arch_id =3D asid; + entry.leaf =3D leaf; =20 memory_region_notify_one(n, &entry); } =20 /* invalidate an asid/iova tuple in all mr's */ -static void smmuv3_inv_notifiers_iova(SMMUState *s, int asid, dma_addr_t= iova) +static void smmuv3_inv_notifiers_iova(SMMUState *s, int asid, + dma_addr_t iova, bool leaf) { SMMUDevice *sdev; =20 @@ -841,7 +842,7 @@ static void smmuv3_inv_notifiers_iova(SMMUState *s, i= nt asid, dma_addr_t iova) trace_smmuv3_inv_notifiers_iova(mr->parent_obj.name, asid, iova)= ; =20 IOMMU_NOTIFIER_FOREACH(n, mr) { - smmuv3_notify_iova(mr, n, asid, iova); + smmuv3_notify_iova(mr, n, asid, iova, leaf); } } } @@ -979,9 +980,10 @@ static int smmuv3_cmdq_consume(SMMUv3State *s) { dma_addr_t addr =3D CMD_ADDR(&cmd); uint16_t vmid =3D CMD_VMID(&cmd); + bool leaf =3D CMD_LEAF(&cmd); =20 - trace_smmuv3_cmdq_tlbi_nh_vaa(vmid, addr); - smmuv3_inv_notifiers_iova(bs, -1, addr); + trace_smmuv3_cmdq_tlbi_nh_vaa(vmid, addr, leaf); + smmuv3_inv_notifiers_iova(bs, -1, addr, leaf); smmu_iotlb_inv_all(bs); break; } @@ -993,7 +995,7 @@ static int smmuv3_cmdq_consume(SMMUv3State *s) bool leaf =3D CMD_LEAF(&cmd); =20 trace_smmuv3_cmdq_tlbi_nh_va(vmid, asid, addr, leaf); - smmuv3_inv_notifiers_iova(bs, asid, addr); + smmuv3_inv_notifiers_iova(bs, asid, addr, leaf); smmu_iotlb_inv_iova(bs, asid, addr); break; } diff --git a/hw/arm/trace-events b/hw/arm/trace-events index 0acedcedc6..3809005cba 100644 --- a/hw/arm/trace-events +++ b/hw/arm/trace-events @@ -43,7 +43,7 @@ smmuv3_cmdq_cfgi_cd(uint32_t sid) "streamid =3D %d" smmuv3_config_cache_hit(uint32_t sid, uint32_t hits, uint32_t misses, ui= nt32_t perc) "Config cache HIT for sid %d (hits=3D%d, misses=3D%d, hit ra= te=3D%d)" smmuv3_config_cache_miss(uint32_t sid, uint32_t hits, uint32_t misses, u= int32_t perc) "Config cache MISS for sid %d (hits=3D%d, misses=3D%d, hit = rate=3D%d)" smmuv3_cmdq_tlbi_nh_va(int vmid, int asid, uint64_t addr, bool leaf) "vm= id =3D%d asid =3D%d addr=3D0x%"PRIx64" leaf=3D%d" -smmuv3_cmdq_tlbi_nh_vaa(int vmid, uint64_t addr) "vmid =3D%d addr=3D0x%"= PRIx64 +smmuv3_cmdq_tlbi_nh_vaa(int vmid, uint64_t addr, bool leaf) "vmid =3D%d = addr=3D0x%"PRIx64" leaf=3D%d" smmuv3_cmdq_tlbi_nh(void) "" smmuv3_cmdq_tlbi_nh_asid(uint16_t asid) "asid=3D%d" smmu_iotlb_cache_hit(uint16_t asid, uint64_t addr, uint32_t hit, uint32_= t miss, uint32_t p) "IOTLB cache HIT asid=3D%d addr=3D0x%"PRIx64" hit=3D%= d miss=3D%d hit rate=3D%d" --=20 2.20.1