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[69.222.133.165]) by smtp.gmail.com with ESMTPSA id z191sm1676728ywa.31.2019.07.11.15.33.12 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Thu, 11 Jul 2019 15:33:12 -0700 (PDT) From: Jan Bobek To: qemu-devel@nongnu.org Date: Thu, 11 Jul 2019 18:32:42 -0400 Message-Id: <20190711223300.6061-1-jan.bobek@gmail.com> X-Mailer: git-send-email 2.20.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::b44 Subject: [Qemu-devel] [RISU PATCH v3 00/18] Support for generating x86 SIMD test images X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jan Bobek , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Richard Henderson Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" This is v3 of the patch series posted in [1] and [2]. Note that this is the first fully-featured patch series implementing all desired functionality, including (V)LDMXCSR and VSIB-based instructions like VGATHER*. While implementing the last bits required in order to support VGATHERx instructions, I ran into problems which required a larger redesign; namely, there are no more !emit blocks as their functionality is now implemented in regular !constraints blocks. Also, memory constraints are specified in !memory blocks, similarly to other architectures. I tested these changes on my machine; both master and slave modes work in both 32-bit and 64-bit modes. Cheers, -Jan Changes since v2: Too many to be listed individually; this patch series might be better reviewed on its own. References: 1. https://lists.nongnu.org/archive/html/qemu-devel/2019-06/msg04123.html 2. https://lists.nongnu.org/archive/html/qemu-devel/2019-07/msg00001.html Jan Bobek (18): risugen_common: add helper functions insnv, randint risugen_common: split eval_with_fields into extract_fields and eval_block risugen_x86_asm: add module risugen_x86_constraints: add module risugen_x86_memory: add module risugen_x86: add module risugen: allow all byte-aligned instructions risugen: add command-line flag --x86_64 risugen: add --xfeatures option for x86 x86.risu: add MMX instructions x86.risu: add SSE instructions x86.risu: add SSE2 instructions x86.risu: add SSE3 instructions x86.risu: add SSSE3 instructions x86.risu: add SSE4.1 and SSE4.2 instructions x86.risu: add AES and PCLMULQDQ instructions x86.risu: add AVX instructions x86.risu: add AVX2 instructions risugen | 27 +- risugen_arm.pm | 6 +- risugen_common.pm | 117 +- risugen_m68k.pm | 3 +- risugen_ppc64.pm | 6 +- risugen_x86.pm | 518 +++++ risugen_x86_asm.pm | 918 ++++++++ risugen_x86_constraints.pm | 154 ++ risugen_x86_memory.pm | 87 + x86.risu | 4499 ++++++++++++++++++++++++++++++++++++ 10 files changed, 6293 insertions(+), 42 deletions(-) create mode 100644 risugen_x86.pm create mode 100644 risugen_x86_asm.pm create mode 100644 risugen_x86_constraints.pm create mode 100644 risugen_x86_memory.pm create mode 100644 x86.risu -- 2.20.1