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From: Lucas De Marchi <lucas.demarchi@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: Mahesh Kumar <mahesh1.kumar@intel.com>
Subject: [PATCH 03/22] drm/i915/tgl: update ddi/tc clock_off bits
Date: Fri, 12 Jul 2019 18:09:21 -0700	[thread overview]
Message-ID: <20190713010940.17711-4-lucas.demarchi@intel.com> (raw)
In-Reply-To: <20190713010940.17711-1-lucas.demarchi@intel.com>

From: Mahesh Kumar <mahesh1.kumar@intel.com>

In GEN 12 PORT_C DDI clk_off bit is not equally distanced to A/B,
it's at offset 24. Similarly TC port (5/6) clk off bits are at
offset 22/23. Extend the macros to cover the additional ports.

Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index def71fd2e4d1..d873d9fbbf0e 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -9749,8 +9749,9 @@ enum skl_power_gate {
 
 #define ICL_DPCLKA_CFGCR0			_MMIO(0x164280)
 #define  ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)	(1 << _PICK(phy, 10, 11, 24))
-#define  ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port) (1 << ((tc_port) == PORT_TC4 ? \
-						      21 : (tc_port) + 12))
+#define  ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port)	(1 << ((tc_port) < PORT_TC4 ? \
+						       (tc_port) + 12 : \
+						       (tc_port) - PORT_TC4 + 21))
 #define  ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)	((phy) * 2)
 #define  ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy)	(3 << ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy))
 #define  ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll, phy)	((pll) << ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy))
-- 
2.21.0

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  parent reply	other threads:[~2019-07-13  1:09 UTC|newest]

Thread overview: 64+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-07-13  1:09 [PATCH 00/22] Tiger Lake part 2 Lucas De Marchi
2019-07-13  1:09 ` [PATCH 01/22] drm/i915/tgl: skip setting PORT_CL_DW12_* on initialization Lucas De Marchi
2019-07-18 20:35   ` Atwood, Matthew S
2019-07-13  1:09 ` [PATCH 02/22] drm/i915/tgl: select correct bit for port select Lucas De Marchi
2019-07-16 21:37   ` Srivatsa, Anusha
2019-07-18 20:20   ` Atwood, Matthew S
2019-07-13  1:09 ` Lucas De Marchi [this message]
2019-07-16 22:41   ` [PATCH 03/22] drm/i915/tgl: update ddi/tc clock_off bits Srivatsa, Anusha
2019-07-18 21:09   ` Atwood, Matthew S
2019-07-13  1:09 ` [PATCH 04/22] drm/i915/tgl: Add hpd interrupt handling Lucas De Marchi
2019-07-19 13:47   ` Ville Syrjälä
2019-07-19 16:45     ` Lucas De Marchi
2019-07-19 17:08       ` Ville Syrjälä
2019-07-19 17:14         ` Ville Syrjälä
2019-07-19 17:28           ` Lucas De Marchi
2019-07-13  1:09 ` [PATCH 05/22] drm/i915/tgl: Update north display hotplug detection to TGL connections Lucas De Marchi
2019-07-16 23:09   ` Srivatsa, Anusha
2019-07-13  1:09 ` [PATCH 06/22] drm/i915/tgl: handle DP aux interrupts Lucas De Marchi
2019-07-17  0:14   ` Srivatsa, Anusha
2019-07-13  1:09 ` [PATCH 07/22] drm/i915/dmc: Load DMC on TGL Lucas De Marchi
2019-07-19 10:44   ` Anshuman Gupta
2019-07-19 15:34     ` Lucas De Marchi
2019-07-19 16:05   ` Atwood, Matthew S
2019-07-13  1:09 ` [PATCH 08/22] drm/i915/tgl: Add DKL phy pll registers Lucas De Marchi
2019-07-19 21:22   ` Atwood, Matthew S
2019-07-13  1:09 ` [PATCH 09/22] drm/i915/tgl: re-indent code to prepare for DKL changes Lucas De Marchi
2019-07-22 22:31   ` Atwood, Matthew S
2019-07-13  1:09 ` [PATCH 10/22] drm/i915/tgl: Add DKL phy pll state calculations Lucas De Marchi
2019-07-13  1:09 ` [PATCH 11/22] drm/i915/tgl: start adding the DKL PLLs to use on TC ports Lucas De Marchi
2019-07-13  1:09 ` [PATCH 12/22] drm/i915/tgl: Add support for dkl pll write Lucas De Marchi
2019-07-13  1:09 ` [PATCH 13/22] drm/i915/gen12: add support for reading the timestamp frequency Lucas De Marchi
2019-07-13  1:09 ` [PATCH 14/22] drm/i915/tgl: allow the reg_read ioctl to read the RCS TIMESTAMP register Lucas De Marchi
2019-07-13  1:09 ` [PATCH 15/22] drm/i915/tgl: Introduce initial Tigerlake Workarounds Lucas De Marchi
2019-07-13  1:09 ` [PATCH 16/22] drm/i915/tgl: Implement Wa_1604555607 Lucas De Marchi
2019-07-18  6:03   ` Tvrtko Ursulin
2019-07-19 17:41     ` Lucas De Marchi
2019-07-13  1:09 ` [PATCH 17/22] drm/i915/tgl: Implement Wa_1406941453 Lucas De Marchi
2019-07-23 16:35   ` Summers, Stuart
2019-07-13  1:09 ` [PATCH 18/22] drm/i915/tgl: Define MOCS entries for Tigerlake Lucas De Marchi
2019-07-18 13:08   ` Ville Syrjälä
2019-07-18 17:09     ` Daniele Ceraolo Spurio
2019-07-18 17:44       ` Ville Syrjälä
2019-07-24 22:32       ` Lucas De Marchi
2019-07-25 18:26         ` Lis, Tomasz
2019-07-13  1:09 ` [PATCH 19/22] drm/i915/tgl: Tigerlake only has global MOCS registers Lucas De Marchi
2019-07-18 17:40   ` Daniele Ceraolo Spurio
2019-07-19 19:42     ` Lucas De Marchi
2019-07-13  1:09 ` [PATCH 20/22] drm/i915: Move MOCS setup to intel_mocs.c Lucas De Marchi
2019-07-23 16:30   ` Summers, Stuart
2019-07-13  1:09 ` [PATCH 21/22] drm/i915/tgl: Add and use new DC5 and DC6 residency counter registers Lucas De Marchi
2019-07-18  5:47   ` Anshuman Gupta
2019-07-19 15:58     ` Atwood, Matthew S
2019-07-19 18:39     ` Lucas De Marchi
2019-07-22  7:41       ` Anshuman Gupta
2019-07-22 17:40         ` Lucas De Marchi
2019-07-13  1:09 ` [PATCH 22/22] drm/i915/mst: Do not hardcoded the crtcs that encoder can connect Lucas De Marchi
2019-07-18 13:10   ` Ville Syrjälä
2019-08-15 17:41     ` James Ausmus
2019-07-13  1:19 ` ✗ Fi.CI.CHECKPATCH: warning for Tiger Lake part 2 Patchwork
2019-07-13  1:38 ` ✓ Fi.CI.BAT: success " Patchwork
2019-07-14 20:26 ` ✗ Fi.CI.IGT: failure " Patchwork
2019-07-15 22:32 ` ✗ Fi.CI.CHECKPATCH: warning for Tiger Lake part 2 (rev2) Patchwork
2019-07-15 22:55 ` ✓ Fi.CI.BAT: success " Patchwork
2019-07-16  0:02 ` ✗ Fi.CI.IGT: failure " Patchwork

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