From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.7 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 87FC2C7618F for ; Wed, 17 Jul 2019 22:37:12 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 64A5420880 for ; Wed, 17 Jul 2019 22:37:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727610AbfGQWhL (ORCPT ); Wed, 17 Jul 2019 18:37:11 -0400 Received: from mga06.intel.com ([134.134.136.31]:27547 "EHLO mga06.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727410AbfGQWhL (ORCPT ); Wed, 17 Jul 2019 18:37:11 -0400 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by orsmga104.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 17 Jul 2019 15:37:11 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,275,1559545200"; d="scan'208";a="169681745" Received: from dk-chv.jf.intel.com ([10.54.75.59]) by fmsmga007.fm.intel.com with ESMTP; 17 Jul 2019 15:37:10 -0700 From: Dhinakaran Pandiyan To: intel-gfx@lists.freedesktop.org Cc: Dhinakaran Pandiyan , Rodrigo Vivi , =?UTF-8?q?Jos=C3=A9=20Roberto=20de=20Souza?= , stable@vger.kernel.org Subject: [PATCH] drm/i915/vbt: Fix VBT parsing for the PSR section Date: Wed, 17 Jul 2019 15:34:51 -0700 Message-Id: <20190717223451.2595-1-dhinakaran.pandiyan@intel.com> X-Mailer: git-send-email 2.17.1 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org A single 32-bit PSR2 training pattern field follows the sixteen element array of PSR table entries in the VBT spec. But, we incorrectly define this PSR2 field for each of the PSR table entries. As a result, the PSR1 training pattern duration for any panel_type != 0 will be parsed incorrectly. Secondly, PSR2 training pattern durations for VBTs with bdb version >= 226 will also be wrong. Cc: Rodrigo Vivi Cc: José Roberto de Souza Cc: stable@vger.kernel.org Cc: stable@vger.kernel.org #v5.2 Fixes: 88a0d9606aff ("drm/i915/vbt: Parse and use the new field with PSR2 TP2/3 wakeup time") Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=111088 Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=204183 Signed-off-by: Dhinakaran Pandiyan Reviewed-by: Ville Syrjälä Reviewed-by: José Roberto de Souza Acked-by: Rodrigo Vivi Tested-by: François Guerraz --- drivers/gpu/drm/i915/display/intel_bios.c | 2 +- drivers/gpu/drm/i915/display/intel_vbt_defs.h | 6 +++--- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c index 21501d565327..b416b394b641 100644 --- a/drivers/gpu/drm/i915/display/intel_bios.c +++ b/drivers/gpu/drm/i915/display/intel_bios.c @@ -766,7 +766,7 @@ parse_psr(struct drm_i915_private *dev_priv, const struct bdb_header *bdb) } if (bdb->version >= 226) { - u32 wakeup_time = psr_table->psr2_tp2_tp3_wakeup_time; + u32 wakeup_time = psr->psr2_tp2_tp3_wakeup_time; wakeup_time = (wakeup_time >> (2 * panel_type)) & 0x3; switch (wakeup_time) { diff --git a/drivers/gpu/drm/i915/display/intel_vbt_defs.h b/drivers/gpu/drm/i915/display/intel_vbt_defs.h index 93f5c9d204d6..09cd37fb0b1c 100644 --- a/drivers/gpu/drm/i915/display/intel_vbt_defs.h +++ b/drivers/gpu/drm/i915/display/intel_vbt_defs.h @@ -481,13 +481,13 @@ struct psr_table { /* TP wake up time in multiple of 100 */ u16 tp1_wakeup_time; u16 tp2_tp3_wakeup_time; - - /* PSR2 TP2/TP3 wakeup time for 16 panels */ - u32 psr2_tp2_tp3_wakeup_time; } __packed; struct bdb_psr { struct psr_table psr_table[16]; + + /* PSR2 TP2/TP3 wakeup time for 16 panels */ + u32 psr2_tp2_tp3_wakeup_time; } __packed; /* -- 2.17.1 From mboxrd@z Thu Jan 1 00:00:00 1970 From: Dhinakaran Pandiyan Subject: [PATCH] drm/i915/vbt: Fix VBT parsing for the PSR section Date: Wed, 17 Jul 2019 15:34:51 -0700 Message-ID: <20190717223451.2595-1-dhinakaran.pandiyan@intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by gabe.freedesktop.org (Postfix) with ESMTPS id CD4146E2B6 for ; Wed, 17 Jul 2019 22:37:11 +0000 (UTC) List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: intel-gfx@lists.freedesktop.org Cc: stable@vger.kernel.org, Dhinakaran Pandiyan List-Id: intel-gfx@lists.freedesktop.org QSBzaW5nbGUgMzItYml0IFBTUjIgdHJhaW5pbmcgcGF0dGVybiBmaWVsZCBmb2xsb3dzIHRoZSBz aXh0ZWVuIGVsZW1lbnQKYXJyYXkgb2YgUFNSIHRhYmxlIGVudHJpZXMgaW4gdGhlIFZCVCBzcGVj LiBCdXQsIHdlIGluY29ycmVjdGx5IGRlZmluZQp0aGlzIFBTUjIgZmllbGQgZm9yIGVhY2ggb2Yg dGhlIFBTUiB0YWJsZSBlbnRyaWVzLiBBcyBhIHJlc3VsdCwgdGhlIFBTUjEKdHJhaW5pbmcgcGF0 dGVybiBkdXJhdGlvbiBmb3IgYW55IHBhbmVsX3R5cGUgIT0gMCB3aWxsIGJlIHBhcnNlZAppbmNv cnJlY3RseS4gU2Vjb25kbHksIFBTUjIgdHJhaW5pbmcgcGF0dGVybiBkdXJhdGlvbnMgZm9yIFZC VHMgd2l0aCBiZGIKdmVyc2lvbiA+PSAyMjYgd2lsbCBhbHNvIGJlIHdyb25nLgoKQ2M6IFJvZHJp Z28gVml2aSA8cm9kcmlnby52aXZpQGludGVsLmNvbT4KQ2M6IEpvc8OpIFJvYmVydG8gZGUgU291 emEgPGpvc2Uuc291emFAaW50ZWwuY29tPgpDYzogc3RhYmxlQHZnZXIua2VybmVsLm9yZwpDYzog c3RhYmxlQHZnZXIua2VybmVsLm9yZyAjdjUuMgpGaXhlczogODhhMGQ5NjA2YWZmICgiZHJtL2k5 MTUvdmJ0OiBQYXJzZSBhbmQgdXNlIHRoZSBuZXcgZmllbGQgd2l0aCBQU1IyIFRQMi8zIHdha2V1 cCB0aW1lIikKQnVnemlsbGE6IGh0dHBzOi8vYnVncy5mcmVlZGVza3RvcC5vcmcvc2hvd19idWcu Y2dpP2lkPTExMTA4OApCdWd6aWxsYTogaHR0cHM6Ly9idWd6aWxsYS5rZXJuZWwub3JnL3Nob3df YnVnLmNnaT9pZD0yMDQxODMKU2lnbmVkLW9mZi1ieTogRGhpbmFrYXJhbiBQYW5kaXlhbiA8ZGhp bmFrYXJhbi5wYW5kaXlhbkBpbnRlbC5jb20+ClJldmlld2VkLWJ5OiBWaWxsZSBTeXJqw6Rsw6Qg PHZpbGxlLnN5cmphbGFAbGludXguaW50ZWwuY29tPgpSZXZpZXdlZC1ieTogSm9zw6kgUm9iZXJ0 byBkZSBTb3V6YSA8am9zZS5zb3V6YUBpbnRlbC5jb20+CkFja2VkLWJ5OiBSb2RyaWdvIFZpdmkg PHJvZHJpZ28udml2aUBpbnRlbC5jb20+ClRlc3RlZC1ieTogRnJhbsOnb2lzIEd1ZXJyYXogPGt1 YnJpY2tAZmd2Ni5uZXQ+Ci0tLQogZHJpdmVycy9ncHUvZHJtL2k5MTUvZGlzcGxheS9pbnRlbF9i aW9zLmMgICAgIHwgMiArLQogZHJpdmVycy9ncHUvZHJtL2k5MTUvZGlzcGxheS9pbnRlbF92YnRf ZGVmcy5oIHwgNiArKystLS0KIDIgZmlsZXMgY2hhbmdlZCwgNCBpbnNlcnRpb25zKCspLCA0IGRl bGV0aW9ucygtKQoKZGlmZiAtLWdpdCBhL2RyaXZlcnMvZ3B1L2RybS9pOTE1L2Rpc3BsYXkvaW50 ZWxfYmlvcy5jIGIvZHJpdmVycy9ncHUvZHJtL2k5MTUvZGlzcGxheS9pbnRlbF9iaW9zLmMKaW5k ZXggMjE1MDFkNTY1MzI3Li5iNDE2YjM5NGI2NDEgMTAwNjQ0Ci0tLSBhL2RyaXZlcnMvZ3B1L2Ry bS9pOTE1L2Rpc3BsYXkvaW50ZWxfYmlvcy5jCisrKyBiL2RyaXZlcnMvZ3B1L2RybS9pOTE1L2Rp c3BsYXkvaW50ZWxfYmlvcy5jCkBAIC03NjYsNyArNzY2LDcgQEAgcGFyc2VfcHNyKHN0cnVjdCBk cm1faTkxNV9wcml2YXRlICpkZXZfcHJpdiwgY29uc3Qgc3RydWN0IGJkYl9oZWFkZXIgKmJkYikK IAl9CiAKIAlpZiAoYmRiLT52ZXJzaW9uID49IDIyNikgewotCQl1MzIgd2FrZXVwX3RpbWUgPSBw c3JfdGFibGUtPnBzcjJfdHAyX3RwM193YWtldXBfdGltZTsKKwkJdTMyIHdha2V1cF90aW1lID0g cHNyLT5wc3IyX3RwMl90cDNfd2FrZXVwX3RpbWU7CiAKIAkJd2FrZXVwX3RpbWUgPSAod2FrZXVw X3RpbWUgPj4gKDIgKiBwYW5lbF90eXBlKSkgJiAweDM7CiAJCXN3aXRjaCAod2FrZXVwX3RpbWUp IHsKZGlmZiAtLWdpdCBhL2RyaXZlcnMvZ3B1L2RybS9pOTE1L2Rpc3BsYXkvaW50ZWxfdmJ0X2Rl ZnMuaCBiL2RyaXZlcnMvZ3B1L2RybS9pOTE1L2Rpc3BsYXkvaW50ZWxfdmJ0X2RlZnMuaAppbmRl eCA5M2Y1YzlkMjA0ZDYuLjA5Y2QzN2ZiMGIxYyAxMDA2NDQKLS0tIGEvZHJpdmVycy9ncHUvZHJt L2k5MTUvZGlzcGxheS9pbnRlbF92YnRfZGVmcy5oCisrKyBiL2RyaXZlcnMvZ3B1L2RybS9pOTE1 L2Rpc3BsYXkvaW50ZWxfdmJ0X2RlZnMuaApAQCAtNDgxLDEzICs0ODEsMTMgQEAgc3RydWN0IHBz cl90YWJsZSB7CiAJLyogVFAgd2FrZSB1cCB0aW1lIGluIG11bHRpcGxlIG9mIDEwMCAqLwogCXUx NiB0cDFfd2FrZXVwX3RpbWU7CiAJdTE2IHRwMl90cDNfd2FrZXVwX3RpbWU7Ci0KLQkvKiBQU1Iy IFRQMi9UUDMgd2FrZXVwIHRpbWUgZm9yIDE2IHBhbmVscyAqLwotCXUzMiBwc3IyX3RwMl90cDNf d2FrZXVwX3RpbWU7CiB9IF9fcGFja2VkOwogCiBzdHJ1Y3QgYmRiX3BzciB7CiAJc3RydWN0IHBz cl90YWJsZSBwc3JfdGFibGVbMTZdOworCisJLyogUFNSMiBUUDIvVFAzIHdha2V1cCB0aW1lIGZv ciAxNiBwYW5lbHMgKi8KKwl1MzIgcHNyMl90cDJfdHAzX3dha2V1cF90aW1lOwogfSBfX3BhY2tl ZDsKIAogLyoKLS0gCjIuMTcuMQoKX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19f X19fX19fX19fX18KSW50ZWwtZ2Z4IG1haWxpbmcgbGlzdApJbnRlbC1nZnhAbGlzdHMuZnJlZWRl c2t0b3Aub3JnCmh0dHBzOi8vbGlzdHMuZnJlZWRlc2t0b3Aub3JnL21haWxtYW4vbGlzdGluZm8v aW50ZWwtZ2Z4