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Violators will be prosecuted; (version=TLSv1/SSLv3 cipher=AES256-GCM-SHA384 bits=256/256) Fri, 19 Jul 2019 20:57:29 +0100 Received: from b01ledav003.gho.pok.ibm.com (b01ledav003.gho.pok.ibm.com [9.57.199.108]) by b01cxnp22033.gho.pok.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id x6JJvSwf49414430 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Fri, 19 Jul 2019 19:57:28 GMT Received: from b01ledav003.gho.pok.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 601CBB2065; Fri, 19 Jul 2019 19:57:28 +0000 (GMT) Received: from b01ledav003.gho.pok.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 3E7D0B205F; Fri, 19 Jul 2019 19:57:28 +0000 (GMT) Received: from paulmck-ThinkPad-W541 (unknown [9.85.185.217]) by b01ledav003.gho.pok.ibm.com (Postfix) with ESMTP; Fri, 19 Jul 2019 19:57:28 +0000 (GMT) Received: by paulmck-ThinkPad-W541 (Postfix, from userid 1000) id 3B5D116C0E4B; Fri, 19 Jul 2019 12:57:28 -0700 (PDT) Date: Fri, 19 Jul 2019 12:57:28 -0700 From: "Paul E. McKenney" To: Byungchul Park Cc: Joel Fernandes , Byungchul Park , rcu , LKML , kernel-team@lge.com Subject: Re: [PATCH] rcu: Make jiffies_till_sched_qs writable Reply-To: paulmck@linux.ibm.com References: <20190713151330.GE26519@linux.ibm.com> <20190713154257.GE133650@google.com> <20190713174111.GG26519@linux.ibm.com> <20190719003942.GA28226@X58A-UD3R> <20190719074329.GY14271@linux.ibm.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.21 (2010-09-15) X-TM-AS-GCONF: 00 x-cbid: 19071919-0052-0000-0000-000003E34560 X-IBM-SpamModules-Scores: X-IBM-SpamModules-Versions: BY=3.00011458; HX=3.00000242; KW=3.00000007; PH=3.00000004; SC=3.00000287; SDB=6.01234541; UDB=6.00650591; IPR=6.01015874; MB=3.00027804; MTD=3.00000008; XFM=3.00000015; UTC=2019-07-19 19:57:31 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 19071919-0053-0000-0000-000061C3A421 Message-Id: <20190719195728.GF14271@linux.ibm.com> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:,, definitions=2019-07-19_12:,, signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=0 phishscore=0 bulkscore=0 spamscore=0 clxscore=1015 lowpriorityscore=0 mlxscore=0 impostorscore=0 mlxlogscore=999 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1810050000 definitions=main-1907190215 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri, Jul 19, 2019 at 06:57:58PM +0900, Byungchul Park wrote: > On Fri, Jul 19, 2019 at 4:43 PM Paul E. McKenney wrote: > > > > On Thu, Jul 18, 2019 at 08:52:52PM -0400, Joel Fernandes wrote: > > > On Thu, Jul 18, 2019 at 8:40 PM Byungchul Park wrote: > > > [snip] > > > > > - There is a bug in the CPU stopper machinery itself preventing it > > > > > from scheduling the stopper on Y. Even though Y is not holding up the > > > > > grace period. > > > > > > > > Or any thread on Y is busy with preemption/irq disabled preventing the > > > > stopper from being scheduled on Y. > > > > > > > > Or something is stuck in ttwu() to wake up the stopper on Y due to any > > > > scheduler locks such as pi_lock or rq->lock or something. > > > > > > > > I think what you mentioned can happen easily. > > > > > > > > Basically we would need information about preemption/irq disabled > > > > sections on Y and scheduler's current activity on every cpu at that time. > > > > > > I think all that's needed is an NMI backtrace on all CPUs. An ARM we > > > don't have NMI solutions and only IPI or interrupt based backtrace > > > works which should at least catch and the preempt disable and softirq > > > disable cases. > > > > True, though people with systems having hundreds of CPUs might not > > thank you for forcing an NMI backtrace on each of them. Is it possible > > to NMI only the ones that are holding up the CPU stopper? > > What a good idea! I think it's possible! > > But we need to think about the case NMI doesn't work when the > holding-up was caused by IRQ disabled. > > Though it's just around the corner of weekend, I will keep thinking > on it during weekend! Very good! Thanx, Paul > Thanks, > Byungchul > > > Thanx, Paul > > > > > But yeah I don't see why just the stacks of those CPUs that are > > > blocking the CPU X would not suffice for the trivial cases where a > > > piece of misbehaving code disable interrupts / preemption and > > > prevented the stopper thread from executing. > > > > > > May be once the test case is ready (no rush!) , then it will be more > > > clear what can help. > > > > > > J. > > > > > > > -- > Thanks, > Byungchul >