From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_SANE_1 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D5BE7C76196 for ; Sat, 20 Jul 2019 09:32:10 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id AF94120873 for ; Sat, 20 Jul 2019 09:32:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727353AbfGTJcJ (ORCPT ); Sat, 20 Jul 2019 05:32:09 -0400 Received: from relay3-d.mail.gandi.net ([217.70.183.195]:48167 "EHLO relay3-d.mail.gandi.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727323AbfGTJcJ (ORCPT ); Sat, 20 Jul 2019 05:32:09 -0400 X-Originating-IP: 91.163.65.175 Received: from localhost (91-163-65-175.subs.proxad.net [91.163.65.175]) (Authenticated sender: maxime.ripard@bootlin.com) by relay3-d.mail.gandi.net (Postfix) with ESMTPSA id 1A5FF60002; Sat, 20 Jul 2019 09:32:02 +0000 (UTC) Date: Sat, 20 Jul 2019 11:32:02 +0200 From: Maxime Ripard To: Jagan Teki Cc: Michael Nazzareno Trimarchi , David Airlie , Daniel Vetter , Chen-Yu Tsai , Michael Turquette , Rob Herring , Mark Rutland , linux-arm-kernel , linux-kernel , linux-clk , dri-devel , devicetree , linux-amarula , linux-sunxi Subject: Re: [PATCH v6 11/22] clk: sunxi-ng: a64: Add minimum rate for PLL_MIPI Message-ID: <20190720093202.6fn6xmhvsgawscnu@flea> References: <20190614142406.ybdiqfppo5mc5bgq@flea> <20190625144930.5hegt6bkzqzykjid@flea> <20190703114933.u3x4ej3v7ocewvif@flea> <20190711100100.cty3s6rs3w27low6@flea> <20190720065830.zn3txpyduakywcva@flea> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="2dbototu7fqsblax" Content-Disposition: inline In-Reply-To: User-Agent: NeoMutt/20180716 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org --2dbototu7fqsblax Content-Type: text/plain; charset=us-ascii Content-Disposition: inline On Sat, Jul 20, 2019 at 12:46:27PM +0530, Jagan Teki wrote: > On Sat, Jul 20, 2019 at 12:28 PM Maxime Ripard > wrote: > > > > On Thu, Jul 11, 2019 at 07:43:16PM +0200, Michael Nazzareno Trimarchi wrote: > > > > > tcon-pixel clock is the rate that you want to achive on display side > > > > > and if you have 4 lanes 32bit or lanes and different bit number that > > > > > you need to have a clock that is able to put outside bits and speed > > > > > equal to pixel-clock * bits / lanes. so If you want a pixel-clock of > > > > > 40 mhz and you have 32bits and 4 lanes you need to have a clock of > > > > > 40 * 32 / 4 in no-burst mode. I think that this is done but most of > > > > > the display. > > > > > > > > So this is what the issue is then? > > > > > > > > This one does make sense, and you should just change the rate in the > > > > call to clk_set_rate in sun4i_tcon0_mode_set_cpu. > > > > > > > > I'm still wondering why that hasn't been brought up in either the > > > > discussion or the commit log before though. > > > > > > > Something like this? > > > > > > drivers/gpu/drm/sun4i/sun4i_tcon.c | 20 +++++++++++--------- > > > drivers/gpu/drm/sun4i/sun6i_mipi_dsi.h | 2 -- > > > 2 files changed, 11 insertions(+), 11 deletions(-) > > > > > > diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.c > > > b/drivers/gpu/drm/sun4i/sun4i_tcon.c > > > index 64c43ee6bd92..42560d5c327c 100644 > > > --- a/drivers/gpu/drm/sun4i/sun4i_tcon.c > > > +++ b/drivers/gpu/drm/sun4i/sun4i_tcon.c > > > @@ -263,10 +263,11 @@ static int sun4i_tcon_get_clk_delay(const struct > > > drm_display_mode *mode, > > > } > > > > > > static void sun4i_tcon0_mode_set_common(struct sun4i_tcon *tcon, > > > - const struct drm_display_mode *mode) > > > + const struct drm_display_mode *mode, > > > + u32 tcon_mul) > > > { > > > /* Configure the dot clock */ > > > - clk_set_rate(tcon->dclk, mode->crtc_clock * 1000); > > > + clk_set_rate(tcon->dclk, mode->crtc_clock * tcon_mul * 1000); > > > > > > /* Set the resolution */ > > > regmap_write(tcon->regs, SUN4I_TCON0_BASIC0_REG, > > > @@ -335,12 +336,13 @@ static void sun4i_tcon0_mode_set_cpu(struct > > > sun4i_tcon *tcon, > > > u8 bpp = mipi_dsi_pixel_format_to_bpp(device->format); > > > u8 lanes = device->lanes; > > > u32 block_space, start_delay; > > > - u32 tcon_div; > > > + u32 tcon_div, tcon_mul; > > > > > > - tcon->dclk_min_div = SUN6I_DSI_TCON_DIV; > > > - tcon->dclk_max_div = SUN6I_DSI_TCON_DIV; > > > + tcon->dclk_min_div = 4; > > > + tcon->dclk_max_div = 127; > > > > > > - sun4i_tcon0_mode_set_common(tcon, mode); > > > + tcon_mul = bpp / lanes; > > > + sun4i_tcon0_mode_set_common(tcon, mode, tcon_mul); > > > > > > /* Set dithering if needed */ > > > sun4i_tcon0_mode_set_dithering(tcon, sun4i_tcon_get_connector(encoder)); > > > @@ -366,7 +368,7 @@ static void sun4i_tcon0_mode_set_cpu(struct > > > sun4i_tcon *tcon, > > > */ > > > regmap_read(tcon->regs, SUN4I_TCON0_DCLK_REG, &tcon_div); > > > tcon_div &= GENMASK(6, 0); > > > - block_space = mode->htotal * bpp / (tcon_div * lanes); > > > + block_space = mode->htotal * tcon_div * tcon_mul; > > > block_space -= mode->hdisplay + 40; > > > > > > regmap_write(tcon->regs, SUN4I_TCON0_CPU_TRI0_REG, > > > @@ -408,7 +410,7 @@ static void sun4i_tcon0_mode_set_lvds(struct > > > sun4i_tcon *tcon, > > > > > > tcon->dclk_min_div = 7; > > > tcon->dclk_max_div = 7; > > > - sun4i_tcon0_mode_set_common(tcon, mode); > > > + sun4i_tcon0_mode_set_common(tcon, mode, 1); > > > > > > /* Set dithering if needed */ > > > sun4i_tcon0_mode_set_dithering(tcon, sun4i_tcon_get_connector(encoder)); > > > @@ -487,7 +489,7 @@ static void sun4i_tcon0_mode_set_rgb(struct > > > sun4i_tcon *tcon, > > > > > > tcon->dclk_min_div = 6; > > > tcon->dclk_max_div = 127; > > > - sun4i_tcon0_mode_set_common(tcon, mode); > > > + sun4i_tcon0_mode_set_common(tcon, mode, 1); > > > > > > /* Set dithering if needed */ > > > sun4i_tcon0_mode_set_dithering(tcon, connector); > > > diff --git a/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.h > > > b/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.h > > > index 5c3ad5be0690..a07090579f84 100644 > > > --- a/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.h > > > +++ b/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.h > > > @@ -13,8 +13,6 @@ > > > #include > > > #include > > > > > > -#define SUN6I_DSI_TCON_DIV 4 > > > - > > > struct sun6i_dsi { > > > struct drm_connector connector; > > > struct drm_encoder encoder; > > > > I had more something like this in mind: > > http://code.bulix.org/nlp5a4-803511 > > Worth to look at it. was it working on your panel? meanwhile I will check it. I haven't tested it. > We have updated with below change [1], seems working on but is > actually checking the each divider as before start with 4... till 127. > > This new approach, is start looking the best divider from 4.. based on > the idea vs rounded it will ended up best divider like [2] But why? I mean, it's not like it's the first time I'm asking this... If the issue is what Micheal described, then the divider has nothing to do with it. We've had that discussion over and over again. So you need to come with some argument and proof that the divider of that clock need to change. Otherwise, stop trying to make that happen: it won't. Maxime -- Maxime Ripard, Bootlin Embedded Linux and Kernel engineering https://bootlin.com --2dbototu7fqsblax Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iHUEABYIAB0WIQRcEzekXsqa64kGDp7j7w1vZxhRxQUCXTLfkgAKCRDj7w1vZxhR xXluAP4vGeqsFx22zqCbCazkSqNBlJ1xlo7FG4cHnv34XdrozgEAwDmJm2HpOFaV KgsjKFHWq3QK4YYxA3/WinhP6mxyVg8= =VKsI -----END PGP SIGNATURE----- --2dbototu7fqsblax-- From mboxrd@z Thu Jan 1 00:00:00 1970 From: Maxime Ripard Subject: Re: [PATCH v6 11/22] clk: sunxi-ng: a64: Add minimum rate for PLL_MIPI Date: Sat, 20 Jul 2019 11:32:02 +0200 Message-ID: <20190720093202.6fn6xmhvsgawscnu@flea> References: <20190614142406.ybdiqfppo5mc5bgq@flea> <20190625144930.5hegt6bkzqzykjid@flea> <20190703114933.u3x4ej3v7ocewvif@flea> <20190711100100.cty3s6rs3w27low6@flea> <20190720065830.zn3txpyduakywcva@flea> Reply-To: maxime.ripard-LDxbnhwyfcJBDgjK7y7TUQ@public.gmane.org Mime-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="2dbototu7fqsblax" Return-path: Sender: linux-sunxi-/JYPxA39Uh5TLH3MbocFFw@public.gmane.org Content-Disposition: inline In-Reply-To: List-Post: , List-Help: , List-Archive: , List-Unsubscribe: , To: Jagan Teki Cc: Michael Nazzareno Trimarchi , David Airlie , Daniel Vetter , Chen-Yu Tsai , Michael Turquette , Rob Herring , Mark Rutland , linux-arm-kernel , linux-kernel , linux-clk , dri-devel , devicetree , linux-amarula , linux-sunxi List-Id: devicetree@vger.kernel.org --2dbototu7fqsblax Content-Type: text/plain; charset="UTF-8" Content-Disposition: inline On Sat, Jul 20, 2019 at 12:46:27PM +0530, Jagan Teki wrote: > On Sat, Jul 20, 2019 at 12:28 PM Maxime Ripard > wrote: > > > > On Thu, Jul 11, 2019 at 07:43:16PM +0200, Michael Nazzareno Trimarchi wrote: > > > > > tcon-pixel clock is the rate that you want to achive on display side > > > > > and if you have 4 lanes 32bit or lanes and different bit number that > > > > > you need to have a clock that is able to put outside bits and speed > > > > > equal to pixel-clock * bits / lanes. so If you want a pixel-clock of > > > > > 40 mhz and you have 32bits and 4 lanes you need to have a clock of > > > > > 40 * 32 / 4 in no-burst mode. I think that this is done but most of > > > > > the display. > > > > > > > > So this is what the issue is then? > > > > > > > > This one does make sense, and you should just change the rate in the > > > > call to clk_set_rate in sun4i_tcon0_mode_set_cpu. > > > > > > > > I'm still wondering why that hasn't been brought up in either the > > > > discussion or the commit log before though. > > > > > > > Something like this? > > > > > > drivers/gpu/drm/sun4i/sun4i_tcon.c | 20 +++++++++++--------- > > > drivers/gpu/drm/sun4i/sun6i_mipi_dsi.h | 2 -- > > > 2 files changed, 11 insertions(+), 11 deletions(-) > > > > > > diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.c > > > b/drivers/gpu/drm/sun4i/sun4i_tcon.c > > > index 64c43ee6bd92..42560d5c327c 100644 > > > --- a/drivers/gpu/drm/sun4i/sun4i_tcon.c > > > +++ b/drivers/gpu/drm/sun4i/sun4i_tcon.c > > > @@ -263,10 +263,11 @@ static int sun4i_tcon_get_clk_delay(const struct > > > drm_display_mode *mode, > > > } > > > > > > static void sun4i_tcon0_mode_set_common(struct sun4i_tcon *tcon, > > > - const struct drm_display_mode *mode) > > > + const struct drm_display_mode *mode, > > > + u32 tcon_mul) > > > { > > > /* Configure the dot clock */ > > > - clk_set_rate(tcon->dclk, mode->crtc_clock * 1000); > > > + clk_set_rate(tcon->dclk, mode->crtc_clock * tcon_mul * 1000); > > > > > > /* Set the resolution */ > > > regmap_write(tcon->regs, SUN4I_TCON0_BASIC0_REG, > > > @@ -335,12 +336,13 @@ static void sun4i_tcon0_mode_set_cpu(struct > > > sun4i_tcon *tcon, > > > u8 bpp = mipi_dsi_pixel_format_to_bpp(device->format); > > > u8 lanes = device->lanes; > > > u32 block_space, start_delay; > > > - u32 tcon_div; > > > + u32 tcon_div, tcon_mul; > > > > > > - tcon->dclk_min_div = SUN6I_DSI_TCON_DIV; > > > - tcon->dclk_max_div = SUN6I_DSI_TCON_DIV; > > > + tcon->dclk_min_div = 4; > > > + tcon->dclk_max_div = 127; > > > > > > - sun4i_tcon0_mode_set_common(tcon, mode); > > > + tcon_mul = bpp / lanes; > > > + sun4i_tcon0_mode_set_common(tcon, mode, tcon_mul); > > > > > > /* Set dithering if needed */ > > > sun4i_tcon0_mode_set_dithering(tcon, sun4i_tcon_get_connector(encoder)); > > > @@ -366,7 +368,7 @@ static void sun4i_tcon0_mode_set_cpu(struct > > > sun4i_tcon *tcon, > > > */ > > > regmap_read(tcon->regs, SUN4I_TCON0_DCLK_REG, &tcon_div); > > > tcon_div &= GENMASK(6, 0); > > > - block_space = mode->htotal * bpp / (tcon_div * lanes); > > > + block_space = mode->htotal * tcon_div * tcon_mul; > > > block_space -= mode->hdisplay + 40; > > > > > > regmap_write(tcon->regs, SUN4I_TCON0_CPU_TRI0_REG, > > > @@ -408,7 +410,7 @@ static void sun4i_tcon0_mode_set_lvds(struct > > > sun4i_tcon *tcon, > > > > > > tcon->dclk_min_div = 7; > > > tcon->dclk_max_div = 7; > > > - sun4i_tcon0_mode_set_common(tcon, mode); > > > + sun4i_tcon0_mode_set_common(tcon, mode, 1); > > > > > > /* Set dithering if needed */ > > > sun4i_tcon0_mode_set_dithering(tcon, sun4i_tcon_get_connector(encoder)); > > > @@ -487,7 +489,7 @@ static void sun4i_tcon0_mode_set_rgb(struct > > > sun4i_tcon *tcon, > > > > > > tcon->dclk_min_div = 6; > > > tcon->dclk_max_div = 127; > > > - sun4i_tcon0_mode_set_common(tcon, mode); > > > + sun4i_tcon0_mode_set_common(tcon, mode, 1); > > > > > > /* Set dithering if needed */ > > > sun4i_tcon0_mode_set_dithering(tcon, connector); > > > diff --git a/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.h > > > b/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.h > > > index 5c3ad5be0690..a07090579f84 100644 > > > --- a/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.h > > > +++ b/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.h > > > @@ -13,8 +13,6 @@ > > > #include > > > #include > > > > > > -#define SUN6I_DSI_TCON_DIV 4 > > > - > > > struct sun6i_dsi { > > > struct drm_connector connector; > > > struct drm_encoder encoder; > > > > I had more something like this in mind: > > http://code.bulix.org/nlp5a4-803511 > > Worth to look at it. was it working on your panel? meanwhile I will check it. I haven't tested it. > We have updated with below change [1], seems working on but is > actually checking the each divider as before start with 4... till 127. > > This new approach, is start looking the best divider from 4.. based on > the idea vs rounded it will ended up best divider like [2] But why? I mean, it's not like it's the first time I'm asking this... If the issue is what Micheal described, then the divider has nothing to do with it. We've had that discussion over and over again. So you need to come with some argument and proof that the divider of that clock need to change. Otherwise, stop trying to make that happen: it won't. Maxime -- Maxime Ripard, Bootlin Embedded Linux and Kernel engineering https://bootlin.com --2dbototu7fqsblax-- From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D52B2C76188 for ; Sat, 20 Jul 2019 09:32:25 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id AABEB20873 for ; Sat, 20 Jul 2019 09:32:25 +0000 (UTC) Authentication-Results: mail.kernel.org; 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Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.92 #3 (Red Hat Linux)) id 1holj5-0006tw-Kk; Sat, 20 Jul 2019 09:32:23 +0000 Received: from relay3-d.mail.gandi.net ([217.70.183.195]) by bombadil.infradead.org with esmtps (Exim 4.92 #3 (Red Hat Linux)) id 1holj1-0006tE-NB for linux-arm-kernel@lists.infradead.org; Sat, 20 Jul 2019 09:32:21 +0000 X-Originating-IP: 91.163.65.175 Received: from localhost (91-163-65-175.subs.proxad.net [91.163.65.175]) (Authenticated sender: maxime.ripard@bootlin.com) by relay3-d.mail.gandi.net (Postfix) with ESMTPSA id 1A5FF60002; Sat, 20 Jul 2019 09:32:02 +0000 (UTC) Date: Sat, 20 Jul 2019 11:32:02 +0200 From: Maxime Ripard To: Jagan Teki Subject: Re: [PATCH v6 11/22] clk: sunxi-ng: a64: Add minimum rate for PLL_MIPI Message-ID: <20190720093202.6fn6xmhvsgawscnu@flea> References: <20190614142406.ybdiqfppo5mc5bgq@flea> <20190625144930.5hegt6bkzqzykjid@flea> <20190703114933.u3x4ej3v7ocewvif@flea> <20190711100100.cty3s6rs3w27low6@flea> <20190720065830.zn3txpyduakywcva@flea> MIME-Version: 1.0 In-Reply-To: User-Agent: NeoMutt/20180716 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190720_023220_074172_E85A70A6 X-CRM114-Status: GOOD ( 27.96 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , devicetree , David Airlie , Michael Turquette , linux-sunxi , linux-kernel , dri-devel , Chen-Yu Tsai , Rob Herring , Daniel Vetter , Michael Nazzareno Trimarchi , linux-amarula , linux-clk , linux-arm-kernel Content-Type: multipart/mixed; boundary="===============8140124772473344484==" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org --===============8140124772473344484== Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="2dbototu7fqsblax" Content-Disposition: inline --2dbototu7fqsblax Content-Type: text/plain; charset=us-ascii Content-Disposition: inline On Sat, Jul 20, 2019 at 12:46:27PM +0530, Jagan Teki wrote: > On Sat, Jul 20, 2019 at 12:28 PM Maxime Ripard > wrote: > > > > On Thu, Jul 11, 2019 at 07:43:16PM +0200, Michael Nazzareno Trimarchi wrote: > > > > > tcon-pixel clock is the rate that you want to achive on display side > > > > > and if you have 4 lanes 32bit or lanes and different bit number that > > > > > you need to have a clock that is able to put outside bits and speed > > > > > equal to pixel-clock * bits / lanes. so If you want a pixel-clock of > > > > > 40 mhz and you have 32bits and 4 lanes you need to have a clock of > > > > > 40 * 32 / 4 in no-burst mode. I think that this is done but most of > > > > > the display. > > > > > > > > So this is what the issue is then? > > > > > > > > This one does make sense, and you should just change the rate in the > > > > call to clk_set_rate in sun4i_tcon0_mode_set_cpu. > > > > > > > > I'm still wondering why that hasn't been brought up in either the > > > > discussion or the commit log before though. > > > > > > > Something like this? > > > > > > drivers/gpu/drm/sun4i/sun4i_tcon.c | 20 +++++++++++--------- > > > drivers/gpu/drm/sun4i/sun6i_mipi_dsi.h | 2 -- > > > 2 files changed, 11 insertions(+), 11 deletions(-) > > > > > > diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.c > > > b/drivers/gpu/drm/sun4i/sun4i_tcon.c > > > index 64c43ee6bd92..42560d5c327c 100644 > > > --- a/drivers/gpu/drm/sun4i/sun4i_tcon.c > > > +++ b/drivers/gpu/drm/sun4i/sun4i_tcon.c > > > @@ -263,10 +263,11 @@ static int sun4i_tcon_get_clk_delay(const struct > > > drm_display_mode *mode, > > > } > > > > > > static void sun4i_tcon0_mode_set_common(struct sun4i_tcon *tcon, > > > - const struct drm_display_mode *mode) > > > + const struct drm_display_mode *mode, > > > + u32 tcon_mul) > > > { > > > /* Configure the dot clock */ > > > - clk_set_rate(tcon->dclk, mode->crtc_clock * 1000); > > > + clk_set_rate(tcon->dclk, mode->crtc_clock * tcon_mul * 1000); > > > > > > /* Set the resolution */ > > > regmap_write(tcon->regs, SUN4I_TCON0_BASIC0_REG, > > > @@ -335,12 +336,13 @@ static void sun4i_tcon0_mode_set_cpu(struct > > > sun4i_tcon *tcon, > > > u8 bpp = mipi_dsi_pixel_format_to_bpp(device->format); > > > u8 lanes = device->lanes; > > > u32 block_space, start_delay; > > > - u32 tcon_div; > > > + u32 tcon_div, tcon_mul; > > > > > > - tcon->dclk_min_div = SUN6I_DSI_TCON_DIV; > > > - tcon->dclk_max_div = SUN6I_DSI_TCON_DIV; > > > + tcon->dclk_min_div = 4; > > > + tcon->dclk_max_div = 127; > > > > > > - sun4i_tcon0_mode_set_common(tcon, mode); > > > + tcon_mul = bpp / lanes; > > > + sun4i_tcon0_mode_set_common(tcon, mode, tcon_mul); > > > > > > /* Set dithering if needed */ > > > sun4i_tcon0_mode_set_dithering(tcon, sun4i_tcon_get_connector(encoder)); > > > @@ -366,7 +368,7 @@ static void sun4i_tcon0_mode_set_cpu(struct > > > sun4i_tcon *tcon, > > > */ > > > regmap_read(tcon->regs, SUN4I_TCON0_DCLK_REG, &tcon_div); > > > tcon_div &= GENMASK(6, 0); > > > - block_space = mode->htotal * bpp / (tcon_div * lanes); > > > + block_space = mode->htotal * tcon_div * tcon_mul; > > > block_space -= mode->hdisplay + 40; > > > > > > regmap_write(tcon->regs, SUN4I_TCON0_CPU_TRI0_REG, > > > @@ -408,7 +410,7 @@ static void sun4i_tcon0_mode_set_lvds(struct > > > sun4i_tcon *tcon, > > > > > > tcon->dclk_min_div = 7; > > > tcon->dclk_max_div = 7; > > > - sun4i_tcon0_mode_set_common(tcon, mode); > > > + sun4i_tcon0_mode_set_common(tcon, mode, 1); > > > > > > /* Set dithering if needed */ > > > sun4i_tcon0_mode_set_dithering(tcon, sun4i_tcon_get_connector(encoder)); > > > @@ -487,7 +489,7 @@ static void sun4i_tcon0_mode_set_rgb(struct > > > sun4i_tcon *tcon, > > > > > > tcon->dclk_min_div = 6; > > > tcon->dclk_max_div = 127; > > > - sun4i_tcon0_mode_set_common(tcon, mode); > > > + sun4i_tcon0_mode_set_common(tcon, mode, 1); > > > > > > /* Set dithering if needed */ > > > sun4i_tcon0_mode_set_dithering(tcon, connector); > > > diff --git a/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.h > > > b/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.h > > > index 5c3ad5be0690..a07090579f84 100644 > > > --- a/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.h > > > +++ b/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.h > > > @@ -13,8 +13,6 @@ > > > #include > > > #include > > > > > > -#define SUN6I_DSI_TCON_DIV 4 > > > - > > > struct sun6i_dsi { > > > struct drm_connector connector; > > > struct drm_encoder encoder; > > > > I had more something like this in mind: > > http://code.bulix.org/nlp5a4-803511 > > Worth to look at it. was it working on your panel? meanwhile I will check it. I haven't tested it. > We have updated with below change [1], seems working on but is > actually checking the each divider as before start with 4... till 127. > > This new approach, is start looking the best divider from 4.. based on > the idea vs rounded it will ended up best divider like [2] But why? I mean, it's not like it's the first time I'm asking this... If the issue is what Micheal described, then the divider has nothing to do with it. We've had that discussion over and over again. So you need to come with some argument and proof that the divider of that clock need to change. Otherwise, stop trying to make that happen: it won't. Maxime -- Maxime Ripard, Bootlin Embedded Linux and Kernel engineering https://bootlin.com --2dbototu7fqsblax Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iHUEABYIAB0WIQRcEzekXsqa64kGDp7j7w1vZxhRxQUCXTLfkgAKCRDj7w1vZxhR xXluAP4vGeqsFx22zqCbCazkSqNBlJ1xlo7FG4cHnv34XdrozgEAwDmJm2HpOFaV KgsjKFHWq3QK4YYxA3/WinhP6mxyVg8= =VKsI -----END PGP SIGNATURE----- --2dbototu7fqsblax-- --===============8140124772473344484== Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Disposition: inline _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel --===============8140124772473344484==--