From mboxrd@z Thu Jan 1 00:00:00 1970 From: Peter De Schrijver Subject: Re: [PATCH v2 1/2] soc/tegra: pmc: Query PCLK clock rate at probe time Date: Thu, 25 Jul 2019 12:36:45 +0300 Message-ID: <20190725093644.GJ12715@pdeschrijver-desktop.Nvidia.com> References: <20190723023511.24542-1-digetx@gmail.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Return-path: Content-Disposition: inline In-Reply-To: <20190723023511.24542-1-digetx@gmail.com> Sender: linux-kernel-owner@vger.kernel.org To: Dmitry Osipenko Cc: Thierry Reding , Jonathan Hunter , linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org List-Id: linux-tegra@vger.kernel.org On Tue, Jul 23, 2019 at 05:35:10AM +0300, Dmitry Osipenko wrote: > The PCLK clock is running off SCLK, which is a critical clock that is > very unlikely to randomly change its rate. It's also a bit clumsy (and > apparently incorrect) to query the clock's rate with interrupts being > disabled because clk_get_rate() takes a mutex and that's the case during > suspend/cpuidle entering. > SCLK and PCLK certainly can change rate at runtime, although the code to handle this hasn't reached upstream yet. Peter. > Signed-off-by: Dmitry Osipenko > --- > > Changelog: > > v2: Addressed review comments that were made by Jon Hunter to v1 by > not moving the memory barrier, replacing one missed clk_get_rate() > with pmc->rate, handling possible clk_get_rate() error on probe and > slightly adjusting the commits message. > > drivers/soc/tegra/pmc.c | 34 ++++++++++++++++------------------ > 1 file changed, 16 insertions(+), 18 deletions(-) > > diff --git a/drivers/soc/tegra/pmc.c b/drivers/soc/tegra/pmc.c > index 9f9c1c677cf4..aba3396b2e73 100644 > --- a/drivers/soc/tegra/pmc.c > +++ b/drivers/soc/tegra/pmc.c > @@ -1192,7 +1192,7 @@ static int tegra_io_pad_prepare(struct tegra_pmc *pmc, enum tegra_io_pad id, > return err; > > if (pmc->clk) { > - rate = clk_get_rate(pmc->clk); > + rate = pmc->rate; > if (!rate) { > dev_err(pmc->dev, "failed to get clock rate\n"); > return -ENODEV; > @@ -1433,6 +1433,7 @@ void tegra_pmc_set_suspend_mode(enum tegra_suspend_mode mode) > void tegra_pmc_enter_suspend_mode(enum tegra_suspend_mode mode) > { > unsigned long long rate = 0; > + u64 ticks; > u32 value; > > switch (mode) { > @@ -1441,31 +1442,22 @@ void tegra_pmc_enter_suspend_mode(enum tegra_suspend_mode mode) > break; > > case TEGRA_SUSPEND_LP2: > - rate = clk_get_rate(pmc->clk); > + rate = pmc->rate; > break; > > default: > break; > } > > - if (WARN_ON_ONCE(rate == 0)) > - rate = 100000000; > + ticks = pmc->cpu_good_time * rate + USEC_PER_SEC - 1; > + do_div(ticks, USEC_PER_SEC); > + tegra_pmc_writel(pmc, ticks, PMC_CPUPWRGOOD_TIMER); > > - if (rate != pmc->rate) { > - u64 ticks; > + ticks = pmc->cpu_off_time * rate + USEC_PER_SEC - 1; > + do_div(ticks, USEC_PER_SEC); > + tegra_pmc_writel(pmc, ticks, PMC_CPUPWROFF_TIMER); > > - ticks = pmc->cpu_good_time * rate + USEC_PER_SEC - 1; > - do_div(ticks, USEC_PER_SEC); > - tegra_pmc_writel(pmc, ticks, PMC_CPUPWRGOOD_TIMER); > - > - ticks = pmc->cpu_off_time * rate + USEC_PER_SEC - 1; > - do_div(ticks, USEC_PER_SEC); > - tegra_pmc_writel(pmc, ticks, PMC_CPUPWROFF_TIMER); > - > - wmb(); > - > - pmc->rate = rate; > - } > + wmb(); > > value = tegra_pmc_readl(pmc, PMC_CNTRL); > value &= ~PMC_CNTRL_SIDE_EFFECT_LP0; > @@ -2082,8 +2074,14 @@ static int tegra_pmc_probe(struct platform_device *pdev) > pmc->clk = NULL; > } > > + pmc->rate = clk_get_rate(pmc->clk); > pmc->dev = &pdev->dev; > > + if (!pmc->rate) { > + dev_err(&pdev->dev, "failed to get pclk rate\n"); > + pmc->rate = 100000000; > + } > + > tegra_pmc_init(pmc); > > tegra_pmc_init_tsense_reset(pmc); > -- > 2.22.0 > From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.4 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id CD28EC7618B for ; Thu, 25 Jul 2019 09:39:08 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 8E64222ADA for ; Thu, 25 Jul 2019 09:39:08 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=nvidia.com header.i=@nvidia.com header.b="fPKwjp/l" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2390613AbfGYJjH (ORCPT ); Thu, 25 Jul 2019 05:39:07 -0400 Received: from hqemgate14.nvidia.com ([216.228.121.143]:15441 "EHLO hqemgate14.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2387533AbfGYJjH (ORCPT ); Thu, 25 Jul 2019 05:39:07 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate14.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Thu, 25 Jul 2019 02:39:05 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Thu, 25 Jul 2019 02:39:04 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Thu, 25 Jul 2019 02:39:04 -0700 Received: from tbergstrom-lnx.Nvidia.com (172.20.13.39) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Thu, 25 Jul 2019 09:36:47 +0000 Received: by tbergstrom-lnx.Nvidia.com (Postfix, from userid 1000) id 0DD6B4286D; Thu, 25 Jul 2019 12:36:45 +0300 (EEST) Date: Thu, 25 Jul 2019 12:36:45 +0300 From: Peter De Schrijver To: Dmitry Osipenko CC: Thierry Reding , Jonathan Hunter , , Subject: Re: [PATCH v2 1/2] soc/tegra: pmc: Query PCLK clock rate at probe time Message-ID: <20190725093644.GJ12715@pdeschrijver-desktop.Nvidia.com> References: <20190723023511.24542-1-digetx@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: <20190723023511.24542-1-digetx@gmail.com> X-NVConfidentiality: public User-Agent: Mutt/1.9.4 (2018-02-28) X-Originating-IP: [172.20.13.39] X-ClientProxiedBy: HQMAIL107.nvidia.com (172.20.187.13) To HQMAIL107.nvidia.com (172.20.187.13) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1564047545; bh=z/b91Cml6zDC1P2RGluPj308VR8sVHX0e0iaWNpGUCs=; h=X-PGP-Universal:Date:From:To:CC:Subject:Message-ID:References: MIME-Version:Content-Type:Content-Disposition:In-Reply-To: X-NVConfidentiality:User-Agent:X-Originating-IP:X-ClientProxiedBy; b=fPKwjp/lRhsKdu+dBZO6pu8ZZPEt5vCY9FkwWVxvN4RWBwU0Id0Anbl/+gCFgNfSQ Abm09WhkGCW4pJZKM9JoEd74VuxajQDQ1VKMMtXOXwrGoDR5uIcx5uFGSaoVyHZjKR bMh01N4dO0qp6hGp5bTjZ0m9Cr5cDKDd4lTZYGENZmMVKD9vpw3OCNlxguNOWDUVOo 65+eG+Xonm9gV3qd+wAQBUrfJOkVCcNugt7I1NuNXXEG5VGhCe5A/1I2rpvVXZXlsx hMMVjKAadz9ZPNPsXPGgwxQmp7PRNkCjnh1MILJVatPox8hfkWZlSwq82osKtjETR9 DCkkxL21RYsgQ== Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, Jul 23, 2019 at 05:35:10AM +0300, Dmitry Osipenko wrote: > The PCLK clock is running off SCLK, which is a critical clock that is > very unlikely to randomly change its rate. It's also a bit clumsy (and > apparently incorrect) to query the clock's rate with interrupts being > disabled because clk_get_rate() takes a mutex and that's the case during > suspend/cpuidle entering. > SCLK and PCLK certainly can change rate at runtime, although the code to handle this hasn't reached upstream yet. Peter. > Signed-off-by: Dmitry Osipenko > --- > > Changelog: > > v2: Addressed review comments that were made by Jon Hunter to v1 by > not moving the memory barrier, replacing one missed clk_get_rate() > with pmc->rate, handling possible clk_get_rate() error on probe and > slightly adjusting the commits message. > > drivers/soc/tegra/pmc.c | 34 ++++++++++++++++------------------ > 1 file changed, 16 insertions(+), 18 deletions(-) > > diff --git a/drivers/soc/tegra/pmc.c b/drivers/soc/tegra/pmc.c > index 9f9c1c677cf4..aba3396b2e73 100644 > --- a/drivers/soc/tegra/pmc.c > +++ b/drivers/soc/tegra/pmc.c > @@ -1192,7 +1192,7 @@ static int tegra_io_pad_prepare(struct tegra_pmc *pmc, enum tegra_io_pad id, > return err; > > if (pmc->clk) { > - rate = clk_get_rate(pmc->clk); > + rate = pmc->rate; > if (!rate) { > dev_err(pmc->dev, "failed to get clock rate\n"); > return -ENODEV; > @@ -1433,6 +1433,7 @@ void tegra_pmc_set_suspend_mode(enum tegra_suspend_mode mode) > void tegra_pmc_enter_suspend_mode(enum tegra_suspend_mode mode) > { > unsigned long long rate = 0; > + u64 ticks; > u32 value; > > switch (mode) { > @@ -1441,31 +1442,22 @@ void tegra_pmc_enter_suspend_mode(enum tegra_suspend_mode mode) > break; > > case TEGRA_SUSPEND_LP2: > - rate = clk_get_rate(pmc->clk); > + rate = pmc->rate; > break; > > default: > break; > } > > - if (WARN_ON_ONCE(rate == 0)) > - rate = 100000000; > + ticks = pmc->cpu_good_time * rate + USEC_PER_SEC - 1; > + do_div(ticks, USEC_PER_SEC); > + tegra_pmc_writel(pmc, ticks, PMC_CPUPWRGOOD_TIMER); > > - if (rate != pmc->rate) { > - u64 ticks; > + ticks = pmc->cpu_off_time * rate + USEC_PER_SEC - 1; > + do_div(ticks, USEC_PER_SEC); > + tegra_pmc_writel(pmc, ticks, PMC_CPUPWROFF_TIMER); > > - ticks = pmc->cpu_good_time * rate + USEC_PER_SEC - 1; > - do_div(ticks, USEC_PER_SEC); > - tegra_pmc_writel(pmc, ticks, PMC_CPUPWRGOOD_TIMER); > - > - ticks = pmc->cpu_off_time * rate + USEC_PER_SEC - 1; > - do_div(ticks, USEC_PER_SEC); > - tegra_pmc_writel(pmc, ticks, PMC_CPUPWROFF_TIMER); > - > - wmb(); > - > - pmc->rate = rate; > - } > + wmb(); > > value = tegra_pmc_readl(pmc, PMC_CNTRL); > value &= ~PMC_CNTRL_SIDE_EFFECT_LP0; > @@ -2082,8 +2074,14 @@ static int tegra_pmc_probe(struct platform_device *pdev) > pmc->clk = NULL; > } > > + pmc->rate = clk_get_rate(pmc->clk); > pmc->dev = &pdev->dev; > > + if (!pmc->rate) { > + dev_err(&pdev->dev, "failed to get pclk rate\n"); > + pmc->rate = 100000000; > + } > + > tegra_pmc_init(pmc); > > tegra_pmc_init_tsense_reset(pmc); > -- > 2.22.0 >