From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-3.8 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 190EAC7618F for ; Fri, 26 Jul 2019 18:40:59 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id E0CE422BEF for ; Fri, 26 Jul 2019 18:40:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2387845AbfGZSk6 (ORCPT ); Fri, 26 Jul 2019 14:40:58 -0400 Received: from mailoutvs25.siol.net ([185.57.226.216]:54746 "EHLO mail.siol.net" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S2387434AbfGZSk5 (ORCPT ); Fri, 26 Jul 2019 14:40:57 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.siol.net (Postfix) with ESMTP id 3F180522DEC; Fri, 26 Jul 2019 20:40:54 +0200 (CEST) X-Virus-Scanned: amavisd-new at psrvmta10.zcs-production.pri Received: from mail.siol.net ([127.0.0.1]) by localhost (psrvmta10.zcs-production.pri [127.0.0.1]) (amavisd-new, port 10032) with ESMTP id haV3ghgp1HtG; Fri, 26 Jul 2019 20:40:54 +0200 (CEST) Received: from mail.siol.net (localhost [127.0.0.1]) by mail.siol.net (Postfix) with ESMTPS id E644D523034; Fri, 26 Jul 2019 20:40:53 +0200 (CEST) Received: from localhost.localdomain (cpe-194-152-11-237.cable.triera.net [194.152.11.237]) (Authenticated sender: 031275009) by mail.siol.net (Postfix) with ESMTPSA id 313BA522DEC; Fri, 26 Jul 2019 20:40:52 +0200 (CEST) From: Jernej Skrabec To: thierry.reding@gmail.com, mripard@kernel.org, wens@csie.org Cc: robh+dt@kernel.org, mark.rutland@arm.com, linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-sunxi@googlegroups.com Subject: [PATCH 0/6] pwm: sun4i: Add support for Allwinner H6 Date: Fri, 26 Jul 2019 20:40:39 +0200 Message-Id: <20190726184045.14669-1-jernej.skrabec@siol.net> X-Mailer: git-send-email 2.22.0 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Allwinner H6 SoC has PWM core which is basically the same as that found in A20, it's just depends on additional bus clock and reset line. This series adds support for it and extends PWM driver functionality in a way that it's now possible to bypass whole core and output PWM source clock directly as a PWM signal. This functionality is needed by AC200 chip, which is bundled in same physical package as H6 SoC, to serve as a clock source of 24 MHz. AC200 clock input pin is bonded internally to the second PWM channel. I would be grateful if anyone can test this patch series for any kind of regression on other SoCs. Please take a look. Best regards, Jernej Jernej Skrabec (6): dt-bindings: pwm: allwinner: Add H6 PWM description pwm: sun4i: Add a quirk for reset line pwm: sun4i: Add a quirk for bus clock pwm: sun4i: Add support for H6 PWM pwm: sun4i: Add support to output source clock directly arm64: dts: allwinner: h6: Add PWM node .../bindings/pwm/allwinner,sun4i-a10-pwm.yaml | 36 +++++++- arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 10 +++ drivers/pwm/pwm-sun4i.c | 83 ++++++++++++++++++- 3 files changed, 125 insertions(+), 4 deletions(-) --=20 2.22.0 From mboxrd@z Thu Jan 1 00:00:00 1970 From: Jernej Skrabec Subject: [PATCH 0/6] pwm: sun4i: Add support for Allwinner H6 Date: Fri, 26 Jul 2019 20:40:39 +0200 Message-ID: <20190726184045.14669-1-jernej.skrabec@siol.net> Reply-To: jernej.skrabec-gGgVlfcn5nU@public.gmane.org Mime-Version: 1.0 Content-Type: text/plain; charset="UTF-8" Return-path: Sender: linux-sunxi-/JYPxA39Uh5TLH3MbocFFw@public.gmane.org List-Post: , List-Help: , List-Archive: , List-Unsubscribe: , To: thierry.reding-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org, mripard-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org, wens-jdAy2FN1RRM@public.gmane.org Cc: robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org, mark.rutland-5wv7dgnIgG8@public.gmane.org, linux-pwm-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org, linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-sunxi-/JYPxA39Uh5TLH3MbocFFw@public.gmane.org List-Id: devicetree@vger.kernel.org Allwinner H6 SoC has PWM core which is basically the same as that found in A20, it's just depends on additional bus clock and reset line. This series adds support for it and extends PWM driver functionality in a way that it's now possible to bypass whole core and output PWM source clock directly as a PWM signal. This functionality is needed by AC200 chip, which is bundled in same physical package as H6 SoC, to serve as a clock source of 24 MHz. AC200 clock input pin is bonded internally to the second PWM channel. I would be grateful if anyone can test this patch series for any kind of regression on other SoCs. Please take a look. Best regards, Jernej Jernej Skrabec (6): dt-bindings: pwm: allwinner: Add H6 PWM description pwm: sun4i: Add a quirk for reset line pwm: sun4i: Add a quirk for bus clock pwm: sun4i: Add support for H6 PWM pwm: sun4i: Add support to output source clock directly arm64: dts: allwinner: h6: Add PWM node .../bindings/pwm/allwinner,sun4i-a10-pwm.yaml | 36 +++++++- arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 10 +++ drivers/pwm/pwm-sun4i.c | 83 ++++++++++++++++++- 3 files changed, 125 insertions(+), 4 deletions(-) -- 2.22.0 From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-3.8 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_HELO_NONE, SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D55AFC76191 for ; Fri, 26 Jul 2019 18:41:19 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id AA3A322C7E for ; Fri, 26 Jul 2019 18:41:19 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="UzRXpUBS" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org AA3A322C7E Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=siol.net Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:Message-Id:Date:Subject:To :From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References: List-Owner; bh=94vtlXYlzJqhItg93wrIj2UZ/zV3L47fDTUT1LLURR0=; b=UzRXpUBSnDSq1o uHSte++pOLgjFj/6azRVcVypBF41EkrIR/8aXrlW9luGK08dNlothv1yafs/Rp1hk+OieEY0PeEvd nuZpZ3IEfcjpCirzSnIr1ZUIFe6JQS9End+CkgYEr4bnAL7kh6Pbdm7y8p2KQ8y8ufmdBj9M8lzrS AktFPgi8IiP9EiCbHWpJuxtx4rKF3EDk+vBgk6mPBWtumLshovF2Ne12BUcElynobun2SCOxSUn2g U/N2obftMdSLjbLUNGYb5pfy2QU09kl0BO5Ji/pke9Iqe0UDBz/mxK57nTRBhbAoGFZOKoByPol/a Me3bozBNIJhITPOy/jgQ==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.92 #3 (Red Hat Linux)) id 1hr59b-0003nM-0s; Fri, 26 Jul 2019 18:41:19 +0000 Received: from mailoutvs3.siol.net ([185.57.226.194] helo=mail.siol.net) by bombadil.infradead.org with esmtps (Exim 4.92 #3 (Red Hat Linux)) id 1hr59K-0003VZ-Tp for linux-arm-kernel@lists.infradead.org; Fri, 26 Jul 2019 18:41:04 +0000 Received: from localhost (localhost [127.0.0.1]) by mail.siol.net (Postfix) with ESMTP id 3F180522DEC; Fri, 26 Jul 2019 20:40:54 +0200 (CEST) X-Virus-Scanned: amavisd-new at psrvmta10.zcs-production.pri Received: from mail.siol.net ([127.0.0.1]) by localhost (psrvmta10.zcs-production.pri [127.0.0.1]) (amavisd-new, port 10032) with ESMTP id haV3ghgp1HtG; Fri, 26 Jul 2019 20:40:54 +0200 (CEST) Received: from mail.siol.net (localhost [127.0.0.1]) by mail.siol.net (Postfix) with ESMTPS id E644D523034; Fri, 26 Jul 2019 20:40:53 +0200 (CEST) Received: from localhost.localdomain (cpe-194-152-11-237.cable.triera.net [194.152.11.237]) (Authenticated sender: 031275009) by mail.siol.net (Postfix) with ESMTPSA id 313BA522DEC; Fri, 26 Jul 2019 20:40:52 +0200 (CEST) From: Jernej Skrabec To: thierry.reding@gmail.com, mripard@kernel.org, wens@csie.org Subject: [PATCH 0/6] pwm: sun4i: Add support for Allwinner H6 Date: Fri, 26 Jul 2019 20:40:39 +0200 Message-Id: <20190726184045.14669-1-jernej.skrabec@siol.net> X-Mailer: git-send-email 2.22.0 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190726_114103_122556_03E3F380 X-CRM114-Status: UNSURE ( 9.92 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mark.rutland@arm.com, linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-sunxi@googlegroups.com, robh+dt@kernel.org, linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org Allwinner H6 SoC has PWM core which is basically the same as that found in A20, it's just depends on additional bus clock and reset line. This series adds support for it and extends PWM driver functionality in a way that it's now possible to bypass whole core and output PWM source clock directly as a PWM signal. This functionality is needed by AC200 chip, which is bundled in same physical package as H6 SoC, to serve as a clock source of 24 MHz. AC200 clock input pin is bonded internally to the second PWM channel. I would be grateful if anyone can test this patch series for any kind of regression on other SoCs. Please take a look. Best regards, Jernej Jernej Skrabec (6): dt-bindings: pwm: allwinner: Add H6 PWM description pwm: sun4i: Add a quirk for reset line pwm: sun4i: Add a quirk for bus clock pwm: sun4i: Add support for H6 PWM pwm: sun4i: Add support to output source clock directly arm64: dts: allwinner: h6: Add PWM node .../bindings/pwm/allwinner,sun4i-a10-pwm.yaml | 36 +++++++- arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 10 +++ drivers/pwm/pwm-sun4i.c | 83 ++++++++++++++++++- 3 files changed, 125 insertions(+), 4 deletions(-) -- 2.22.0 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel