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From: Anshuman Gupta <anshuman.gupta@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: Deak@freedesktop.org, jani.nikula@intel.com,
	Nikula@freedesktop.org, Manna@freedesktop.org
Subject: [PATCH v3 1/9] drm/i915/tgl: Add DC3CO required register and bits
Date: Tue, 30 Jul 2019 19:20:16 +0530	[thread overview]
Message-ID: <20190730135024.31765-2-anshuman.gupta@intel.com> (raw)
In-Reply-To: <20190730135024.31765-1-anshuman.gupta@intel.com>

Adding following definition to i915_reg.h
1. DC_STATE_EN register DC3CO bit fields and masks.
2. Transcoder EXITLINE register and its bit fields and mask.

Cc: Nikula, Jani <jani.nikula@intel.com>
Cc: Deak, Imre <imre.deak@intel.com>
Cc: Manna, Animesh <animesh.manna@intel.com>
Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index d2b76121d863..d42e95da5b14 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4195,6 +4195,7 @@ enum {
 #define _VTOTAL_A	0x6000c
 #define _VBLANK_A	0x60010
 #define _VSYNC_A	0x60014
+#define _EXITLINE_A	0x60018
 #define _PIPEASRC	0x6001c
 #define _BCLRPAT_A	0x60020
 #define _VSYNCSHIFT_A	0x60028
@@ -4241,11 +4242,16 @@ enum {
 #define VTOTAL(trans)		_MMIO_TRANS2(trans, _VTOTAL_A)
 #define VBLANK(trans)		_MMIO_TRANS2(trans, _VBLANK_A)
 #define VSYNC(trans)		_MMIO_TRANS2(trans, _VSYNC_A)
+#define EXITLINE(trans)		_MMIO_TRANS2(trans, _EXITLINE_A)
 #define BCLRPAT(trans)		_MMIO_TRANS2(trans, _BCLRPAT_A)
 #define VSYNCSHIFT(trans)	_MMIO_TRANS2(trans, _VSYNCSHIFT_A)
 #define PIPESRC(trans)		_MMIO_TRANS2(trans, _PIPEASRC)
 #define PIPE_MULT(trans)	_MMIO_TRANS2(trans, _PIPE_MULT_A)
 
+#define  EXITLINE_ENABLE	(1 << 31)
+#define  EXITLINE_MASK		(0x1fff)
+#define  EXITLINE_SHIFT		0
+
 /* HSW+ eDP PSR registers */
 #define HSW_EDP_PSR_BASE	0x64800
 #define BDW_EDP_PSR_BASE	0x6f800
@@ -9996,6 +10002,8 @@ enum skl_power_gate {
 /* GEN9 DC */
 #define DC_STATE_EN			_MMIO(0x45504)
 #define  DC_STATE_DISABLE		0
+#define  DC_STATE_EN_DC3CO		(1 << 30)
+#define  DC_STATE_DC3CO_STATUS		(1 << 29)
 #define  DC_STATE_EN_UPTO_DC5		(1 << 0)
 #define  DC_STATE_EN_DC9		(1 << 3)
 #define  DC_STATE_EN_UPTO_DC6		(2 << 0)
-- 
2.21.0

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  reply	other threads:[~2019-07-30 13:54 UTC|newest]

Thread overview: 16+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-07-30 13:50 [PATCH v3 0/9] DC3CO Support for TGL Anshuman Gupta
2019-07-30 13:50 ` Anshuman Gupta [this message]
2019-08-01  4:23   ` [PATCH v3 1/9] drm/i915/tgl: Add DC3CO required register and bits Animesh Manna
2019-07-30 13:50 ` [PATCH v3 2/9] drm/i915/tgl: Add DC3CO mask to allowed_dc_mask and gen9_dc_mask Anshuman Gupta
2019-08-01  4:35   ` Animesh Manna
2019-07-30 13:50 ` [PATCH v3 3/9] drm/i915/tgl: Add power well to enable DC3CO state Anshuman Gupta
2019-07-30 13:50 ` [PATCH v3 4/9] drm/i915/tgl: mutual exclusive handling for DC3CO and DC5/6 Anshuman Gupta
2019-07-30 13:50 ` [PATCH v3 5/9] drm/i915/tgl: Add helper function to prefer dc3co over dc5 Anshuman Gupta
2019-07-30 13:50 ` [PATCH v3 6/9] drm/i915/tgl: Add VIDEO power domain Anshuman Gupta
2019-07-30 13:50 ` [PATCH v3 7/9] drm/i915/tgl: DC3CO PSR2 helper Anshuman Gupta
2019-07-31  7:11   ` kbuild test robot
2019-07-30 13:50 ` [PATCH v3 8/9] drm/i915/tgl: switch between dc3co and dc5 based on display idleness Anshuman Gupta
2019-07-30 13:50 ` [PATCH v3 9/9] drm/i915/tgl: Add DC3CO counter in i915_dmc_info Anshuman Gupta
2019-07-30 14:23 ` ✗ Fi.CI.SPARSE: warning for DC3CO Support for TGL Patchwork
2019-07-30 14:41 ` ✓ Fi.CI.BAT: success " Patchwork
2019-07-31  0:37 ` ✓ Fi.CI.IGT: " Patchwork

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