Re: [PATCH] arm64: sysreg: Remove unused and rotting SCTLR_ELx field definitions

[Mark Rutland <mark.rutland@arm.com>]

On Tue, Jul 30, 2019 at 03:41:21PM +0100, Will Deacon wrote:
> Our SCTLR_ELx field definitions are somewhat over-engineered in that
> they carefully define masks describing the RES0/RES1 bits and then use
> these to construct further masks representing bits to be set/cleared for
> the _EL1 and _EL2 registers.
> 
> However, most of the resulting definitions aren't actually used by
> anybody and have subsequently started to bit-rot when new fields have
> been added by the architecture, resulting in fields being part of the
> RES0 mask despite being defined and used elsewhere.
> 
> Rather than fix up these masks, simply remove the unused parts entirely
> so that we can drop the maintenance burden. We can always add things
> back if we need them in the future.
> 
> Signed-off-by: Will Deacon <will@kernel.org>

I have no strong feelings either way, so FWIW:

Acked-by: Mark Rutland <mark.rutland@arm.com>

Mark.

> ---
>  arch/arm64/include/asm/sysreg.h | 29 -----------------------------
>  1 file changed, 29 deletions(-)
> 
> diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
> index 06ebcfef73df..1df45c7ffcf7 100644
> --- a/arch/arm64/include/asm/sysreg.h
> +++ b/arch/arm64/include/asm/sysreg.h
> @@ -499,28 +499,11 @@
>  #define SCTLR_EL2_RES1	((BIT(4))  | (BIT(5))  | (BIT(11)) | (BIT(16)) | \
>  			 (BIT(18)) | (BIT(22)) | (BIT(23)) | (BIT(28)) | \
>  			 (BIT(29)))
> -#define SCTLR_EL2_RES0	((BIT(6))  | (BIT(7))  | (BIT(8))  | (BIT(9))  | \
> -			 (BIT(10)) | (BIT(13)) | (BIT(14)) | (BIT(15)) | \
> -			 (BIT(17)) | (BIT(20)) | (BIT(24)) | (BIT(26)) | \
> -			 (BIT(27)) | (BIT(30)) | (BIT(31)) | \
> -			 (0xffffefffUL << 32))
>  
>  #ifdef CONFIG_CPU_BIG_ENDIAN
>  #define ENDIAN_SET_EL2		SCTLR_ELx_EE
> -#define ENDIAN_CLEAR_EL2	0
>  #else
>  #define ENDIAN_SET_EL2		0
> -#define ENDIAN_CLEAR_EL2	SCTLR_ELx_EE
> -#endif
> -
> -/* SCTLR_EL2 value used for the hyp-stub */
> -#define SCTLR_EL2_SET	(SCTLR_ELx_IESB   | ENDIAN_SET_EL2   | SCTLR_EL2_RES1)
> -#define SCTLR_EL2_CLEAR	(SCTLR_ELx_M      | SCTLR_ELx_A    | SCTLR_ELx_C   | \
> -			 SCTLR_ELx_SA     | SCTLR_ELx_I    | SCTLR_ELx_WXN | \
> -			 SCTLR_ELx_DSSBS | ENDIAN_CLEAR_EL2 | SCTLR_EL2_RES0)
> -
> -#if (SCTLR_EL2_SET ^ SCTLR_EL2_CLEAR) != 0xffffffffffffffffUL
> -#error "Inconsistent SCTLR_EL2 set/clear bits"
>  #endif
>  
>  /* SCTLR_EL1 specific flags. */
> @@ -539,16 +522,11 @@
>  
>  #define SCTLR_EL1_RES1	((BIT(11)) | (BIT(20)) | (BIT(22)) | (BIT(28)) | \
>  			 (BIT(29)))
> -#define SCTLR_EL1_RES0  ((BIT(6))  | (BIT(10)) | (BIT(13)) | (BIT(17)) | \
> -			 (BIT(27)) | (BIT(30)) | (BIT(31)) | \
> -			 (0xffffefffUL << 32))
>  
>  #ifdef CONFIG_CPU_BIG_ENDIAN
>  #define ENDIAN_SET_EL1		(SCTLR_EL1_E0E | SCTLR_ELx_EE)
> -#define ENDIAN_CLEAR_EL1	0
>  #else
>  #define ENDIAN_SET_EL1		0
> -#define ENDIAN_CLEAR_EL1	(SCTLR_EL1_E0E | SCTLR_ELx_EE)
>  #endif
>  
>  #define SCTLR_EL1_SET	(SCTLR_ELx_M    | SCTLR_ELx_C    | SCTLR_ELx_SA   |\
> @@ -556,13 +534,6 @@
>  			 SCTLR_EL1_DZE  | SCTLR_EL1_UCT                   |\
>  			 SCTLR_EL1_NTWE | SCTLR_ELx_IESB | SCTLR_EL1_SPAN |\
>  			 ENDIAN_SET_EL1 | SCTLR_EL1_UCI  | SCTLR_EL1_RES1)
> -#define SCTLR_EL1_CLEAR	(SCTLR_ELx_A   | SCTLR_EL1_CP15BEN | SCTLR_EL1_ITD    |\
> -			 SCTLR_EL1_UMA | SCTLR_ELx_WXN     | ENDIAN_CLEAR_EL1 |\
> -			 SCTLR_ELx_DSSBS | SCTLR_EL1_NTWI  | SCTLR_EL1_RES0)
> -
> -#if (SCTLR_EL1_SET ^ SCTLR_EL1_CLEAR) != 0xffffffffffffffffUL
> -#error "Inconsistent SCTLR_EL1 set/clear bits"
> -#endif
>  
>  /* id_aa64isar0 */
>  #define ID_AA64ISAR0_TS_SHIFT		52
> -- 
> 2.11.0
> 

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