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From: Stephen Boyd <sboyd@kernel.org>
To: Michael Turquette <mturquette@baylibre.com>,
	Stephen Boyd <sboyd@kernel.org>
Cc: linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org,
	Dinh Nguyen <dinguyen@kernel.org>
Subject: [PATCH 6/9] clk: socfpga: Don't reference clk_init_data after registration
Date: Wed, 31 Jul 2019 12:35:14 -0700	[thread overview]
Message-ID: <20190731193517.237136-7-sboyd@kernel.org> (raw)
In-Reply-To: <20190731193517.237136-1-sboyd@kernel.org>

A future patch is going to change semantics of clk_register() so that
clk_hw::init is guaranteed to be NULL after a clk is registered. Avoid
referencing this member here so that we don't run into NULL pointer
exceptions.

Cc: Dinh Nguyen <dinguyen@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
---

Please ack so I can take this through clk tree

 drivers/clk/socfpga/clk-gate.c       | 21 +++++++++++----------
 drivers/clk/socfpga/clk-periph-a10.c |  7 ++++---
 2 files changed, 15 insertions(+), 13 deletions(-)

diff --git a/drivers/clk/socfpga/clk-gate.c b/drivers/clk/socfpga/clk-gate.c
index 3966cd43b552..b3c8143909dc 100644
--- a/drivers/clk/socfpga/clk-gate.c
+++ b/drivers/clk/socfpga/clk-gate.c
@@ -31,20 +31,20 @@ static u8 socfpga_clk_get_parent(struct clk_hw *hwclk)
 	u32 l4_src;
 	u32 perpll_src;
 
-	if (streq(hwclk->init->name, SOCFPGA_L4_MP_CLK)) {
+	if (streq(name, SOCFPGA_L4_MP_CLK)) {
 		l4_src = readl(clk_mgr_base_addr + CLKMGR_L4SRC);
 		return l4_src &= 0x1;
 	}
-	if (streq(hwclk->init->name, SOCFPGA_L4_SP_CLK)) {
+	if (streq(name, SOCFPGA_L4_SP_CLK)) {
 		l4_src = readl(clk_mgr_base_addr + CLKMGR_L4SRC);
 		return !!(l4_src & 2);
 	}
 
 	perpll_src = readl(clk_mgr_base_addr + CLKMGR_PERPLL_SRC);
-	if (streq(hwclk->init->name, SOCFPGA_MMC_CLK))
+	if (streq(name, SOCFPGA_MMC_CLK))
 		return perpll_src &= 0x3;
-	if (streq(hwclk->init->name, SOCFPGA_NAND_CLK) ||
-			streq(hwclk->init->name, SOCFPGA_NAND_X_CLK))
+	if (streq(name, SOCFPGA_NAND_CLK) ||
+			streq(name, SOCFPGA_NAND_X_CLK))
 			return (perpll_src >> 2) & 3;
 
 	/* QSPI clock */
@@ -55,24 +55,25 @@ static u8 socfpga_clk_get_parent(struct clk_hw *hwclk)
 static int socfpga_clk_set_parent(struct clk_hw *hwclk, u8 parent)
 {
 	u32 src_reg;
+	const char *name = clk_hw_get_name(hwclk);
 
-	if (streq(hwclk->init->name, SOCFPGA_L4_MP_CLK)) {
+	if (streq(name, SOCFPGA_L4_MP_CLK)) {
 		src_reg = readl(clk_mgr_base_addr + CLKMGR_L4SRC);
 		src_reg &= ~0x1;
 		src_reg |= parent;
 		writel(src_reg, clk_mgr_base_addr + CLKMGR_L4SRC);
-	} else if (streq(hwclk->init->name, SOCFPGA_L4_SP_CLK)) {
+	} else if (streq(name, SOCFPGA_L4_SP_CLK)) {
 		src_reg = readl(clk_mgr_base_addr + CLKMGR_L4SRC);
 		src_reg &= ~0x2;
 		src_reg |= (parent << 1);
 		writel(src_reg, clk_mgr_base_addr + CLKMGR_L4SRC);
 	} else {
 		src_reg = readl(clk_mgr_base_addr + CLKMGR_PERPLL_SRC);
-		if (streq(hwclk->init->name, SOCFPGA_MMC_CLK)) {
+		if (streq(name, SOCFPGA_MMC_CLK)) {
 			src_reg &= ~0x3;
 			src_reg |= parent;
-		} else if (streq(hwclk->init->name, SOCFPGA_NAND_CLK) ||
-			streq(hwclk->init->name, SOCFPGA_NAND_X_CLK)) {
+		} else if (streq(name, SOCFPGA_NAND_CLK) ||
+			streq(name, SOCFPGA_NAND_X_CLK)) {
 			src_reg &= ~0xC;
 			src_reg |= (parent << 2);
 		} else {/* QSPI clock */
diff --git a/drivers/clk/socfpga/clk-periph-a10.c b/drivers/clk/socfpga/clk-periph-a10.c
index a8ff7229611d..3e0c55727b89 100644
--- a/drivers/clk/socfpga/clk-periph-a10.c
+++ b/drivers/clk/socfpga/clk-periph-a10.c
@@ -40,11 +40,12 @@ static u8 clk_periclk_get_parent(struct clk_hw *hwclk)
 {
 	struct socfpga_periph_clk *socfpgaclk = to_socfpga_periph_clk(hwclk);
 	u32 clk_src;
+	const char *name = clk_hw_get_name(hwclk);
 
 	clk_src = readl(socfpgaclk->hw.reg);
-	if (streq(hwclk->init->name, SOCFPGA_MPU_FREE_CLK) ||
-	    streq(hwclk->init->name, SOCFPGA_NOC_FREE_CLK) ||
-	    streq(hwclk->init->name, SOCFPGA_SDMMC_FREE_CLK))
+	if (streq(name, SOCFPGA_MPU_FREE_CLK) ||
+	    streq(name, SOCFPGA_NOC_FREE_CLK) ||
+	    streq(name, SOCFPGA_SDMMC_FREE_CLK))
 		return (clk_src >> CLK_MGR_FREE_SHIFT) &
 			CLK_MGR_FREE_MASK;
 	else
-- 
Sent by a computer through tubes


  parent reply	other threads:[~2019-07-31 19:35 UTC|newest]

Thread overview: 34+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-07-31 19:35 [PATCH 0/9] Make clk_hw::init NULL after clk registration Stephen Boyd
2019-07-31 19:35 ` [PATCH 1/9] clk: actions: Don't reference clk_init_data after registration Stephen Boyd
2019-08-03 12:48   ` Manivannan Sadhasivam
2019-08-14  0:24   ` Stephen Boyd
2019-08-16 11:22   ` Manivannan Sadhasivam
2019-08-16 14:50     ` Stephen Boyd
2019-07-31 19:35 ` [PATCH 2/9] clk: lochnagar: " Stephen Boyd
2019-08-01  8:07   ` Charles Keepax
2019-08-14  0:24   ` Stephen Boyd
2019-07-31 19:35 ` [PATCH 3/9] clk: meson: axg-audio: " Stephen Boyd
2019-07-31 19:53   ` Neil Armstrong
2019-08-06  8:49   ` Jerome Brunet
2019-08-06 21:48     ` Stephen Boyd
2019-08-07 13:57       ` Jerome Brunet
2019-08-14  0:24   ` Stephen Boyd
2019-07-31 19:35 ` [PATCH 4/9] clk: qcom: " Stephen Boyd
2019-08-04 17:49   ` Taniya Das
2019-08-14  0:24   ` Stephen Boyd
2019-07-31 19:35 ` [PATCH 5/9] clk: sirf: " Stephen Boyd
2019-08-14  0:25   ` Stephen Boyd
2019-07-31 19:35 ` Stephen Boyd [this message]
2019-08-01 15:12   ` [PATCH 6/9] clk: socfpga: " Dinh Nguyen
2019-08-01 16:13     ` Stephen Boyd
2019-08-14  0:25   ` Stephen Boyd
2019-07-31 19:35 ` [PATCH 7/9] clk: sprd: " Stephen Boyd
2019-08-01  7:41   ` Baolin Wang
2019-08-02  1:57   ` Chunyan Zhang
2019-08-14  0:25   ` Stephen Boyd
2019-07-31 19:35 ` [PATCH 8/9] phy: ti: am654-serdes: " Stephen Boyd
2019-08-02 12:45   ` Kishon Vijay Abraham I
2019-08-14  0:25   ` Stephen Boyd
2019-07-31 19:35 ` [PATCH 9/9] clk: Overwrite clk_hw::init with NULL during clk_register() Stephen Boyd
2019-08-08 16:14   ` Sylwester Nawrocki
2019-08-14  0:25   ` Stephen Boyd

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