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From: Lucas De Marchi <lucas.de.marchi@gmail.com>
To: "José Roberto de Souza" <jose.souza@intel.com>
Cc: Dhinakaran Pandiyan <dhinakaran.pandiya@intel.com>,
	intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH v7 2/4] drm/i915: Add _TRANS2()
Date: Tue, 6 Aug 2019 16:31:18 -0700	[thread overview]
Message-ID: <20190806233118.GB8519@ldmartin-desk1> (raw)
In-Reply-To: <20190730224753.14907-2-jose.souza@intel.com>

On Tue, Jul 30, 2019 at 03:47:51PM -0700, Jose Souza wrote:
>A new macro that is going to be added in a further patch will need to
>adjust the offset returned by _MMIO_TRANS2(), so here adding
>_TRANS2() and moving most of the implementation of _MMIO_TRANS2() to
>it and while at it taking the opportunity to rename pipe to trans.
>
>Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
>Cc: Dhinakaran Pandiyan <dhinakaran.pandiya@intel.com>
>Reviewed-by: Dhinakaran Pandiyan <dhinakaran.pandiya@intel.com>
>Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
>---
> drivers/gpu/drm/i915/i915_reg.h | 7 ++++---
> 1 file changed, 4 insertions(+), 3 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>index 21306dd3790a..f4e1acc936b3 100644
>--- a/drivers/gpu/drm/i915/i915_reg.h
>+++ b/drivers/gpu/drm/i915/i915_reg.h
>@@ -251,9 +251,10 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
> #define _MMIO_PIPE2(pipe, reg)		_MMIO(INTEL_INFO(dev_priv)->pipe_offsets[pipe] - \
> 					      INTEL_INFO(dev_priv)->pipe_offsets[PIPE_A] + (reg) + \
> 					      DISPLAY_MMIO_BASE(dev_priv))
>-#define _MMIO_TRANS2(pipe, reg)		_MMIO(INTEL_INFO(dev_priv)->trans_offsets[(pipe)] - \
>-					      INTEL_INFO(dev_priv)->trans_offsets[TRANSCODER_A] + (reg) + \
>-					      DISPLAY_MMIO_BASE(dev_priv))
>+#define _TRANS2(tran, reg)		(INTEL_INFO(dev_priv)->trans_offsets[(tran)] - \
>+					 INTEL_INFO(dev_priv)->trans_offsets[TRANSCODER_A] + (reg) + \
>+					 DISPLAY_MMIO_BASE(dev_priv))

a pure move with no behavior change


Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>

Lucas De Marchi


>+#define _MMIO_TRANS2(tran, reg)		_MMIO(_TRANS2(tran, reg))
> #define _CURSOR2(pipe, reg)		_MMIO(INTEL_INFO(dev_priv)->cursor_offsets[(pipe)] - \
> 					      INTEL_INFO(dev_priv)->cursor_offsets[PIPE_A] + (reg) + \
> 					      DISPLAY_MMIO_BASE(dev_priv))
>-- 
>2.22.0
>
>_______________________________________________
>Intel-gfx mailing list
>Intel-gfx@lists.freedesktop.org
>https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
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  reply	other threads:[~2019-08-06 23:31 UTC|newest]

Thread overview: 12+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-07-30 22:47 [PATCH v7 1/4] drm/i915/bdw+: Move misc display IRQ handling to it own function José Roberto de Souza
2019-07-30 22:47 ` [PATCH v7 2/4] drm/i915: Add _TRANS2() José Roberto de Souza
2019-08-06 23:31   ` Lucas De Marchi [this message]
2019-08-13 23:03     ` Souza, Jose
2019-07-30 22:47 ` [PATCH v7 3/4] drm/i915/psr: Make PSR registers relative to transcoders José Roberto de Souza
2019-07-30 22:47 ` [PATCH v7 4/4] drm/i915: Add transcoder restriction to PSR2 José Roberto de Souza
2019-08-12 13:50   ` Gupta, Anshuman
2019-08-12 17:39     ` Souza, Jose
2019-07-30 23:31 ` ✗ Fi.CI.CHECKPATCH: warning for series starting with [v7,1/4] drm/i915/bdw+: Move misc display IRQ handling to it own function Patchwork
2019-07-30 23:51 ` ✓ Fi.CI.BAT: success " Patchwork
2019-08-01 14:15 ` ✓ Fi.CI.IGT: " Patchwork
2019-08-06 23:23 ` [PATCH v7 1/4] " Lucas De Marchi

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