From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.3 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_SANE_1 autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 19DCDC0650F for ; Wed, 14 Aug 2019 04:35:57 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id EDF592064A for ; Wed, 14 Aug 2019 04:35:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727330AbfHNEfz (ORCPT ); Wed, 14 Aug 2019 00:35:55 -0400 Received: from verein.lst.de ([213.95.11.211]:34398 "EHLO verein.lst.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726631AbfHNEfz (ORCPT ); Wed, 14 Aug 2019 00:35:55 -0400 Received: by verein.lst.de (Postfix, from userid 2407) id 9889C68B02; Wed, 14 Aug 2019 06:35:51 +0200 (CEST) Date: Wed, 14 Aug 2019 06:35:51 +0200 From: Christoph Hellwig To: Alan Kao Cc: Christoph Hellwig , Palmer Dabbelt , Paul Walmsley , Damien Le Moal , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH 13/15] riscv: clear the instruction cache and all registers when booting Message-ID: <20190814043551.GA22862@lst.de> References: <20190813154747.24256-1-hch@lst.de> <20190813154747.24256-14-hch@lst.de> <20190814010013.GA18655@andestech.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20190814010013.GA18655@andestech.com> User-Agent: Mutt/1.5.17 (2007-11-01) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, Aug 14, 2019 at 09:00:14AM +0800, Alan Kao wrote: > But it doesn't really mean that the running system has an FPU given CONFIG_FPU > enabled. Normally the existence of an FPU is checked in riscv_fill_hwcap by > searching device tree, where the code looks like > > > bool has_fpu = false; // this one is global > ... > #ifdef CONFIG_FPU > if (elf_hwcap & (COMPAT_HWCAP_ISA_F | COMPAT_HWCAP_ISA_D)) > has_fpu = true; > #endif > > > Or does CONFIG_FPU have a more intuitive meaning when CONFIG_M_MODE is enabled? No, it doesn't.. > > > + csrr t0, CSR_MISA > > + andi t0, t0, (COMPAT_HWCAP_ISA_F | COMPAT_HWCAP_ISA_D) > > + bnez t0, .Lreset_regs_done ... which is why we have these few lines of code that check the caps returns from the misa CSR, similar to the elf_caps check quoted above. From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.3 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_HELO_NONE, SPF_PASS,URIBL_BLOCKED,USER_AGENT_SANE_1 autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7B9A5C0650F for ; Wed, 14 Aug 2019 04:36:04 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 50EEA2064A for ; Wed, 14 Aug 2019 04:36:04 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="sCIbbnTi" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 50EEA2064A Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=lst.de Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-riscv-bounces+infradead-linux-riscv=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=gCQ77sDgtWN+KW9+/7mvhNJCTD5I0KjOwYi3YNTzh80=; b=sCIbbnTisDaPY7 N13/gGik3JHCTMykV2J9S10CdcHDOsfifYcCyAwL3LyRKOrQn780UAC31+k1tNJCHraz54Fw+hr3r iiB5JtlaC577X/I0vEyza+powQc3/xWU45q4JBQc0jjsBx7UMO7xLEyPKvIivHg6DR79LdxZ1Q/ui dsgv1Vu3CqxtbXCubz47M0SMYxJYjuBPEpG2EKUVeTrVmpUibkacLCqXJbtql2nNfvtk3zjmRMw+L hgJ3XmFuYZDocRyB91xrqyfPLcw9noGkwx/naYq8WXmDx7USv6SsZ7phju2uqDgjYCtDQrIyVieeX 45YC6i3tX5axo8NssCIw==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.92 #3 (Red Hat Linux)) id 1hxl0x-0007YD-G3; Wed, 14 Aug 2019 04:35:59 +0000 Received: from verein.lst.de ([213.95.11.211]) by bombadil.infradead.org with esmtps (Exim 4.92 #3 (Red Hat Linux)) id 1hxl0u-0007Xb-8Z for linux-riscv@lists.infradead.org; Wed, 14 Aug 2019 04:35:57 +0000 Received: by verein.lst.de (Postfix, from userid 2407) id 9889C68B02; Wed, 14 Aug 2019 06:35:51 +0200 (CEST) Date: Wed, 14 Aug 2019 06:35:51 +0200 From: Christoph Hellwig To: Alan Kao Subject: Re: [PATCH 13/15] riscv: clear the instruction cache and all registers when booting Message-ID: <20190814043551.GA22862@lst.de> References: <20190813154747.24256-1-hch@lst.de> <20190813154747.24256-14-hch@lst.de> <20190814010013.GA18655@andestech.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20190814010013.GA18655@andestech.com> User-Agent: Mutt/1.5.17 (2007-11-01) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190813_213556_451883_84741F71 X-CRM114-Status: UNSURE ( 8.99 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Damien Le Moal , Palmer Dabbelt , linux-kernel@vger.kernel.org, Paul Walmsley , linux-riscv@lists.infradead.org, Christoph Hellwig Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+infradead-linux-riscv=archiver.kernel.org@lists.infradead.org On Wed, Aug 14, 2019 at 09:00:14AM +0800, Alan Kao wrote: > But it doesn't really mean that the running system has an FPU given CONFIG_FPU > enabled. Normally the existence of an FPU is checked in riscv_fill_hwcap by > searching device tree, where the code looks like > > > bool has_fpu = false; // this one is global > ... > #ifdef CONFIG_FPU > if (elf_hwcap & (COMPAT_HWCAP_ISA_F | COMPAT_HWCAP_ISA_D)) > has_fpu = true; > #endif > > > Or does CONFIG_FPU have a more intuitive meaning when CONFIG_M_MODE is enabled? No, it doesn't.. > > > + csrr t0, CSR_MISA > > + andi t0, t0, (COMPAT_HWCAP_ISA_F | COMPAT_HWCAP_ISA_D) > > + bnez t0, .Lreset_regs_done ... which is why we have these few lines of code that check the caps returns from the misa CSR, similar to the elf_caps check quoted above. _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv