[PATCH 1/4] drm/amd/powerplay: update Arcturus smc fw and driver interface header

[PATCH 1/4] drm/amd/powerplay: update Arcturus smc fw and driver interface header

[Evan Quan]

Update smc fw and driver interface header.

Change-Id: If4ac09c41b1309f746b757f78880fffb491d50f8
Signed-off-by: Evan Quan <evan.quan@amd.com>
---
 .../powerplay/inc/smu11_driver_if_arcturus.h    | 17 +++++++++++------
 drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h   |  2 +-
 2 files changed, 12 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_arcturus.h b/drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_arcturus.h
index b99e98c40720..e02950b505fa 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_arcturus.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_arcturus.h
@@ -27,7 +27,7 @@
 // *** IMPORTANT ***
 // SMU TEAM: Always increment the interface version if
 // any structure is changed in this file
-//#define SMU11_DRIVER_IF_VERSION 0x08
+//#define SMU11_DRIVER_IF_VERSION 0x09
 
 #define PPTABLE_ARCTURUS_SMU_VERSION 4
 
@@ -691,7 +691,12 @@ typedef struct {
   uint16_t          XgmiFclkFreq    [NUM_XGMI_PSTATE_LEVELS];
   uint16_t          XgmiSocVoltage  [NUM_XGMI_PSTATE_LEVELS];
 
-  uint32_t     BoardReserved[10];
+  // GPIO pins for I2C communications with 2nd controller for Input Telemetry Sequence
+  uint8_t      GpioI2cScl;          // Serial Clock
+  uint8_t      GpioI2cSda;          // Serial Data
+  uint16_t     GpioPadding;
+
+  uint32_t     BoardReserved[9];
 
   // Padding for MMHUB - do not modify this
   uint32_t     MmHubPadding[8]; // SMU internal use
@@ -738,7 +743,7 @@ typedef struct {
   uint32_t Padding[4];
 
   // Padding - ignore
-  uint32_t     MmHubPadding[7]; // SMU internal use
+  uint32_t     MmHubPadding[8]; // SMU internal use
 } SmuMetrics_t;
 
 
@@ -748,7 +753,7 @@ typedef struct {
   float    avgPsmVoltage[75];
   float    minPsmVoltage[75];
 
-  uint32_t MmHubPadding[3]; // SMU internal use
+  uint32_t MmHubPadding[8]; // SMU internal use
 } AvfsDebugTable_t;
 
 typedef struct {
@@ -797,9 +802,9 @@ typedef struct {
 
   uint32_t P2VCharzFreq[AVFS_VOLTAGE_COUNT]; // in 10KHz units
 
-  uint32_t EnabledAvfsModules;
+  uint32_t EnabledAvfsModules[2];
 
-  uint32_t MmHubPadding[7]; // SMU internal use
+  uint32_t MmHubPadding[8]; // SMU internal use
 } AvfsFuseOverride_t;
 
 /* NOT CURRENTLY USED
diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h b/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
index 5fbf082be091..0a22fa48ff5a 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
@@ -27,7 +27,7 @@
 
 #define SMU11_DRIVER_IF_VERSION_INV 0xFFFFFFFF
 #define SMU11_DRIVER_IF_VERSION_VG20 0x13
-#define SMU11_DRIVER_IF_VERSION_ARCT 0x08
+#define SMU11_DRIVER_IF_VERSION_ARCT 0x09
 #define SMU11_DRIVER_IF_VERSION_NV10 0x33
 #define SMU11_DRIVER_IF_VERSION_NV12 0x33
 #define SMU11_DRIVER_IF_VERSION_NV14 0x33
-- 
2.22.0

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[PATCH 2/4] drm/amd/powerplay: expose supported clock domains only through sysfs

[Evan Quan]

Do not expose those unsupported clock domains through sysfs on
Arcturus.

Change-Id: I526e7bd457fdcd8c79d4581bb9b77e5cb57f5844
Signed-off-by: Evan Quan <evan.quan@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | 26 ++++++++++++++++----------
 1 file changed, 16 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
index c5642be9b44b..7accf2c7f8cd 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
@@ -2879,10 +2879,12 @@ int amdgpu_pm_sysfs_init(struct amdgpu_device *adev)
 			DRM_ERROR("failed to create device file pp_dpm_socclk\n");
 			return ret;
 		}
-		ret = device_create_file(adev->dev, &dev_attr_pp_dpm_dcefclk);
-		if (ret) {
-			DRM_ERROR("failed to create device file pp_dpm_dcefclk\n");
-			return ret;
+		if (adev->asic_type != CHIP_ARCTURUS) {
+			ret = device_create_file(adev->dev, &dev_attr_pp_dpm_dcefclk);
+			if (ret) {
+				DRM_ERROR("failed to create device file pp_dpm_dcefclk\n");
+				return ret;
+			}
 		}
 	}
 	if (adev->asic_type >= CHIP_VEGA20) {
@@ -2892,10 +2894,12 @@ int amdgpu_pm_sysfs_init(struct amdgpu_device *adev)
 			return ret;
 		}
 	}
-	ret = device_create_file(adev->dev, &dev_attr_pp_dpm_pcie);
-	if (ret) {
-		DRM_ERROR("failed to create device file pp_dpm_pcie\n");
-		return ret;
+	if (adev->asic_type != CHIP_ARCTURUS) {
+		ret = device_create_file(adev->dev, &dev_attr_pp_dpm_pcie);
+		if (ret) {
+			DRM_ERROR("failed to create device file pp_dpm_pcie\n");
+			return ret;
+		}
 	}
 	ret = device_create_file(adev->dev, &dev_attr_pp_sclk_od);
 	if (ret) {
@@ -2999,9 +3003,11 @@ void amdgpu_pm_sysfs_fini(struct amdgpu_device *adev)
 	device_remove_file(adev->dev, &dev_attr_pp_dpm_mclk);
 	if (adev->asic_type >= CHIP_VEGA10) {
 		device_remove_file(adev->dev, &dev_attr_pp_dpm_socclk);
-		device_remove_file(adev->dev, &dev_attr_pp_dpm_dcefclk);
+		if (adev->asic_type != CHIP_ARCTURUS)
+			device_remove_file(adev->dev, &dev_attr_pp_dpm_dcefclk);
 	}
-	device_remove_file(adev->dev, &dev_attr_pp_dpm_pcie);
+	if (adev->asic_type != CHIP_ARCTURUS)
+		device_remove_file(adev->dev, &dev_attr_pp_dpm_pcie);
 	if (adev->asic_type >= CHIP_VEGA20)
 		device_remove_file(adev->dev, &dev_attr_pp_dpm_fclk);
 	device_remove_file(adev->dev, &dev_attr_pp_sclk_od);
-- 
2.22.0

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[PATCH 3/4] drm/amd/powerplay: get bootup fclk value

[Evan Quan]

This is available with firmwareinfo table v3.2 or later.

Change-Id: I223edf3c616b9e3e2527c752214fef5ab53d1cea
Signed-off-by: Evan Quan <evan.quan@amd.com>
---
 .../gpu/drm/amd/powerplay/inc/amdgpu_smu.h    |  3 +++
 drivers/gpu/drm/amd/powerplay/smu_v11_0.c     | 21 +++++++++++++++++++
 2 files changed, 24 insertions(+)

diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
index ca9b9ec39de8..2c16eb412954 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
@@ -222,6 +222,9 @@ struct smu_bios_boot_up_values
 	uint16_t			vdd_gfx;
 	uint8_t				cooling_id;
 	uint32_t			pp_table_id;
+	uint32_t			format_revision;
+	uint32_t			content_revision;
+	uint32_t			fclk;
 };
 
 enum smu_table_id
diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
index 4a51de4ff162..df7b65360ac7 100644
--- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
@@ -568,6 +568,9 @@ int smu_v11_0_get_vbios_bootup_values(struct smu_context *smu)
 		smu->smu_table.boot_values.pp_table_id = v_3_3->pplib_pptable_id;
 	}
 
+	smu->smu_table.boot_values.format_revision = header->format_revision;
+	smu->smu_table.boot_values.content_revision = header->content_revision;
+
 	return 0;
 }
 
@@ -647,6 +650,24 @@ static int smu_v11_0_get_clk_info_from_vbios(struct smu_context *smu)
 	output = (struct atom_get_smu_clock_info_output_parameters_v3_1 *)&input;
 	smu->smu_table.boot_values.dclk = le32_to_cpu(output->atom_smu_outputclkfreq.smu_clock_freq_hz) / 10000;
 
+	if ((smu->smu_table.boot_values.format_revision == 3) &&
+	    (smu->smu_table.boot_values.content_revision >= 2)) {
+		memset(&input, 0, sizeof(input));
+		input.clk_id = SMU11_SYSPLL1_0_FCLK_ID;
+		input.syspll_id = SMU11_SYSPLL1_2_ID;
+		input.command = GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ;
+		index = get_index_into_master_table(atom_master_list_of_command_functions_v2_1,
+						    getsmuclockinfo);
+
+		ret = amdgpu_atom_execute_table(adev->mode_info.atom_context, index,
+						(uint32_t *)&input);
+		if (ret)
+			return -EINVAL;
+
+		output = (struct atom_get_smu_clock_info_output_parameters_v3_1 *)&input;
+		smu->smu_table.boot_values.fclk = le32_to_cpu(output->atom_smu_outputclkfreq.smu_clock_freq_hz) / 10000;
+	}
+
 	return 0;
 }
 
-- 
2.22.0

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[PATCH 4/4] drm/amd/powerplay: set Arcturus default fclk as bootup value on dpm disabled

[Evan Quan]

On fclk dpm disabled, the default dpm table will be setup with only one
level and clock frequency as bootup value.

Change-Id: Iecf74aa5bd10c9aa7839bc32877cfa99bcbef4b3
Signed-off-by: Evan Quan <evan.quan@amd.com>
---
 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
index 9107beba6790..db8be6d8d903 100644
--- a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
@@ -463,7 +463,8 @@ static int arcturus_set_default_dpm_table(struct smu_context *smu)
 			return ret;
 		}
 	} else {
-		single_dpm_table->count = 0;
+		single_dpm_table->count = 1;
+		single_dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.fclk / 100;
 	}
 	arcturus_init_single_dpm_state(&(single_dpm_table->dpm_state));
 
-- 
2.22.0

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Re: [PATCH 1/4] drm/amd/powerplay: update Arcturus smc fw and driver interface header

[Wang, Kevin(Yang)]

[-- Attachment #1.1: Type: text/plain, Size: 3681 bytes --]

Reviewed-by: Kevin Wang <kevin1.wang-5C7GfCeVMHo@public.gmane.org>

Best Regards,
Kevin
________________________________
From: amd-gfx <amd-gfx-bounces-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org> on behalf of Evan Quan <evan.quan-5C7GfCeVMHo@public.gmane.org>
Sent: Friday, August 16, 2019 2:08 PM
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org <amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org>
Cc: Quan, Evan <Evan.Quan-5C7GfCeVMHo@public.gmane.org>
Subject: [PATCH 1/4] drm/amd/powerplay: update Arcturus smc fw and driver interface header

Update smc fw and driver interface header.

Change-Id: If4ac09c41b1309f746b757f78880fffb491d50f8
Signed-off-by: Evan Quan <evan.quan-5C7GfCeVMHo@public.gmane.org>
---
 .../powerplay/inc/smu11_driver_if_arcturus.h    | 17 +++++++++++------
 drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h   |  2 +-
 2 files changed, 12 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_arcturus.h b/drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_arcturus.h
index b99e98c40720..e02950b505fa 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_arcturus.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_arcturus.h
@@ -27,7 +27,7 @@
 // *** IMPORTANT ***
 // SMU TEAM: Always increment the interface version if
 // any structure is changed in this file
-//#define SMU11_DRIVER_IF_VERSION 0x08
+//#define SMU11_DRIVER_IF_VERSION 0x09

 #define PPTABLE_ARCTURUS_SMU_VERSION 4

@@ -691,7 +691,12 @@ typedef struct {
   uint16_t          XgmiFclkFreq    [NUM_XGMI_PSTATE_LEVELS];
   uint16_t          XgmiSocVoltage  [NUM_XGMI_PSTATE_LEVELS];

-  uint32_t     BoardReserved[10];
+  // GPIO pins for I2C communications with 2nd controller for Input Telemetry Sequence
+  uint8_t      GpioI2cScl;          // Serial Clock
+  uint8_t      GpioI2cSda;          // Serial Data
+  uint16_t     GpioPadding;
+
+  uint32_t     BoardReserved[9];

   // Padding for MMHUB - do not modify this
   uint32_t     MmHubPadding[8]; // SMU internal use
@@ -738,7 +743,7 @@ typedef struct {
   uint32_t Padding[4];

   // Padding - ignore
-  uint32_t     MmHubPadding[7]; // SMU internal use
+  uint32_t     MmHubPadding[8]; // SMU internal use
 } SmuMetrics_t;


@@ -748,7 +753,7 @@ typedef struct {
   float    avgPsmVoltage[75];
   float    minPsmVoltage[75];

-  uint32_t MmHubPadding[3]; // SMU internal use
+  uint32_t MmHubPadding[8]; // SMU internal use
 } AvfsDebugTable_t;

 typedef struct {
@@ -797,9 +802,9 @@ typedef struct {

   uint32_t P2VCharzFreq[AVFS_VOLTAGE_COUNT]; // in 10KHz units

-  uint32_t EnabledAvfsModules;
+  uint32_t EnabledAvfsModules[2];

-  uint32_t MmHubPadding[7]; // SMU internal use
+  uint32_t MmHubPadding[8]; // SMU internal use
 } AvfsFuseOverride_t;

 /* NOT CURRENTLY USED
diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h b/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
index 5fbf082be091..0a22fa48ff5a 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
@@ -27,7 +27,7 @@

 #define SMU11_DRIVER_IF_VERSION_INV 0xFFFFFFFF
 #define SMU11_DRIVER_IF_VERSION_VG20 0x13
-#define SMU11_DRIVER_IF_VERSION_ARCT 0x08
+#define SMU11_DRIVER_IF_VERSION_ARCT 0x09
 #define SMU11_DRIVER_IF_VERSION_NV10 0x33
 #define SMU11_DRIVER_IF_VERSION_NV12 0x33
 #define SMU11_DRIVER_IF_VERSION_NV14 0x33
--
2.22.0

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Re: [PATCH 3/4] drm/amd/powerplay: get bootup fclk value

[Wang, Kevin(Yang)]

[-- Attachment #1.1: Type: text/plain, Size: 4013 bytes --]

i think we can use a function to retrieve this information without storing it separately.
likes:  ret = smu_get_atom_data_table(smu, index, &size, &frev, &crev,
                                      (uint8_t **)&header);
because these information is a generic information from atom_common_table_header.
and other function don't care it except in smu_v11_0_get_clk_info_from_vbios.

Best Regards,
Kevin
________________________________
From: amd-gfx <amd-gfx-bounces-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org> on behalf of Evan Quan <evan.quan-5C7GfCeVMHo@public.gmane.org>
Sent: Friday, August 16, 2019 2:08 PM
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org <amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org>
Cc: Quan, Evan <Evan.Quan-5C7GfCeVMHo@public.gmane.org>
Subject: [PATCH 3/4] drm/amd/powerplay: get bootup fclk value

This is available with firmwareinfo table v3.2 or later.

Change-Id: I223edf3c616b9e3e2527c752214fef5ab53d1cea
Signed-off-by: Evan Quan <evan.quan-5C7GfCeVMHo@public.gmane.org>
---
 .../gpu/drm/amd/powerplay/inc/amdgpu_smu.h    |  3 +++
 drivers/gpu/drm/amd/powerplay/smu_v11_0.c     | 21 +++++++++++++++++++
 2 files changed, 24 insertions(+)

diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
index ca9b9ec39de8..2c16eb412954 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
@@ -222,6 +222,9 @@ struct smu_bios_boot_up_values
         uint16_t                        vdd_gfx;
         uint8_t                         cooling_id;
         uint32_t                        pp_table_id;
+       uint32_t                        format_revision;
+       uint32_t                        content_revision;
+       uint32_t                        fclk;
 };

 enum smu_table_id
diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
index 4a51de4ff162..df7b65360ac7 100644
--- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
@@ -568,6 +568,9 @@ int smu_v11_0_get_vbios_bootup_values(struct smu_context *smu)
                 smu->smu_table.boot_values.pp_table_id = v_3_3->pplib_pptable_id;
         }

+       smu->smu_table.boot_values.format_revision = header->format_revision;
+       smu->smu_table.boot_values.content_revision = header->content_revision;
+
         return 0;
 }

@@ -647,6 +650,24 @@ static int smu_v11_0_get_clk_info_from_vbios(struct smu_context *smu)
         output = (struct atom_get_smu_clock_info_output_parameters_v3_1 *)&input;
         smu->smu_table.boot_values.dclk = le32_to_cpu(output->atom_smu_outputclkfreq.smu_clock_freq_hz) / 10000;

+       if ((smu->smu_table.boot_values.format_revision == 3) &&
+           (smu->smu_table.boot_values.content_revision >= 2)) {
+               memset(&input, 0, sizeof(input));
+               input.clk_id = SMU11_SYSPLL1_0_FCLK_ID;
+               input.syspll_id = SMU11_SYSPLL1_2_ID;
+               input.command = GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ;
+               index = get_index_into_master_table(atom_master_list_of_command_functions_v2_1,
+                                                   getsmuclockinfo);
+
+               ret = amdgpu_atom_execute_table(adev->mode_info.atom_context, index,
+                                               (uint32_t *)&input);
+               if (ret)
+                       return -EINVAL;
+
+               output = (struct atom_get_smu_clock_info_output_parameters_v3_1 *)&input;
+               smu->smu_table.boot_values.fclk = le32_to_cpu(output->atom_smu_outputclkfreq.smu_clock_freq_hz) / 10000;
+       }
+
         return 0;
 }

--
2.22.0

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Re: [PATCH 4/4] drm/amd/powerplay: set Arcturus default fclk as bootup value on dpm disabled

[Wang, Kevin(Yang)]

[-- Attachment #1.1: Type: text/plain, Size: 1836 bytes --]

Reviewed-by: Kevin Wang <kevin1.wang-5C7GfCeVMHo@public.gmane.org>

Best Regards,
Kevin
________________________________
From: amd-gfx <amd-gfx-bounces-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org> on behalf of Evan Quan <evan.quan-5C7GfCeVMHo@public.gmane.org>
Sent: Friday, August 16, 2019 2:08 PM
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org <amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org>
Cc: Quan, Evan <Evan.Quan-5C7GfCeVMHo@public.gmane.org>
Subject: [PATCH 4/4] drm/amd/powerplay: set Arcturus default fclk as bootup value on dpm disabled

On fclk dpm disabled, the default dpm table will be setup with only one
level and clock frequency as bootup value.

Change-Id: Iecf74aa5bd10c9aa7839bc32877cfa99bcbef4b3
Signed-off-by: Evan Quan <evan.quan-5C7GfCeVMHo@public.gmane.org>
---
 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
index 9107beba6790..db8be6d8d903 100644
--- a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
@@ -463,7 +463,8 @@ static int arcturus_set_default_dpm_table(struct smu_context *smu)
                         return ret;
                 }
         } else {
-               single_dpm_table->count = 0;
+               single_dpm_table->count = 1;
+               single_dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.fclk / 100;
         }
         arcturus_init_single_dpm_state(&(single_dpm_table->dpm_state));

--
2.22.0

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RE: [PATCH 2/4] drm/amd/powerplay: expose supported clock domains only through sysfs

[Quan, Evan]

[-- Attachment #1.1: Type: text/plain, Size: 4943 bytes --]

Bascially, we should not expose the sysfs interface for those features not supported by the ASIC.
As, there are some tools/tests which judges whether the feature is supported by the existence of the file.
This can fix some test failure in rocm test suit.

Regards,
Evan
From: Wang, Kevin(Yang) <Kevin1.Wang-5C7GfCeVMHo@public.gmane.org>
Sent: Friday, August 16, 2019 3:16 PM
To: Quan, Evan <Evan.Quan-5C7GfCeVMHo@public.gmane.org>; amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
Subject: Re: [PATCH 2/4] drm/amd/powerplay: expose supported clock domains only through sysfs

I don't recommend it. What's the problem if we keep it the way it is?
maybe other asic also has same problems, if do it, the other asic should  add a condition in there too.
eg: navi10 don't support sensor of  "pp_dpm_pcie".

Best Regards,
Kevin
________________________________
From: amd-gfx <amd-gfx-bounces-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org<mailto:amd-gfx-bounces@lists.freedesktop.org>> on behalf of Evan Quan <evan.quan-5C7GfCeVMHo@public.gmane.org<mailto:evan.quan-5C7GfCeVMHo@public.gmane.org>>
Sent: Friday, August 16, 2019 2:08 PM
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org<mailto:amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org> <amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org<mailto:amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org>>
Cc: Quan, Evan <Evan.Quan-5C7GfCeVMHo@public.gmane.org<mailto:Evan.Quan-5C7GfCeVMHo@public.gmane.org>>
Subject: [PATCH 2/4] drm/amd/powerplay: expose supported clock domains only through sysfs

Do not expose those unsupported clock domains through sysfs on
Arcturus.

Change-Id: I526e7bd457fdcd8c79d4581bb9b77e5cb57f5844
Signed-off-by: Evan Quan <evan.quan-5C7GfCeVMHo@public.gmane.org<mailto:evan.quan-5C7GfCeVMHo@public.gmane.org>>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | 26 ++++++++++++++++----------
 1 file changed, 16 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
index c5642be9b44b..7accf2c7f8cd 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
@@ -2879,10 +2879,12 @@ int amdgpu_pm_sysfs_init(struct amdgpu_device *adev)
                         DRM_ERROR("failed to create device file pp_dpm_socclk\n");
                         return ret;
                 }
-               ret = device_create_file(adev->dev, &dev_attr_pp_dpm_dcefclk);
-               if (ret) {
-                       DRM_ERROR("failed to create device file pp_dpm_dcefclk\n");
-                       return ret;
+               if (adev->asic_type != CHIP_ARCTURUS) {
+                       ret = device_create_file(adev->dev, &dev_attr_pp_dpm_dcefclk);
+                       if (ret) {
+                               DRM_ERROR("failed to create device file pp_dpm_dcefclk\n");
+                               return ret;
+                       }
                 }
         }
         if (adev->asic_type >= CHIP_VEGA20) {
@@ -2892,10 +2894,12 @@ int amdgpu_pm_sysfs_init(struct amdgpu_device *adev)
                         return ret;
                 }
         }
-       ret = device_create_file(adev->dev, &dev_attr_pp_dpm_pcie);
-       if (ret) {
-               DRM_ERROR("failed to create device file pp_dpm_pcie\n");
-               return ret;
+       if (adev->asic_type != CHIP_ARCTURUS) {
+               ret = device_create_file(adev->dev, &dev_attr_pp_dpm_pcie);
+               if (ret) {
+                       DRM_ERROR("failed to create device file pp_dpm_pcie\n");
+                       return ret;
+               }
         }
         ret = device_create_file(adev->dev, &dev_attr_pp_sclk_od);
         if (ret) {
@@ -2999,9 +3003,11 @@ void amdgpu_pm_sysfs_fini(struct amdgpu_device *adev)
         device_remove_file(adev->dev, &dev_attr_pp_dpm_mclk);
         if (adev->asic_type >= CHIP_VEGA10) {
                 device_remove_file(adev->dev, &dev_attr_pp_dpm_socclk);
-               device_remove_file(adev->dev, &dev_attr_pp_dpm_dcefclk);
+               if (adev->asic_type != CHIP_ARCTURUS)
+                       device_remove_file(adev->dev, &dev_attr_pp_dpm_dcefclk);
         }
-       device_remove_file(adev->dev, &dev_attr_pp_dpm_pcie);
+       if (adev->asic_type != CHIP_ARCTURUS)
+               device_remove_file(adev->dev, &dev_attr_pp_dpm_pcie);
         if (adev->asic_type >= CHIP_VEGA20)
                 device_remove_file(adev->dev, &dev_attr_pp_dpm_fclk);
         device_remove_file(adev->dev, &dev_attr_pp_sclk_od);
--
2.22.0

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RE: [PATCH 3/4] drm/amd/powerplay: get bootup fclk value

[Quan, Evan]

[-- Attachment #1.1: Type: text/plain, Size: 5066 bytes --]

Since smu_get_atom_data_table() was already used in smu_v11_0_get_vbios_bootup_values(). We should get all our needed information at once.
Also, what smu_get_atom_data_table() does is to get the data table from vbios. It's a time and resource cost job.
I do not think it's a good idea to call it again just to get some information we should already know.

Regards,
Evan
From: Wang, Kevin(Yang) <Kevin1.Wang-5C7GfCeVMHo@public.gmane.org>
Sent: Friday, August 16, 2019 3:10 PM
To: Quan, Evan <Evan.Quan-5C7GfCeVMHo@public.gmane.org>; amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
Subject: Re: [PATCH 3/4] drm/amd/powerplay: get bootup fclk value

i think we can use a function to retrieve this information without storing it separately.
likes:  ret = smu_get_atom_data_table(smu, index, &size, &frev, &crev,
                                      (uint8_t **)&header);
because these information is a generic information from atom_common_table_header.
and other function don't care it except in smu_v11_0_get_clk_info_from_vbios.

Best Regards,
Kevin
________________________________
From: amd-gfx <amd-gfx-bounces-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org<mailto:amd-gfx-bounces@lists.freedesktop.org>> on behalf of Evan Quan <evan.quan-5C7GfCeVMHo@public.gmane.org<mailto:evan.quan-5C7GfCeVMHo@public.gmane.org>>
Sent: Friday, August 16, 2019 2:08 PM
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org<mailto:amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org> <amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org<mailto:amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org>>
Cc: Quan, Evan <Evan.Quan-5C7GfCeVMHo@public.gmane.org<mailto:Evan.Quan-5C7GfCeVMHo@public.gmane.org>>
Subject: [PATCH 3/4] drm/amd/powerplay: get bootup fclk value

This is available with firmwareinfo table v3.2 or later.

Change-Id: I223edf3c616b9e3e2527c752214fef5ab53d1cea
Signed-off-by: Evan Quan <evan.quan-5C7GfCeVMHo@public.gmane.org<mailto:evan.quan-5C7GfCeVMHo@public.gmane.org>>
---
 .../gpu/drm/amd/powerplay/inc/amdgpu_smu.h    |  3 +++
 drivers/gpu/drm/amd/powerplay/smu_v11_0.c     | 21 +++++++++++++++++++
 2 files changed, 24 insertions(+)

diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
index ca9b9ec39de8..2c16eb412954 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
@@ -222,6 +222,9 @@ struct smu_bios_boot_up_values
         uint16_t                        vdd_gfx;
         uint8_t                         cooling_id;
         uint32_t                        pp_table_id;
+       uint32_t                        format_revision;
+       uint32_t                        content_revision;
+       uint32_t                        fclk;
 };

 enum smu_table_id
diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
index 4a51de4ff162..df7b65360ac7 100644
--- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
@@ -568,6 +568,9 @@ int smu_v11_0_get_vbios_bootup_values(struct smu_context *smu)
                 smu->smu_table.boot_values.pp_table_id = v_3_3->pplib_pptable_id;
         }

+       smu->smu_table.boot_values.format_revision = header->format_revision;
+       smu->smu_table.boot_values.content_revision = header->content_revision;
+
         return 0;
 }

@@ -647,6 +650,24 @@ static int smu_v11_0_get_clk_info_from_vbios(struct smu_context *smu)
         output = (struct atom_get_smu_clock_info_output_parameters_v3_1 *)&input;
         smu->smu_table.boot_values.dclk = le32_to_cpu(output->atom_smu_outputclkfreq.smu_clock_freq_hz) / 10000;

+       if ((smu->smu_table.boot_values.format_revision == 3) &&
+           (smu->smu_table.boot_values.content_revision >= 2)) {
+               memset(&input, 0, sizeof(input));
+               input.clk_id = SMU11_SYSPLL1_0_FCLK_ID;
+               input.syspll_id = SMU11_SYSPLL1_2_ID;
+               input.command = GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ;
+               index = get_index_into_master_table(atom_master_list_of_command_functions_v2_1,
+                                                   getsmuclockinfo);
+
+               ret = amdgpu_atom_execute_table(adev->mode_info.atom_context, index,
+                                               (uint32_t *)&input);
+               if (ret)
+                       return -EINVAL;
+
+               output = (struct atom_get_smu_clock_info_output_parameters_v3_1 *)&input;
+               smu->smu_table.boot_values.fclk = le32_to_cpu(output->atom_smu_outputclkfreq.smu_clock_freq_hz) / 10000;
+       }
+
         return 0;
 }

--
2.22.0

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Re: [PATCH 2/4] drm/amd/powerplay: expose supported clock domains only through sysfs

[Kevin Wang]

[-- Attachment #1.1: Type: text/plain, Size: 5073 bytes --]

sure, i know, I feel this is not a good way to do code when other asics have similar problems.
we'd better add a helper function to check which sysfs interface is supported for each asic.
or move these sysfs interface to asic file to create.

anyway, we can optimize this logic later.
Reviewed-by: Kevin Wang <kevin1.wang@amd.com><mailto:kevin1.wang@amd.com>

Best Regards,
Kevin

On 8/16/19 3:52 PM, Quan, Evan wrote:
Bascially, we should not expose the sysfs interface for those features not supported by the ASIC.
As, there are some tools/tests which judges whether the feature is supported by the existence of the file.
This can fix some test failure in rocm test suit.

Regards,
Evan
From: Wang, Kevin(Yang) <Kevin1.Wang@amd.com><mailto:Kevin1.Wang@amd.com>
Sent: Friday, August 16, 2019 3:16 PM
To: Quan, Evan <Evan.Quan@amd.com><mailto:Evan.Quan@amd.com>; amd-gfx@lists.freedesktop.org<mailto:amd-gfx@lists.freedesktop.org>
Subject: Re: [PATCH 2/4] drm/amd/powerplay: expose supported clock domains only through sysfs

I don't recommend it. What's the problem if we keep it the way it is?
maybe other asic also has same problems, if do it, the other asic should  add a condition in there too.
eg: navi10 don't support sensor of  "pp_dpm_pcie".

Best Regards,
Kevin
________________________________
From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org<mailto:amd-gfx-bounces@lists.freedesktop.org>> on behalf of Evan Quan <evan.quan@amd.com<mailto:evan.quan@amd.com>>
Sent: Friday, August 16, 2019 2:08 PM
To: amd-gfx@lists.freedesktop.org<mailto:amd-gfx@lists.freedesktop.org> <amd-gfx@lists.freedesktop.org<mailto:amd-gfx@lists.freedesktop.org>>
Cc: Quan, Evan <Evan.Quan@amd.com<mailto:Evan.Quan@amd.com>>
Subject: [PATCH 2/4] drm/amd/powerplay: expose supported clock domains only through sysfs

Do not expose those unsupported clock domains through sysfs on
Arcturus.

Change-Id: I526e7bd457fdcd8c79d4581bb9b77e5cb57f5844
Signed-off-by: Evan Quan <evan.quan@amd.com<mailto:evan.quan@amd.com>>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | 26 ++++++++++++++++----------
 1 file changed, 16 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
index c5642be9b44b..7accf2c7f8cd 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
@@ -2879,10 +2879,12 @@ int amdgpu_pm_sysfs_init(struct amdgpu_device *adev)
                         DRM_ERROR("failed to create device file pp_dpm_socclk\n");
                         return ret;
                 }
-               ret = device_create_file(adev->dev, &dev_attr_pp_dpm_dcefclk);
-               if (ret) {
-                       DRM_ERROR("failed to create device file pp_dpm_dcefclk\n");
-                       return ret;
+               if (adev->asic_type != CHIP_ARCTURUS) {
+                       ret = device_create_file(adev->dev, &dev_attr_pp_dpm_dcefclk);
+                       if (ret) {
+                               DRM_ERROR("failed to create device file pp_dpm_dcefclk\n");
+                               return ret;
+                       }
                 }
         }
         if (adev->asic_type >= CHIP_VEGA20) {
@@ -2892,10 +2894,12 @@ int amdgpu_pm_sysfs_init(struct amdgpu_device *adev)
                         return ret;
                 }
         }
-       ret = device_create_file(adev->dev, &dev_attr_pp_dpm_pcie);
-       if (ret) {
-               DRM_ERROR("failed to create device file pp_dpm_pcie\n");
-               return ret;
+       if (adev->asic_type != CHIP_ARCTURUS) {
+               ret = device_create_file(adev->dev, &dev_attr_pp_dpm_pcie);
+               if (ret) {
+                       DRM_ERROR("failed to create device file pp_dpm_pcie\n");
+                       return ret;
+               }
         }
         ret = device_create_file(adev->dev, &dev_attr_pp_sclk_od);
         if (ret) {
@@ -2999,9 +3003,11 @@ void amdgpu_pm_sysfs_fini(struct amdgpu_device *adev)
         device_remove_file(adev->dev, &dev_attr_pp_dpm_mclk);
         if (adev->asic_type >= CHIP_VEGA10) {
                 device_remove_file(adev->dev, &dev_attr_pp_dpm_socclk);
-               device_remove_file(adev->dev, &dev_attr_pp_dpm_dcefclk);
+               if (adev->asic_type != CHIP_ARCTURUS)
+                       device_remove_file(adev->dev, &dev_attr_pp_dpm_dcefclk);
         }
-       device_remove_file(adev->dev, &dev_attr_pp_dpm_pcie);
+       if (adev->asic_type != CHIP_ARCTURUS)
+               device_remove_file(adev->dev, &dev_attr_pp_dpm_pcie);
         if (adev->asic_type >= CHIP_VEGA20)
                 device_remove_file(adev->dev, &dev_attr_pp_dpm_fclk);
         device_remove_file(adev->dev, &dev_attr_pp_sclk_od);
--
2.22.0

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RE: [PATCH 3/4] drm/amd/powerplay: get bootup fclk value

[Quan, Evan]

[-- Attachment #1.1: Type: text/plain, Size: 5461 bytes --]

Ping..

From: Quan, Evan
Sent: Friday, August 16, 2019 4:00 PM
To: Wang, Kevin(Yang) <Kevin1.Wang-5C7GfCeVMHo@public.gmane.org>; amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
Subject: RE: [PATCH 3/4] drm/amd/powerplay: get bootup fclk value

Since smu_get_atom_data_table() was already used in smu_v11_0_get_vbios_bootup_values(). We should get all our needed information at once.
Also, what smu_get_atom_data_table() does is to get the data table from vbios. It's a time and resource cost job.
I do not think it's a good idea to call it again just to get some information we should already know.

Regards,
Evan
From: Wang, Kevin(Yang) <Kevin1.Wang-5C7GfCeVMHo@public.gmane.org<mailto:Kevin1.Wang-5C7GfCeVMHo@public.gmane.org>>
Sent: Friday, August 16, 2019 3:10 PM
To: Quan, Evan <Evan.Quan-5C7GfCeVMHo@public.gmane.org<mailto:Evan.Quan-5C7GfCeVMHo@public.gmane.org>>; amd-gfx@lists.freedesktop.org<mailto:amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org>
Subject: Re: [PATCH 3/4] drm/amd/powerplay: get bootup fclk value

i think we can use a function to retrieve this information without storing it separately.
likes:  ret = smu_get_atom_data_table(smu, index, &size, &frev, &crev,
                                      (uint8_t **)&header);
because these information is a generic information from atom_common_table_header.
and other function don't care it except in smu_v11_0_get_clk_info_from_vbios.

Best Regards,
Kevin
________________________________
From: amd-gfx <amd-gfx-bounces-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org<mailto:amd-gfx-bounces@lists.freedesktop.org>> on behalf of Evan Quan <evan.quan-5C7GfCeVMHo@public.gmane.org<mailto:evan.quan-5C7GfCeVMHo@public.gmane.org>>
Sent: Friday, August 16, 2019 2:08 PM
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org<mailto:amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org> <amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org<mailto:amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org>>
Cc: Quan, Evan <Evan.Quan-5C7GfCeVMHo@public.gmane.org<mailto:Evan.Quan-5C7GfCeVMHo@public.gmane.org>>
Subject: [PATCH 3/4] drm/amd/powerplay: get bootup fclk value

This is available with firmwareinfo table v3.2 or later.

Change-Id: I223edf3c616b9e3e2527c752214fef5ab53d1cea
Signed-off-by: Evan Quan <evan.quan-5C7GfCeVMHo@public.gmane.org<mailto:evan.quan-5C7GfCeVMHo@public.gmane.org>>
---
 .../gpu/drm/amd/powerplay/inc/amdgpu_smu.h    |  3 +++
 drivers/gpu/drm/amd/powerplay/smu_v11_0.c     | 21 +++++++++++++++++++
 2 files changed, 24 insertions(+)

diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
index ca9b9ec39de8..2c16eb412954 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
@@ -222,6 +222,9 @@ struct smu_bios_boot_up_values
         uint16_t                        vdd_gfx;
         uint8_t                         cooling_id;
         uint32_t                        pp_table_id;
+       uint32_t                        format_revision;
+       uint32_t                        content_revision;
+       uint32_t                        fclk;
 };

 enum smu_table_id
diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
index 4a51de4ff162..df7b65360ac7 100644
--- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
@@ -568,6 +568,9 @@ int smu_v11_0_get_vbios_bootup_values(struct smu_context *smu)
                 smu->smu_table.boot_values.pp_table_id = v_3_3->pplib_pptable_id;
         }

+       smu->smu_table.boot_values.format_revision = header->format_revision;
+       smu->smu_table.boot_values.content_revision = header->content_revision;
+
         return 0;
 }

@@ -647,6 +650,24 @@ static int smu_v11_0_get_clk_info_from_vbios(struct smu_context *smu)
         output = (struct atom_get_smu_clock_info_output_parameters_v3_1 *)&input;
         smu->smu_table.boot_values.dclk = le32_to_cpu(output->atom_smu_outputclkfreq.smu_clock_freq_hz) / 10000;

+       if ((smu->smu_table.boot_values.format_revision == 3) &&
+           (smu->smu_table.boot_values.content_revision >= 2)) {
+               memset(&input, 0, sizeof(input));
+               input.clk_id = SMU11_SYSPLL1_0_FCLK_ID;
+               input.syspll_id = SMU11_SYSPLL1_2_ID;
+               input.command = GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ;
+               index = get_index_into_master_table(atom_master_list_of_command_functions_v2_1,
+                                                   getsmuclockinfo);
+
+               ret = amdgpu_atom_execute_table(adev->mode_info.atom_context, index,
+                                               (uint32_t *)&input);
+               if (ret)
+                       return -EINVAL;
+
+               output = (struct atom_get_smu_clock_info_output_parameters_v3_1 *)&input;
+               smu->smu_table.boot_values.fclk = le32_to_cpu(output->atom_smu_outputclkfreq.smu_clock_freq_hz) / 10000;
+       }
+
         return 0;
 }

--
2.22.0

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Re: [PATCH 3/4] drm/amd/powerplay: get bootup fclk value

[Wang, Kevin(Yang)]

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Reviewed-by: Kevin Wang <kevin1.wang-5C7GfCeVMHo@public.gmane.org>

Best Regards,
Kevin
________________________________
From: Quan, Evan <Evan.Quan-5C7GfCeVMHo@public.gmane.org>
Sent: Tuesday, August 20, 2019 10:09 AM
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org <amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org>
Cc: Wang, Kevin(Yang) <Kevin1.Wang-5C7GfCeVMHo@public.gmane.org>
Subject: RE: [PATCH 3/4] drm/amd/powerplay: get bootup fclk value


Ping..



From: Quan, Evan
Sent: Friday, August 16, 2019 4:00 PM
To: Wang, Kevin(Yang) <Kevin1.Wang-5C7GfCeVMHo@public.gmane.org>; amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
Subject: RE: [PATCH 3/4] drm/amd/powerplay: get bootup fclk value



Since smu_get_atom_data_table() was already used in smu_v11_0_get_vbios_bootup_values(). We should get all our needed information at once.

Also, what smu_get_atom_data_table() does is to get the data table from vbios. It’s a time and resource cost job.

I do not think it’s a good idea to call it again just to get some information we should already know.



Regards,

Evan

From: Wang, Kevin(Yang) <Kevin1.Wang-5C7GfCeVMHo@public.gmane.org<mailto:Kevin1.Wang-5C7GfCeVMHo@public.gmane.org>>
Sent: Friday, August 16, 2019 3:10 PM
To: Quan, Evan <Evan.Quan-5C7GfCeVMHo@public.gmane.org<mailto:Evan.Quan-5C7GfCeVMHo@public.gmane.org>>; amd-gfx@lists.freedesktop.org<mailto:amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org>
Subject: Re: [PATCH 3/4] drm/amd/powerplay: get bootup fclk value



i think we can use a function to retrieve this information without storing it separately.

likes:  ret = smu_get_atom_data_table(smu, index, &size, &frev, &crev,
                                      (uint8_t **)&header);

because these information is a generic information from atom_common_table_header.

and other function don't care it except in smu_v11_0_get_clk_info_from_vbios.



Best Regards,
Kevin

________________________________

From: amd-gfx <amd-gfx-bounces-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org<mailto:amd-gfx-bounces@lists.freedesktop.org>> on behalf of Evan Quan <evan.quan-5C7GfCeVMHo@public.gmane.org<mailto:evan.quan-5C7GfCeVMHo@public.gmane.org>>
Sent: Friday, August 16, 2019 2:08 PM
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org<mailto:amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org> <amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org<mailto:amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org>>
Cc: Quan, Evan <Evan.Quan-5C7GfCeVMHo@public.gmane.org<mailto:Evan.Quan-5C7GfCeVMHo@public.gmane.org>>
Subject: [PATCH 3/4] drm/amd/powerplay: get bootup fclk value



This is available with firmwareinfo table v3.2 or later.

Change-Id: I223edf3c616b9e3e2527c752214fef5ab53d1cea
Signed-off-by: Evan Quan <evan.quan-5C7GfCeVMHo@public.gmane.org<mailto:evan.quan-5C7GfCeVMHo@public.gmane.org>>
---
 .../gpu/drm/amd/powerplay/inc/amdgpu_smu.h    |  3 +++
 drivers/gpu/drm/amd/powerplay/smu_v11_0.c     | 21 +++++++++++++++++++
 2 files changed, 24 insertions(+)

diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
index ca9b9ec39de8..2c16eb412954 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
@@ -222,6 +222,9 @@ struct smu_bios_boot_up_values
         uint16_t                        vdd_gfx;
         uint8_t                         cooling_id;
         uint32_t                        pp_table_id;
+       uint32_t                        format_revision;
+       uint32_t                        content_revision;
+       uint32_t                        fclk;
 };

 enum smu_table_id
diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
index 4a51de4ff162..df7b65360ac7 100644
--- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
@@ -568,6 +568,9 @@ int smu_v11_0_get_vbios_bootup_values(struct smu_context *smu)
                 smu->smu_table.boot_values.pp_table_id = v_3_3->pplib_pptable_id;
         }

+       smu->smu_table.boot_values.format_revision = header->format_revision;
+       smu->smu_table.boot_values.content_revision = header->content_revision;
+
         return 0;
 }

@@ -647,6 +650,24 @@ static int smu_v11_0_get_clk_info_from_vbios(struct smu_context *smu)
         output = (struct atom_get_smu_clock_info_output_parameters_v3_1 *)&input;
         smu->smu_table.boot_values.dclk = le32_to_cpu(output->atom_smu_outputclkfreq.smu_clock_freq_hz) / 10000;

+       if ((smu->smu_table.boot_values.format_revision == 3) &&
+           (smu->smu_table.boot_values.content_revision >= 2)) {
+               memset(&input, 0, sizeof(input));
+               input.clk_id = SMU11_SYSPLL1_0_FCLK_ID;
+               input.syspll_id = SMU11_SYSPLL1_2_ID;
+               input.command = GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ;
+               index = get_index_into_master_table(atom_master_list_of_command_functions_v2_1,
+                                                   getsmuclockinfo);
+
+               ret = amdgpu_atom_execute_table(adev->mode_info.atom_context, index,
+                                               (uint32_t *)&input);
+               if (ret)
+                       return -EINVAL;
+
+               output = (struct atom_get_smu_clock_info_output_parameters_v3_1 *)&input;
+               smu->smu_table.boot_values.fclk = le32_to_cpu(output->atom_smu_outputclkfreq.smu_clock_freq_hz) / 10000;
+       }
+
         return 0;
 }

--
2.22.0

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