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From: Lucas De Marchi <lucas.demarchi@intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [PATCH 01/39] drm/i915/tgl: do not use DDIC
Date: Fri, 16 Aug 2019 01:04:25 -0700	[thread overview]
Message-ID: <20190816080503.28594-2-lucas.demarchi@intel.com> (raw)
In-Reply-To: <20190816080503.28594-1-lucas.demarchi@intel.com>

On both A0 and A2 machines DDIC is not working. VBT reports the port as
being present. In BIOS configuration it seems to be disabled and can't
be enabled.

The symptom we have is while enabling the combo phy, PORT_COMP_DW*
return 0xFFFFFFFF, which is invalid per register definition.

During initialization we check what phys are not yet enabled by reading
PHY_MISC_C and try to enable it by toggling the "DE to IO Comp Pwr Down"
bit.  But after that any read to the PORT_COMP_DW* returns invalid
results. To me it looks like it's powered down and we can't bring it up.

This papers over the following warnings:

[56997.634353] Missing case (val == 4294967295)
[56997.639241] WARNING: CPU: 5 PID: 768 at drivers/gpu/drm/i915/display/intel_combo_phy.c:54 cnl_get_procmon_ref_values+0xc9/0xf0 [i915]
[56997.639808] Modules linked in: i915(+) prime_numbers x86_pkg_temp_thermal coretemp kvm_intel kvm irqbypass crct10dif_pclmul crc32_pclmul ghash_clmulni_intel e1000e [last unloaded: prime_numbers]
[56997.639808] CPU: 5 PID: 768 Comm: insmod Tainted: G     U  W         5.2.0-demarchi+ #65
[56997.639808] Hardware name: Intel Corporation Tiger Lake Client Platform/TigerLake U DDR4 SODIMM RVP, BIOS TGLSFWI1.R00.2252.A03.1906270154 06/27/2019
[56997.639808] RIP: 0010:cnl_get_procmon_ref_values+0xc9/0xf0 [i915]
[56997.639808] Code: 2c a0 85 c9 74 e0 81 f9 00 00 00 01 75 09 48 c7 c0 0c a4 2c a0 eb cf 48 c7 c6 3c 3a 31 a0 48 c7 c7 40 3a 31 a0 e8 6b 4d ea e0 <0f> 0b 48 c7 c0 00 a4 2c a0 eb b1 48 c7 c0 24 a4 2
c a0 eb a8 e8 be
[56997.639808] RSP: 0018:ffffc9000068f8a8 EFLAGS: 00010286
[56997.639808] RAX: 0000000000000000 RBX: ffff88848fa90000 RCX: 0000000000000000
[56997.639808] RDX: ffff8884a08b5ef8 RSI: ffff8884a08a6658 RDI: 00000000ffffffff
[56997.639808] RBP: 0000000000000002 R08: 0000000000000000 R09: 0000000000000000
[56997.639808] R10: 0000000000000000 R11: 0000000000000000 R12: ffff88848fa90000
[56997.639808] R13: 0000000000000000 R14: 0000000000000002 R15: 0006c00000162000
[56997.639808] FS:  00007f61ca3d12c0(0000) GS:ffff8884a0880000(0000) knlGS:0000000000000000
[56997.639808] CS:  0010 DS: 0000 ES: 0000 CR0: 0000000080050033
[56997.639808] CR2: 00007f71be6a92c0 CR3: 0000000494750006 CR4: 0000000000760ee0
[56997.639808] PKRU: 55555554
[56997.639808] Call Trace:
[56997.639808]  cnl_verify_procmon_ref_values+0x36/0xf0 [i915]
[56997.639808]  ? rcu_read_lock_sched_held+0x6f/0x80
[56997.639808]  ? gen11_fwtable_read32+0x257/0x290 [i915]
[56997.639808]  icl_combo_phy_verify_state.part.0+0x22/0xa0 [i915]
[56997.639808]  intel_combo_phy_init+0x17e/0x3e0 [i915]
[56997.639808]  ? icl_display_core_init+0x2c/0x1a0 [i915]
[56997.639808]  ? _raw_spin_unlock_irqrestore+0x4c/0x60
[56997.639808]  icl_display_core_init+0x34/0x1a0 [i915]
[56997.639808]  intel_power_domains_init_hw+0x200/0x570 [i915]
[56997.639808]  i915_driver_probe+0x103b/0x17e0 [i915]
[56997.639808]  ? printk+0x53/0x6a
[56997.639808]  i915_pci_probe+0x3b/0x190 [i915]

Feedback from people responsible for VBT:

	We got a confirmation that DDI-C is not pinned out in the
	packaging/disabled, probably this is the reason the Combo PHY C
	registers are not accessible. Once the spec is updated, we will remap
	DDI-C to No Display type and will hide configuration of DDI-C, so that
	it is not configurable by the user.

Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 5b733e38eae3..6c6a5a5f41bb 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -6683,7 +6683,7 @@ bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy phy)
 	if (phy == PHY_NONE)
 		return false;
 
-	if (IS_ELKHARTLAKE(dev_priv) || INTEL_GEN(dev_priv) >= 12)
+	if (IS_ELKHARTLAKE(dev_priv))
 		return phy <= PHY_C;
 
 	if (INTEL_GEN(dev_priv) >= 11)
@@ -15317,7 +15317,6 @@ static void intel_setup_outputs(struct drm_i915_private *dev_priv)
 		/* TODO: initialize TC ports as well */
 		intel_ddi_init(dev_priv, PORT_A);
 		intel_ddi_init(dev_priv, PORT_B);
-		intel_ddi_init(dev_priv, PORT_C);
 		icl_dsi_init(dev_priv);
 	} else if (IS_ELKHARTLAKE(dev_priv)) {
 		intel_ddi_init(dev_priv, PORT_A);
-- 
2.21.0

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  reply	other threads:[~2019-08-16  8:05 UTC|newest]

Thread overview: 58+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-08-16  8:04 [PATCH 00/39] Tiger Lake batch 3 Lucas De Marchi
2019-08-16  8:04 ` Lucas De Marchi [this message]
2019-08-16  8:04 ` [PATCH 02/39] drm/i915/psr: Make PSR registers relative to transcoders Lucas De Marchi
2019-08-16  8:04 ` [PATCH 03/39] drm/i915: Add transcoder restriction to PSR2 Lucas De Marchi
2019-08-16  8:04 ` [PATCH 04/39] drm/i915: Do not unmask PSR interruption in IRQ postinstall Lucas De Marchi
2019-08-16  8:04 ` [PATCH 05/39] drm/i915/psr: Only handle interruptions of the transcoder in use Lucas De Marchi
2019-08-16  8:04 ` [PATCH 06/39] drm/i915/bdw+: Enable PSR in any eDP port Lucas De Marchi
2019-08-22 16:20   ` Gupta, Anshuman
2019-08-22 16:42     ` Gupta, Anshuman
2019-08-16  8:04 ` [PATCH 07/39] drm/i915: Guard and warn if more than one eDP panel is present Lucas De Marchi
2019-08-16  8:04 ` [PATCH 08/39] drm/i915/tgl: Change PSR2 transcoder restriction Lucas De Marchi
2019-08-16 21:28   ` Lucas De Marchi
2019-08-16 21:59     ` Souza, Jose
2019-08-16  8:04 ` [PATCH 09/39] drm/i915: Do not read PSR2 register in transcoders without PSR2 Lucas De Marchi
2019-08-16  8:04 ` [PATCH 10/39] drm/i915/tgl: PSR link standby is not supported anymore Lucas De Marchi
2019-08-22  9:54   ` Gupta, Anshuman
2019-08-16  8:04 ` [PATCH 11/39] drm/i915/tgl: Access the right register when handling PSR interruptions Lucas De Marchi
2019-08-16  8:04 ` [PATCH 12/39] drm/i915/tgl: Add maximum resolution supported by PSR2 HW Lucas De Marchi
2019-08-22 16:46   ` Gupta, Anshuman
2019-08-16  8:04 ` [PATCH 13/39] drm/i915/mst: Do not hardcoded the crtcs that encoder can connect Lucas De Marchi
2019-08-16  8:04 ` [PATCH 14/39] drm/i915: Add for_each_new_intel_connector_in_state() Lucas De Marchi
2019-08-22 12:55   ` Maarten Lankhorst
2019-08-16  8:04 ` [PATCH 15/39] drm: Add for_each_oldnew_intel_crtc_in_state_reverse() Lucas De Marchi
2019-08-16  8:04 ` [PATCH 16/39] drm/i915: Disable pipes in reverse order Lucas De Marchi
2019-08-16  8:04 ` [PATCH 17/39] drm/i915/tgl: Select master transcoder in DP MST Lucas De Marchi
2019-08-16  8:04 ` [PATCH 18/39] drm/i915/tgl: Introduce initial Tiger Lake workarounds Lucas De Marchi
2019-08-16  8:04 ` [PATCH 19/39] drm/i915/tgl: Implement Wa_1406941453 Lucas De Marchi
2019-08-16  8:04 ` [PATCH 20/39] drm/i915/tgl: Enable VD HCP/MFX sub-pipe power gating Lucas De Marchi
2019-08-16  8:04 ` [PATCH 21/39] drm/i915/tgl: Do not apply WaIncreaseDefaultTLBEntries from GEN12 onwards Lucas De Marchi
2019-08-16  8:04 ` [PATCH 22/39] drm/i915/tgl: implement WaProgramMgsrForCorrectSliceSpecificMmioReads Lucas De Marchi
2019-08-16  8:04 ` [PATCH 23/39] drm/i915/tgl: Register state context definition for Gen12 Lucas De Marchi
2019-08-16  8:04 ` [PATCH 24/39] drm/i915/tgl: move DP_TP_* to transcoder Lucas De Marchi
2019-08-16  8:04 ` [PATCH 25/39] drm/i915/tgl: Implement TGL DisplayPort training sequence Lucas De Marchi
2019-08-19 14:21   ` Maarten Lankhorst
2019-08-19 21:26     ` Souza, Jose
2019-08-16  8:04 ` [PATCH 26/39] HACK: drm/i915/tgl: Gen12 render context size Lucas De Marchi
2019-08-16  8:04 ` [PATCH 27/39] drm/i915/tgl: add Gen12 default indirect ctx offset Lucas De Marchi
2019-08-16  8:04 ` [PATCH 28/39] drm/i915/tgl: add GEN12_MAX_CONTEXT_HW_ID Lucas De Marchi
2019-08-16  8:04 ` [PATCH 29/39] drm/i915/tgl: Report valid VDBoxes with SFC capability Lucas De Marchi
2019-08-16  8:04 ` [PATCH 30/39] drm/i915/tgl: Move GTCR register to cope with GAM MMIO address remap Lucas De Marchi
2019-08-16  8:04 ` [PATCH 31/39] drm/i915/tgl: Updated Private PAT programming Lucas De Marchi
2019-08-16  8:04 ` [PATCH 32/39] drm/i915/tgl/perf: use the same oa ctx_id format as icl Lucas De Marchi
2019-08-16  8:04 ` [PATCH 33/39] drm/i915/perf: add a parameter to control the size of OA buffer Lucas De Marchi
2019-08-19 18:31   ` Umesh Nerlige Ramappa
2019-08-21  8:37   ` Lionel Landwerlin
2019-08-22 10:43   ` Joonas Lahtinen
2019-08-22 12:13     ` Lionel Landwerlin
2019-08-23  8:30       ` Lucas De Marchi
2019-08-16  8:04 ` [PATCH 34/39] drm/i915/tgl: Add perf support on TGL Lucas De Marchi
2019-08-16  8:04 ` [PATCH 35/39] drm/i915/tgl: Gen-12 display loses Yf tiling and legacy CCS support Lucas De Marchi
2019-08-16  8:05 ` [PATCH 36/39] drm/framebuffer/tgl: Format modifier for Intel Gen-12 render compression Lucas De Marchi
2019-08-16  8:05 ` [PATCH 37/39] drm/i915/tgl: Gen-12 render decompression Lucas De Marchi
2019-08-16  8:05 ` [PATCH 38/39] drm/framebuffer/tgl: Format modifier for Intel Gen-12 media compression Lucas De Marchi
2019-08-16  8:05 ` [PATCH 39/39] drm/i915/tgl: " Lucas De Marchi
2019-08-16  9:37 ` ✗ Fi.CI.CHECKPATCH: warning for Tiger Lake batch 3 Patchwork
2019-08-16  9:51 ` ✗ Fi.CI.SPARSE: " Patchwork
2019-08-16  9:57 ` ✓ Fi.CI.BAT: success " Patchwork
2019-08-16 21:26 ` ✓ Fi.CI.IGT: " Patchwork

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