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* [PATCH] drm/i915/selftests: Check the context size
@ 2019-08-16 17:58 Chris Wilson
  2019-08-16 18:43 ` Daniele Ceraolo Spurio
                   ` (6 more replies)
  0 siblings, 7 replies; 12+ messages in thread
From: Chris Wilson @ 2019-08-16 17:58 UTC (permalink / raw)
  To: intel-gfx

Add a redzone to our context image and check the HW does not write into
after a context save, to verify that we have the correct context size.
(This does vary with feature bits, so test with a live setup that should
match how we run userspace.)

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
---
 drivers/gpu/drm/i915/gt/selftest_context.c | 133 +++++++++++++++++++++
 1 file changed, 133 insertions(+)

diff --git a/drivers/gpu/drm/i915/gt/selftest_context.c b/drivers/gpu/drm/i915/gt/selftest_context.c
index 6fbc72bc290e..69f2233104f1 100644
--- a/drivers/gpu/drm/i915/gt/selftest_context.c
+++ b/drivers/gpu/drm/i915/gt/selftest_context.c
@@ -5,6 +5,7 @@
  */
 
 #include "i915_selftest.h"
+#include "intel_engine_pm.h"
 #include "intel_gt.h"
 
 #include "gem/selftests/mock_context.h"
@@ -64,6 +65,137 @@ static int context_sync(struct intel_context *ce)
 	return err;
 }
 
+static int __live_context_size(struct intel_engine_cs *engine,
+			       struct i915_gem_context *fixme)
+{
+	struct intel_context *ce;
+	struct i915_request *rq;
+	void *vaddr;
+	int err;
+
+	ce = intel_context_create(fixme, engine);
+	if (IS_ERR(ce))
+		return PTR_ERR(ce);
+
+	err = intel_context_pin(ce);
+	if (err)
+		goto err;
+
+	vaddr = i915_gem_object_pin_map(ce->state->obj,
+					i915_coherent_map_type(engine->i915));
+	if (IS_ERR(vaddr)) {
+		err = PTR_ERR(vaddr);
+		intel_context_unpin(ce);
+		goto err;
+	}
+
+	if (HAS_EXECLISTS(engine->i915))
+		vaddr += LRC_HEADER_PAGES * PAGE_SIZE;
+
+	vaddr += engine->context_size - I915_GTT_PAGE_SIZE;
+	memset(vaddr, POISON_INUSE, I915_GTT_PAGE_SIZE);
+
+	rq = intel_context_create_request(ce);
+	intel_context_unpin(ce);
+	if (IS_ERR(rq)) {
+		err = PTR_ERR(rq);
+		goto err_unpin;
+	}
+
+	err = request_sync(rq);
+	if (err)
+		goto err_unpin;
+
+	/* Force the context switch */
+	rq = i915_request_create(engine->kernel_context);
+	if (IS_ERR(rq)) {
+		err = PTR_ERR(rq);
+		goto err_unpin;
+	}
+	err = request_sync(rq);
+	if (err)
+		goto err_unpin;
+
+	if (memchr_inv(vaddr, POISON_INUSE, I915_GTT_PAGE_SIZE)) {
+		pr_err("%s context overwrote trailing red-zone!", engine->name);
+		err = -EINVAL;
+	}
+
+err_unpin:
+	i915_gem_object_unpin_map(ce->state->obj);
+err:
+	intel_context_put(ce);
+	return err;
+}
+
+static int live_context_size(void *arg)
+{
+	struct intel_gt *gt = arg;
+	struct intel_engine_cs *engine;
+	struct i915_gem_context *fixme;
+	enum intel_engine_id id;
+	struct drm_file *file;
+	int err = 0;
+
+	/*
+	 * Check that are context sizes are correct by seeing if the
+	 * HW tries to write past the end of one.
+	 */
+
+	file = mock_file(gt->i915);
+	if (IS_ERR(file))
+		return PTR_ERR(file);
+
+	mutex_lock(&gt->i915->drm.struct_mutex);
+
+	fixme = live_context(gt->i915, file);
+	if (IS_ERR(fixme)) {
+		err = PTR_ERR(fixme);
+		goto unlock;
+	}
+
+	for_each_engine(engine, gt->i915, id) {
+		struct {
+			struct drm_i915_gem_object *state;
+			void *pinned;
+		} saved;
+
+		if (!engine->context_size)
+			continue;
+
+		intel_engine_pm_get(engine);
+
+		/*
+		 * Hide the old default state -- we lie about the context size
+		 * and get confused when the default state is smaller than
+		 * expected. For our do nothing request, inheriting the
+		 * active state is sufficient, we are only checking that we
+		 * don't use more than we planned.
+		 */
+		saved.state = fetch_and_zero(&engine->default_state);
+		saved.pinned = fetch_and_zero(&engine->pinned_default_state);
+
+		engine->context_size += I915_GTT_PAGE_SIZE;
+
+		err = __live_context_size(engine, fixme);
+
+		engine->context_size -= I915_GTT_PAGE_SIZE;
+
+		engine->pinned_default_state = saved.pinned;
+		engine->default_state = saved.state;
+
+		intel_engine_pm_put(engine);
+
+		if (err)
+			break;
+	}
+
+unlock:
+	mutex_unlock(&gt->i915->drm.struct_mutex);
+	mock_file_free(gt->i915, file);
+	return err;
+}
+
 static int __live_active_context(struct intel_engine_cs *engine,
 				 struct i915_gem_context *fixme)
 {
@@ -303,6 +435,7 @@ static int live_remote_context(void *arg)
 int intel_context_live_selftests(struct drm_i915_private *i915)
 {
 	static const struct i915_subtest tests[] = {
+		SUBTEST(live_context_size),
 		SUBTEST(live_active_context),
 		SUBTEST(live_remote_context),
 	};
-- 
2.23.0.rc1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 12+ messages in thread

* Re: [PATCH] drm/i915/selftests: Check the context size
  2019-08-16 17:58 [PATCH] drm/i915/selftests: Check the context size Chris Wilson
@ 2019-08-16 18:43 ` Daniele Ceraolo Spurio
  2019-08-16 18:50   ` Chris Wilson
  2019-08-16 19:09 ` [PATCH v2] " Chris Wilson
                   ` (5 subsequent siblings)
  6 siblings, 1 reply; 12+ messages in thread
From: Daniele Ceraolo Spurio @ 2019-08-16 18:43 UTC (permalink / raw)
  To: Chris Wilson, intel-gfx



On 8/16/19 10:58 AM, Chris Wilson wrote:
> Add a redzone to our context image and check the HW does not write into
> after a context save, to verify that we have the correct context size.
> (This does vary with feature bits, so test with a live setup that should
> match how we run userspace.)
> 

On newer gens the data saved during the ctx switch is variable, based on 
the type of switch and the current state of the HW, e.g. some state is 
only saved during a preemption, and the ctx layout is compressed 
accordingly. We'd need the test to generate the maximum possible size 
(and I have no idea which usage case produces that), but I don't think 
that'd scale well from gen to gen.

Daniele

> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> ---
>   drivers/gpu/drm/i915/gt/selftest_context.c | 133 +++++++++++++++++++++
>   1 file changed, 133 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/gt/selftest_context.c b/drivers/gpu/drm/i915/gt/selftest_context.c
> index 6fbc72bc290e..69f2233104f1 100644
> --- a/drivers/gpu/drm/i915/gt/selftest_context.c
> +++ b/drivers/gpu/drm/i915/gt/selftest_context.c
> @@ -5,6 +5,7 @@
>    */
>   
>   #include "i915_selftest.h"
> +#include "intel_engine_pm.h"
>   #include "intel_gt.h"
>   
>   #include "gem/selftests/mock_context.h"
> @@ -64,6 +65,137 @@ static int context_sync(struct intel_context *ce)
>   	return err;
>   }
>   
> +static int __live_context_size(struct intel_engine_cs *engine,
> +			       struct i915_gem_context *fixme)
> +{
> +	struct intel_context *ce;
> +	struct i915_request *rq;
> +	void *vaddr;
> +	int err;
> +
> +	ce = intel_context_create(fixme, engine);
> +	if (IS_ERR(ce))
> +		return PTR_ERR(ce);
> +
> +	err = intel_context_pin(ce);
> +	if (err)
> +		goto err;
> +
> +	vaddr = i915_gem_object_pin_map(ce->state->obj,
> +					i915_coherent_map_type(engine->i915));
> +	if (IS_ERR(vaddr)) {
> +		err = PTR_ERR(vaddr);
> +		intel_context_unpin(ce);
> +		goto err;
> +	}
> +
> +	if (HAS_EXECLISTS(engine->i915))
> +		vaddr += LRC_HEADER_PAGES * PAGE_SIZE;
> +
> +	vaddr += engine->context_size - I915_GTT_PAGE_SIZE;
> +	memset(vaddr, POISON_INUSE, I915_GTT_PAGE_SIZE);
> +
> +	rq = intel_context_create_request(ce);
> +	intel_context_unpin(ce);
> +	if (IS_ERR(rq)) {
> +		err = PTR_ERR(rq);
> +		goto err_unpin;
> +	}
> +
> +	err = request_sync(rq);
> +	if (err)
> +		goto err_unpin;
> +
> +	/* Force the context switch */
> +	rq = i915_request_create(engine->kernel_context);
> +	if (IS_ERR(rq)) {
> +		err = PTR_ERR(rq);
> +		goto err_unpin;
> +	}
> +	err = request_sync(rq);
> +	if (err)
> +		goto err_unpin;
> +
> +	if (memchr_inv(vaddr, POISON_INUSE, I915_GTT_PAGE_SIZE)) {
> +		pr_err("%s context overwrote trailing red-zone!", engine->name);
> +		err = -EINVAL;
> +	}
> +
> +err_unpin:
> +	i915_gem_object_unpin_map(ce->state->obj);
> +err:
> +	intel_context_put(ce);
> +	return err;
> +}
> +
> +static int live_context_size(void *arg)
> +{
> +	struct intel_gt *gt = arg;
> +	struct intel_engine_cs *engine;
> +	struct i915_gem_context *fixme;
> +	enum intel_engine_id id;
> +	struct drm_file *file;
> +	int err = 0;
> +
> +	/*
> +	 * Check that are context sizes are correct by seeing if the
> +	 * HW tries to write past the end of one.
> +	 */
> +
> +	file = mock_file(gt->i915);
> +	if (IS_ERR(file))
> +		return PTR_ERR(file);
> +
> +	mutex_lock(&gt->i915->drm.struct_mutex);
> +
> +	fixme = live_context(gt->i915, file);
> +	if (IS_ERR(fixme)) {
> +		err = PTR_ERR(fixme);
> +		goto unlock;
> +	}
> +
> +	for_each_engine(engine, gt->i915, id) {
> +		struct {
> +			struct drm_i915_gem_object *state;
> +			void *pinned;
> +		} saved;
> +
> +		if (!engine->context_size)
> +			continue;
> +
> +		intel_engine_pm_get(engine);
> +
> +		/*
> +		 * Hide the old default state -- we lie about the context size
> +		 * and get confused when the default state is smaller than
> +		 * expected. For our do nothing request, inheriting the
> +		 * active state is sufficient, we are only checking that we
> +		 * don't use more than we planned.
> +		 */
> +		saved.state = fetch_and_zero(&engine->default_state);
> +		saved.pinned = fetch_and_zero(&engine->pinned_default_state);
> +
> +		engine->context_size += I915_GTT_PAGE_SIZE;
> +
> +		err = __live_context_size(engine, fixme);
> +
> +		engine->context_size -= I915_GTT_PAGE_SIZE;
> +
> +		engine->pinned_default_state = saved.pinned;
> +		engine->default_state = saved.state;
> +
> +		intel_engine_pm_put(engine);
> +
> +		if (err)
> +			break;
> +	}
> +
> +unlock:
> +	mutex_unlock(&gt->i915->drm.struct_mutex);
> +	mock_file_free(gt->i915, file);
> +	return err;
> +}
> +
>   static int __live_active_context(struct intel_engine_cs *engine,
>   				 struct i915_gem_context *fixme)
>   {
> @@ -303,6 +435,7 @@ static int live_remote_context(void *arg)
>   int intel_context_live_selftests(struct drm_i915_private *i915)
>   {
>   	static const struct i915_subtest tests[] = {
> +		SUBTEST(live_context_size),
>   		SUBTEST(live_active_context),
>   		SUBTEST(live_remote_context),
>   	};
> 
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 12+ messages in thread

* Re: [PATCH] drm/i915/selftests: Check the context size
  2019-08-16 18:43 ` Daniele Ceraolo Spurio
@ 2019-08-16 18:50   ` Chris Wilson
  0 siblings, 0 replies; 12+ messages in thread
From: Chris Wilson @ 2019-08-16 18:50 UTC (permalink / raw)
  To: Daniele Ceraolo Spurio, intel-gfx

Quoting Daniele Ceraolo Spurio (2019-08-16 19:43:47)
> 
> 
> On 8/16/19 10:58 AM, Chris Wilson wrote:
> > Add a redzone to our context image and check the HW does not write into
> > after a context save, to verify that we have the correct context size.
> > (This does vary with feature bits, so test with a live setup that should
> > match how we run userspace.)
> > 
> 
> On newer gens the data saved during the ctx switch is variable, based on 
> the type of switch and the current state of the HW, e.g. some state is 
> only saved during a preemption, and the ctx layout is compressed 
> accordingly. We'd need the test to generate the maximum possible size 
> (and I have no idea which usage case produces that), but I don't think 
> that'd scale well from gen to gen.

I'd take this as a starting point, and we can definitely generate
preemption events easily etc -- it's only when it start depending on state
set by userspace do we run into logistical problems (I can only dread
encountering such a bug in the wild).

So v2, add a redzone everywhere and check on context unpinning.
-Chris
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 12+ messages in thread

* [PATCH v2] drm/i915/selftests: Check the context size
  2019-08-16 17:58 [PATCH] drm/i915/selftests: Check the context size Chris Wilson
  2019-08-16 18:43 ` Daniele Ceraolo Spurio
@ 2019-08-16 19:09 ` Chris Wilson
  2019-08-16 19:09 ` ✗ Fi.CI.BAT: failure for " Patchwork
                   ` (4 subsequent siblings)
  6 siblings, 0 replies; 12+ messages in thread
From: Chris Wilson @ 2019-08-16 19:09 UTC (permalink / raw)
  To: intel-gfx

Add a redzone to our context image and check the HW does not write into
after a context save, to verify that we have the correct context size.
(This does vary with feature bits, so test with a live setup that should
match how we run userspace.)

v2: Check the redzone on every context unpin

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_lrc.c        |  33 +++++
 drivers/gpu/drm/i915/gt/selftest_context.c | 133 +++++++++++++++++++++
 2 files changed, 166 insertions(+)

diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
index e9863f4d826b..ade212686bf6 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -1578,9 +1578,38 @@ static void execlists_context_destroy(struct kref *kref)
 	intel_context_fini(ce);
 	intel_context_free(ce);
 }
+static void
+set_redzone(void *vaddr, const struct intel_engine_cs *engine)
+{
+	if (!IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM))
+		return;
+
+	vaddr += LRC_HEADER_PAGES * PAGE_SIZE;
+	vaddr += engine->context_size;
+
+	memset(vaddr, POISON_INUSE, I915_GTT_PAGE_SIZE);
+}
+
+static void
+check_redzone(const void *vaddr, const struct intel_engine_cs *engine)
+{
+	if (!IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM))
+		return;
+
+	vaddr += LRC_HEADER_PAGES * PAGE_SIZE;
+	vaddr += engine->context_size;
+
+	if (memchr_inv(vaddr, POISON_INUSE, I915_GTT_PAGE_SIZE))
+		dev_err_once(engine->i915->drm.dev,
+			     "%s context redzone overwritten!\n",
+			     engine->name);
+}
 
 static void execlists_context_unpin(struct intel_context *ce)
 {
+	check_redzone((void *)ce->lrc_reg_state - LRC_STATE_PN * PAGE_SIZE,
+		      ce->engine);
+
 	i915_gem_context_unpin_hw_id(ce->gem_context);
 	i915_gem_object_unpin_map(ce->state->obj);
 	intel_ring_reset(ce->ring, ce->ring->tail);
@@ -3119,6 +3148,8 @@ populate_lr_context(struct intel_context *ce,
 		return ret;
 	}
 
+	set_redzone(vaddr, engine);
+
 	if (engine->default_state) {
 		/*
 		 * We only want to copy over the template context state;
@@ -3173,6 +3204,8 @@ static int __execlists_context_alloc(struct intel_context *ce,
 	 * for our own use and for sharing with the GuC.
 	 */
 	context_size += LRC_HEADER_PAGES * PAGE_SIZE;
+	if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM))
+		context_size += I915_GTT_PAGE_SIZE; /* for redzone */
 
 	ctx_obj = i915_gem_object_create_shmem(engine->i915, context_size);
 	if (IS_ERR(ctx_obj))
diff --git a/drivers/gpu/drm/i915/gt/selftest_context.c b/drivers/gpu/drm/i915/gt/selftest_context.c
index 6fbc72bc290e..0d3afbf4d4dc 100644
--- a/drivers/gpu/drm/i915/gt/selftest_context.c
+++ b/drivers/gpu/drm/i915/gt/selftest_context.c
@@ -5,6 +5,7 @@
  */
 
 #include "i915_selftest.h"
+#include "intel_engine_pm.h"
 #include "intel_gt.h"
 
 #include "gem/selftests/mock_context.h"
@@ -64,6 +65,137 @@ static int context_sync(struct intel_context *ce)
 	return err;
 }
 
+static int __live_context_size(struct intel_engine_cs *engine,
+			       struct i915_gem_context *fixme)
+{
+	struct intel_context *ce;
+	struct i915_request *rq;
+	void *vaddr;
+	int err;
+
+	ce = intel_context_create(fixme, engine);
+	if (IS_ERR(ce))
+		return PTR_ERR(ce);
+
+	err = intel_context_pin(ce);
+	if (err)
+		goto err;
+
+	vaddr = i915_gem_object_pin_map(ce->state->obj,
+					i915_coherent_map_type(engine->i915));
+	if (IS_ERR(vaddr)) {
+		err = PTR_ERR(vaddr);
+		intel_context_unpin(ce);
+		goto err;
+	}
+
+	if (HAS_EXECLISTS(engine->i915))
+		vaddr += LRC_HEADER_PAGES * PAGE_SIZE;
+
+	vaddr += engine->context_size - I915_GTT_PAGE_SIZE;
+	memset(vaddr, POISON_INUSE, I915_GTT_PAGE_SIZE);
+
+	rq = intel_context_create_request(ce);
+	intel_context_unpin(ce);
+	if (IS_ERR(rq)) {
+		err = PTR_ERR(rq);
+		goto err_unpin;
+	}
+
+	err = request_sync(rq);
+	if (err)
+		goto err_unpin;
+
+	/* Force the context switch */
+	rq = i915_request_create(engine->kernel_context);
+	if (IS_ERR(rq)) {
+		err = PTR_ERR(rq);
+		goto err_unpin;
+	}
+	err = request_sync(rq);
+	if (err)
+		goto err_unpin;
+
+	if (memchr_inv(vaddr, POISON_INUSE, I915_GTT_PAGE_SIZE)) {
+		pr_err("%s context overwrote trailing red-zone!", engine->name);
+		err = -EINVAL;
+	}
+
+err_unpin:
+	i915_gem_object_unpin_map(ce->state->obj);
+err:
+	intel_context_put(ce);
+	return err;
+}
+
+static int live_context_size(void *arg)
+{
+	struct intel_gt *gt = arg;
+	struct intel_engine_cs *engine;
+	struct i915_gem_context *fixme;
+	enum intel_engine_id id;
+	struct drm_file *file;
+	int err = 0;
+
+	/*
+	 * Check that our context sizes are correct by seeing if the
+	 * HW tries to write past the end of one.
+	 */
+
+	file = mock_file(gt->i915);
+	if (IS_ERR(file))
+		return PTR_ERR(file);
+
+	mutex_lock(&gt->i915->drm.struct_mutex);
+
+	fixme = live_context(gt->i915, file);
+	if (IS_ERR(fixme)) {
+		err = PTR_ERR(fixme);
+		goto unlock;
+	}
+
+	for_each_engine(engine, gt->i915, id) {
+		struct {
+			struct drm_i915_gem_object *state;
+			void *pinned;
+		} saved;
+
+		if (!engine->context_size)
+			continue;
+
+		intel_engine_pm_get(engine);
+
+		/*
+		 * Hide the old default state -- we lie about the context size
+		 * and get confused when the default state is smaller than
+		 * expected. For our do nothing request, inheriting the
+		 * active state is sufficient, we are only checking that we
+		 * don't use more than we planned.
+		 */
+		saved.state = fetch_and_zero(&engine->default_state);
+		saved.pinned = fetch_and_zero(&engine->pinned_default_state);
+
+		engine->context_size += I915_GTT_PAGE_SIZE;
+
+		err = __live_context_size(engine, fixme);
+
+		engine->context_size -= I915_GTT_PAGE_SIZE;
+
+		engine->pinned_default_state = saved.pinned;
+		engine->default_state = saved.state;
+
+		intel_engine_pm_put(engine);
+
+		if (err)
+			break;
+	}
+
+unlock:
+	mutex_unlock(&gt->i915->drm.struct_mutex);
+	mock_file_free(gt->i915, file);
+	return err;
+}
+
 static int __live_active_context(struct intel_engine_cs *engine,
 				 struct i915_gem_context *fixme)
 {
@@ -303,6 +435,7 @@ static int live_remote_context(void *arg)
 int intel_context_live_selftests(struct drm_i915_private *i915)
 {
 	static const struct i915_subtest tests[] = {
+		SUBTEST(live_context_size),
 		SUBTEST(live_active_context),
 		SUBTEST(live_remote_context),
 	};
-- 
2.23.0.rc1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 12+ messages in thread

* ✗ Fi.CI.BAT: failure for drm/i915/selftests: Check the context size
  2019-08-16 17:58 [PATCH] drm/i915/selftests: Check the context size Chris Wilson
  2019-08-16 18:43 ` Daniele Ceraolo Spurio
  2019-08-16 19:09 ` [PATCH v2] " Chris Wilson
@ 2019-08-16 19:09 ` Patchwork
  2019-08-16 19:17 ` [PATCH v3] " Chris Wilson
                   ` (3 subsequent siblings)
  6 siblings, 0 replies; 12+ messages in thread
From: Patchwork @ 2019-08-16 19:09 UTC (permalink / raw)
  To: Chris Wilson; +Cc: intel-gfx

== Series Details ==

Series: drm/i915/selftests: Check the context size
URL   : https://patchwork.freedesktop.org/series/65323/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_6720 -> Patchwork_14060
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with Patchwork_14060 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_14060, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14060/

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_14060:

### IGT changes ###

#### Possible regressions ####

  * igt@i915_selftest@live_gt_contexts:
    - fi-hsw-4770r:       [PASS][1] -> [DMESG-FAIL][2]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6720/fi-hsw-4770r/igt@i915_selftest@live_gt_contexts.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14060/fi-hsw-4770r/igt@i915_selftest@live_gt_contexts.html
    - fi-elk-e7500:       [PASS][3] -> [DMESG-FAIL][4]
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6720/fi-elk-e7500/igt@i915_selftest@live_gt_contexts.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14060/fi-elk-e7500/igt@i915_selftest@live_gt_contexts.html
    - fi-snb-2600:        [PASS][5] -> [DMESG-FAIL][6]
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6720/fi-snb-2600/igt@i915_selftest@live_gt_contexts.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14060/fi-snb-2600/igt@i915_selftest@live_gt_contexts.html
    - fi-hsw-peppy:       [PASS][7] -> [DMESG-FAIL][8]
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6720/fi-hsw-peppy/igt@i915_selftest@live_gt_contexts.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14060/fi-hsw-peppy/igt@i915_selftest@live_gt_contexts.html
    - fi-snb-2520m:       [PASS][9] -> [DMESG-FAIL][10]
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6720/fi-snb-2520m/igt@i915_selftest@live_gt_contexts.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14060/fi-snb-2520m/igt@i915_selftest@live_gt_contexts.html
    - fi-ilk-650:         [PASS][11] -> [DMESG-FAIL][12]
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6720/fi-ilk-650/igt@i915_selftest@live_gt_contexts.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14060/fi-ilk-650/igt@i915_selftest@live_gt_contexts.html
    - fi-hsw-4770:        [PASS][13] -> [DMESG-FAIL][14]
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6720/fi-hsw-4770/igt@i915_selftest@live_gt_contexts.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14060/fi-hsw-4770/igt@i915_selftest@live_gt_contexts.html

  
Known issues
------------

  Here are the changes found in Patchwork_14060 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_ctx_switch@legacy-render:
    - fi-bxt-dsi:         [PASS][15] -> [INCOMPLETE][16] ([fdo#103927])
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6720/fi-bxt-dsi/igt@gem_ctx_switch@legacy-render.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14060/fi-bxt-dsi/igt@gem_ctx_switch@legacy-render.html
    - fi-bxt-j4205:       [PASS][17] -> [INCOMPLETE][18] ([fdo#103927])
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6720/fi-bxt-j4205/igt@gem_ctx_switch@legacy-render.html
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14060/fi-bxt-j4205/igt@gem_ctx_switch@legacy-render.html

  * igt@prime_vgem@basic-fence-flip:
    - fi-icl-u3:          [PASS][19] -> [DMESG-WARN][20] ([fdo#107724]) +2 similar issues
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6720/fi-icl-u3/igt@prime_vgem@basic-fence-flip.html
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14060/fi-icl-u3/igt@prime_vgem@basic-fence-flip.html

  
#### Possible fixes ####

  * igt@i915_module_load@reload:
    - fi-icl-u3:          [DMESG-WARN][21] ([fdo#107724]) -> [PASS][22]
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6720/fi-icl-u3/igt@i915_module_load@reload.html
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14060/fi-icl-u3/igt@i915_module_load@reload.html

  * igt@i915_selftest@live_execlists:
    - fi-skl-gvtdvm:      [DMESG-FAIL][23] ([fdo#111108]) -> [PASS][24]
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6720/fi-skl-gvtdvm/igt@i915_selftest@live_execlists.html
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14060/fi-skl-gvtdvm/igt@i915_selftest@live_execlists.html

  * igt@i915_selftest@live_hangcheck:
    - fi-icl-u2:          [INCOMPLETE][25] ([fdo#107713] / [fdo#108569]) -> [PASS][26]
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6720/fi-icl-u2/igt@i915_selftest@live_hangcheck.html
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14060/fi-icl-u2/igt@i915_selftest@live_hangcheck.html

  * igt@i915_selftest@live_mman:
    - fi-bsw-kefka:       [DMESG-WARN][27] ([fdo#111373]) -> [PASS][28]
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6720/fi-bsw-kefka/igt@i915_selftest@live_mman.html
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14060/fi-bsw-kefka/igt@i915_selftest@live_mman.html

  
#### Warnings ####

  * igt@kms_chamelium@hdmi-hpd-fast:
    - fi-icl-u2:          [FAIL][29] ([fdo#109483]) -> [FAIL][30] ([fdo#111407])
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6720/fi-icl-u2/igt@kms_chamelium@hdmi-hpd-fast.html
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14060/fi-icl-u2/igt@kms_chamelium@hdmi-hpd-fast.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
  [fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
  [fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
  [fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569
  [fdo#109100]: https://bugs.freedesktop.org/show_bug.cgi?id=109100
  [fdo#109483]: https://bugs.freedesktop.org/show_bug.cgi?id=109483
  [fdo#111108]: https://bugs.freedesktop.org/show_bug.cgi?id=111108
  [fdo#111373]: https://bugs.freedesktop.org/show_bug.cgi?id=111373
  [fdo#111407]: https://bugs.freedesktop.org/show_bug.cgi?id=111407


Participating hosts (54 -> 46)
------------------------------

  Missing    (8): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-icl-y fi-byt-clapper fi-bdw-samus 


Build changes
-------------

  * CI: CI-20190529 -> None
  * Linux: CI_DRM_6720 -> Patchwork_14060

  CI-20190529: 20190529
  CI_DRM_6720: 7d0da9a1f86471d256afbc80f2cfa82e3aafa8ac @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5138: b9abe0bf6c478c4f6cac56bff286d6926ad8c0ab @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_14060: ed85ea88d8a7636b05a588f299cfe0e85c85626f @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

ed85ea88d8a7 drm/i915/selftests: Check the context size

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14060/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 12+ messages in thread

* [PATCH v3] drm/i915/selftests: Check the context size
  2019-08-16 17:58 [PATCH] drm/i915/selftests: Check the context size Chris Wilson
                   ` (2 preceding siblings ...)
  2019-08-16 19:09 ` ✗ Fi.CI.BAT: failure for " Patchwork
@ 2019-08-16 19:17 ` Chris Wilson
  2019-08-16 21:50   ` Daniele Ceraolo Spurio
  2019-08-16 19:55 ` ✗ Fi.CI.CHECKPATCH: warning for drm/i915/selftests: Check the context size (rev3) Patchwork
                   ` (2 subsequent siblings)
  6 siblings, 1 reply; 12+ messages in thread
From: Chris Wilson @ 2019-08-16 19:17 UTC (permalink / raw)
  To: intel-gfx

Add a redzone to our context image and check the HW does not write into
after a context save, to verify that we have the correct context size.
(This does vary with feature bits, so test with a live setup that should
match how we run userspace.)

v2: Check the redzone on every context unpin
v3: Use a kernel context to prevent loading garbage for ringbuffer
submission

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_lrc.c        |  33 ++++++
 drivers/gpu/drm/i915/gt/selftest_context.c | 128 +++++++++++++++++++++
 2 files changed, 161 insertions(+)

diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
index e9863f4d826b..ade212686bf6 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -1578,9 +1578,38 @@ static void execlists_context_destroy(struct kref *kref)
 	intel_context_fini(ce);
 	intel_context_free(ce);
 }
+static void
+set_redzone(void *vaddr, const struct intel_engine_cs *engine)
+{
+	if (!IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM))
+		return;
+
+	vaddr += LRC_HEADER_PAGES * PAGE_SIZE;
+	vaddr += engine->context_size;
+
+	memset(vaddr, POISON_INUSE, I915_GTT_PAGE_SIZE);
+}
+
+static void
+check_redzone(const void *vaddr, const struct intel_engine_cs *engine)
+{
+	if (!IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM))
+		return;
+
+	vaddr += LRC_HEADER_PAGES * PAGE_SIZE;
+	vaddr += engine->context_size;
+
+	if (memchr_inv(vaddr, POISON_INUSE, I915_GTT_PAGE_SIZE))
+		dev_err_once(engine->i915->drm.dev,
+			     "%s context redzone overwritten!\n",
+			     engine->name);
+}
 
 static void execlists_context_unpin(struct intel_context *ce)
 {
+	check_redzone((void *)ce->lrc_reg_state - LRC_STATE_PN * PAGE_SIZE,
+		      ce->engine);
+
 	i915_gem_context_unpin_hw_id(ce->gem_context);
 	i915_gem_object_unpin_map(ce->state->obj);
 	intel_ring_reset(ce->ring, ce->ring->tail);
@@ -3119,6 +3148,8 @@ populate_lr_context(struct intel_context *ce,
 		return ret;
 	}
 
+	set_redzone(vaddr, engine);
+
 	if (engine->default_state) {
 		/*
 		 * We only want to copy over the template context state;
@@ -3173,6 +3204,8 @@ static int __execlists_context_alloc(struct intel_context *ce,
 	 * for our own use and for sharing with the GuC.
 	 */
 	context_size += LRC_HEADER_PAGES * PAGE_SIZE;
+	if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM))
+		context_size += I915_GTT_PAGE_SIZE; /* for redzone */
 
 	ctx_obj = i915_gem_object_create_shmem(engine->i915, context_size);
 	if (IS_ERR(ctx_obj))
diff --git a/drivers/gpu/drm/i915/gt/selftest_context.c b/drivers/gpu/drm/i915/gt/selftest_context.c
index 6fbc72bc290e..cefd2df086fb 100644
--- a/drivers/gpu/drm/i915/gt/selftest_context.c
+++ b/drivers/gpu/drm/i915/gt/selftest_context.c
@@ -5,6 +5,7 @@
  */
 
 #include "i915_selftest.h"
+#include "intel_engine_pm.h"
 #include "intel_gt.h"
 
 #include "gem/selftests/mock_context.h"
@@ -64,6 +65,132 @@ static int context_sync(struct intel_context *ce)
 	return err;
 }
 
+static int __live_context_size(struct intel_engine_cs *engine,
+			       struct i915_gem_context *fixme)
+{
+	struct intel_context *ce;
+	struct i915_request *rq;
+	void *vaddr;
+	int err;
+
+	ce = intel_context_create(fixme, engine);
+	if (IS_ERR(ce))
+		return PTR_ERR(ce);
+
+	err = intel_context_pin(ce);
+	if (err)
+		goto err;
+
+	vaddr = i915_gem_object_pin_map(ce->state->obj,
+					i915_coherent_map_type(engine->i915));
+	if (IS_ERR(vaddr)) {
+		err = PTR_ERR(vaddr);
+		intel_context_unpin(ce);
+		goto err;
+	}
+
+	if (HAS_EXECLISTS(engine->i915))
+		vaddr += LRC_HEADER_PAGES * PAGE_SIZE;
+
+	vaddr += engine->context_size - I915_GTT_PAGE_SIZE;
+	memset(vaddr, POISON_INUSE, I915_GTT_PAGE_SIZE);
+
+	rq = intel_context_create_request(ce);
+	intel_context_unpin(ce);
+	if (IS_ERR(rq)) {
+		err = PTR_ERR(rq);
+		goto err_unpin;
+	}
+
+	err = request_sync(rq);
+	if (err)
+		goto err_unpin;
+
+	/* Force the context switch */
+	rq = i915_request_create(engine->kernel_context);
+	if (IS_ERR(rq)) {
+		err = PTR_ERR(rq);
+		goto err_unpin;
+	}
+	err = request_sync(rq);
+	if (err)
+		goto err_unpin;
+
+	if (memchr_inv(vaddr, POISON_INUSE, I915_GTT_PAGE_SIZE)) {
+		pr_err("%s context overwrote trailing red-zone!", engine->name);
+		err = -EINVAL;
+	}
+
+err_unpin:
+	i915_gem_object_unpin_map(ce->state->obj);
+err:
+	intel_context_put(ce);
+	return err;
+}
+
+static int live_context_size(void *arg)
+{
+	struct intel_gt *gt = arg;
+	struct intel_engine_cs *engine;
+	struct i915_gem_context *fixme;
+	enum intel_engine_id id;
+	int err = 0;
+
+	/*
+	 * Check that our context sizes are correct by seeing if the
+	 * HW tries to write past the end of one.
+	 */
+
+	mutex_lock(&gt->i915->drm.struct_mutex);
+
+	fixme = kernel_context(gt->i915);
+	if (IS_ERR(fixme)) {
+		err = PTR_ERR(fixme);
+		goto unlock;
+	}
+
+	for_each_engine(engine, gt->i915, id) {
+		struct {
+			struct drm_i915_gem_object *state;
+			void *pinned;
+		} saved;
+
+		if (!engine->context_size)
+			continue;
+
+		intel_engine_pm_get(engine);
+
+		/*
+		 * Hide the old default state -- we lie about the context size
+		 * and get confused when the default state is smaller than
+		 * expected. For our do nothing request, inheriting the
+		 * active state is sufficient, we are only checking that we
+		 * don't use more than we planned.
+		 */
+		saved.state = fetch_and_zero(&engine->default_state);
+		saved.pinned = fetch_and_zero(&engine->pinned_default_state);
+
+		engine->context_size += I915_GTT_PAGE_SIZE;
+
+		err = __live_context_size(engine, fixme);
+
+		engine->context_size -= I915_GTT_PAGE_SIZE;
+
+		engine->pinned_default_state = saved.pinned;
+		engine->default_state = saved.state;
+
+		intel_engine_pm_put(engine);
+
+		if (err)
+			break;
+	}
+
+	kernel_context_close(fixme);
+unlock:
+	mutex_unlock(&gt->i915->drm.struct_mutex);
+	return err;
+}
+
 static int __live_active_context(struct intel_engine_cs *engine,
 				 struct i915_gem_context *fixme)
 {
@@ -303,6 +430,7 @@ static int live_remote_context(void *arg)
 int intel_context_live_selftests(struct drm_i915_private *i915)
 {
 	static const struct i915_subtest tests[] = {
+		SUBTEST(live_context_size),
 		SUBTEST(live_active_context),
 		SUBTEST(live_remote_context),
 	};
-- 
2.23.0.rc1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 12+ messages in thread

* ✗ Fi.CI.CHECKPATCH: warning for drm/i915/selftests: Check the context size (rev3)
  2019-08-16 17:58 [PATCH] drm/i915/selftests: Check the context size Chris Wilson
                   ` (3 preceding siblings ...)
  2019-08-16 19:17 ` [PATCH v3] " Chris Wilson
@ 2019-08-16 19:55 ` Patchwork
  2019-08-16 20:16 ` ✓ Fi.CI.BAT: success " Patchwork
  2019-08-17 13:50 ` ✓ Fi.CI.IGT: " Patchwork
  6 siblings, 0 replies; 12+ messages in thread
From: Patchwork @ 2019-08-16 19:55 UTC (permalink / raw)
  To: Chris Wilson; +Cc: intel-gfx

== Series Details ==

Series: drm/i915/selftests: Check the context size (rev3)
URL   : https://patchwork.freedesktop.org/series/65323/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
592028b70fab drm/i915/selftests: Check the context size
-:26: CHECK:LINE_SPACING: Please use a blank line after function/struct/union/enum declarations
#26: FILE: drivers/gpu/drm/i915/gt/intel_lrc.c:1581:
 }
+static void

total: 0 errors, 0 warnings, 1 checks, 200 lines checked

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 12+ messages in thread

* ✓ Fi.CI.BAT: success for drm/i915/selftests: Check the context size (rev3)
  2019-08-16 17:58 [PATCH] drm/i915/selftests: Check the context size Chris Wilson
                   ` (4 preceding siblings ...)
  2019-08-16 19:55 ` ✗ Fi.CI.CHECKPATCH: warning for drm/i915/selftests: Check the context size (rev3) Patchwork
@ 2019-08-16 20:16 ` Patchwork
  2019-08-17 13:50 ` ✓ Fi.CI.IGT: " Patchwork
  6 siblings, 0 replies; 12+ messages in thread
From: Patchwork @ 2019-08-16 20:16 UTC (permalink / raw)
  To: Chris Wilson; +Cc: intel-gfx

== Series Details ==

Series: drm/i915/selftests: Check the context size (rev3)
URL   : https://patchwork.freedesktop.org/series/65323/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_6721 -> Patchwork_14062
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14062/

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_14062:

### IGT changes ###

#### Suppressed ####

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * {igt@i915_selftest@live_gt_timelines}:
    - fi-hsw-peppy:       [PASS][1] -> [INCOMPLETE][2]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6721/fi-hsw-peppy/igt@i915_selftest@live_gt_timelines.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14062/fi-hsw-peppy/igt@i915_selftest@live_gt_timelines.html

  
Known issues
------------

  Here are the changes found in Patchwork_14062 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_flink_basic@bad-open:
    - fi-icl-u3:          [PASS][3] -> [DMESG-WARN][4] ([fdo#107724])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6721/fi-icl-u3/igt@gem_flink_basic@bad-open.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14062/fi-icl-u3/igt@gem_flink_basic@bad-open.html

  
#### Possible fixes ####

  * igt@i915_selftest@live_execlists:
    - fi-skl-gvtdvm:      [DMESG-FAIL][5] ([fdo#111108]) -> [PASS][6]
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6721/fi-skl-gvtdvm/igt@i915_selftest@live_execlists.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14062/fi-skl-gvtdvm/igt@i915_selftest@live_execlists.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
  [fdo#111108]: https://bugs.freedesktop.org/show_bug.cgi?id=111108


Participating hosts (53 -> 46)
------------------------------

  Missing    (7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-icl-y fi-byt-clapper fi-bdw-samus 


Build changes
-------------

  * CI: CI-20190529 -> None
  * Linux: CI_DRM_6721 -> Patchwork_14062

  CI-20190529: 20190529
  CI_DRM_6721: cbf9004bdfce80aff94fbd68ca0feb7fd76af0c4 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5138: b9abe0bf6c478c4f6cac56bff286d6926ad8c0ab @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_14062: 592028b70fabc0065c9c23dc39dd9d4ef57334d8 @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

592028b70fab drm/i915/selftests: Check the context size

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14062/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 12+ messages in thread

* Re: [PATCH v3] drm/i915/selftests: Check the context size
  2019-08-16 19:17 ` [PATCH v3] " Chris Wilson
@ 2019-08-16 21:50   ` Daniele Ceraolo Spurio
  2019-08-16 22:13     ` Chris Wilson
  0 siblings, 1 reply; 12+ messages in thread
From: Daniele Ceraolo Spurio @ 2019-08-16 21:50 UTC (permalink / raw)
  To: Chris Wilson, intel-gfx



On 8/16/19 12:17 PM, Chris Wilson wrote:
> Add a redzone to our context image and check the HW does not write into
> after a context save, to verify that we have the correct context size.
> (This does vary with feature bits, so test with a live setup that should
> match how we run userspace.)
> 
> v2: Check the redzone on every context unpin
> v3: Use a kernel context to prevent loading garbage for ringbuffer
> submission
> 
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> ---
>   drivers/gpu/drm/i915/gt/intel_lrc.c        |  33 ++++++
>   drivers/gpu/drm/i915/gt/selftest_context.c | 128 +++++++++++++++++++++
>   2 files changed, 161 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
> index e9863f4d826b..ade212686bf6 100644
> --- a/drivers/gpu/drm/i915/gt/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
> @@ -1578,9 +1578,38 @@ static void execlists_context_destroy(struct kref *kref)
>   	intel_context_fini(ce);
>   	intel_context_free(ce);
>   }
> +static void
> +set_redzone(void *vaddr, const struct intel_engine_cs *engine)
> +{
> +	if (!IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM))
> +		return;
> +
> +	vaddr += LRC_HEADER_PAGES * PAGE_SIZE;
> +	vaddr += engine->context_size;
> +
> +	memset(vaddr, POISON_INUSE, I915_GTT_PAGE_SIZE);
> +}
> +
> +static void
> +check_redzone(const void *vaddr, const struct intel_engine_cs *engine)
> +{
> +	if (!IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM))
> +		return;
> +
> +	vaddr += LRC_HEADER_PAGES * PAGE_SIZE;
> +	vaddr += engine->context_size;
> +
> +	if (memchr_inv(vaddr, POISON_INUSE, I915_GTT_PAGE_SIZE))
> +		dev_err_once(engine->i915->drm.dev,
> +			     "%s context redzone overwritten!\n",
> +			     engine->name);
> +}
>   
>   static void execlists_context_unpin(struct intel_context *ce)
>   {
> +	check_redzone((void *)ce->lrc_reg_state - LRC_STATE_PN * PAGE_SIZE,
> +		      ce->engine);
> +
>   	i915_gem_context_unpin_hw_id(ce->gem_context);
>   	i915_gem_object_unpin_map(ce->state->obj);
>   	intel_ring_reset(ce->ring, ce->ring->tail);
> @@ -3119,6 +3148,8 @@ populate_lr_context(struct intel_context *ce,
>   		return ret;
>   	}
>   
> +	set_redzone(vaddr, engine);
> +
>   	if (engine->default_state) {
>   		/*
>   		 * We only want to copy over the template context state;
> @@ -3173,6 +3204,8 @@ static int __execlists_context_alloc(struct intel_context *ce,
>   	 * for our own use and for sharing with the GuC.
>   	 */
>   	context_size += LRC_HEADER_PAGES * PAGE_SIZE;
> +	if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM))
> +		context_size += I915_GTT_PAGE_SIZE; /* for redzone */
>   
>   	ctx_obj = i915_gem_object_create_shmem(engine->i915, context_size);
>   	if (IS_ERR(ctx_obj))
> diff --git a/drivers/gpu/drm/i915/gt/selftest_context.c b/drivers/gpu/drm/i915/gt/selftest_context.c
> index 6fbc72bc290e..cefd2df086fb 100644
> --- a/drivers/gpu/drm/i915/gt/selftest_context.c
> +++ b/drivers/gpu/drm/i915/gt/selftest_context.c
> @@ -5,6 +5,7 @@
>    */
>   
>   #include "i915_selftest.h"
> +#include "intel_engine_pm.h"
>   #include "intel_gt.h"
>   
>   #include "gem/selftests/mock_context.h"
> @@ -64,6 +65,132 @@ static int context_sync(struct intel_context *ce)
>   	return err;
>   }
>   
> +static int __live_context_size(struct intel_engine_cs *engine,
> +			       struct i915_gem_context *fixme)
> +{
> +	struct intel_context *ce;
> +	struct i915_request *rq;
> +	void *vaddr;
> +	int err;
> +
> +	ce = intel_context_create(fixme, engine);
> +	if (IS_ERR(ce))
> +		return PTR_ERR(ce);
> +
> +	err = intel_context_pin(ce);
> +	if (err)
> +		goto err;
> +
> +	vaddr = i915_gem_object_pin_map(ce->state->obj,
> +					i915_coherent_map_type(engine->i915));
> +	if (IS_ERR(vaddr)) {
> +		err = PTR_ERR(vaddr);
> +		intel_context_unpin(ce);
> +		goto err;
> +	}
> +
> +	if (HAS_EXECLISTS(engine->i915))
> +		vaddr += LRC_HEADER_PAGES * PAGE_SIZE;
> +
> +	vaddr += engine->context_size - I915_GTT_PAGE_SIZE;
> +	memset(vaddr, POISON_INUSE, I915_GTT_PAGE_SIZE);
> +
> +	rq = intel_context_create_request(ce);
> +	intel_context_unpin(ce);
> +	if (IS_ERR(rq)) {
> +		err = PTR_ERR(rq);
> +		goto err_unpin;
> +	}
> +
> +	err = request_sync(rq);
> +	if (err)
> +		goto err_unpin;
> +
> +	/* Force the context switch */
> +	rq = i915_request_create(engine->kernel_context);
> +	if (IS_ERR(rq)) {
> +		err = PTR_ERR(rq);
> +		goto err_unpin;
> +	}
> +	err = request_sync(rq);
> +	if (err)
> +		goto err_unpin;
> +
> +	if (memchr_inv(vaddr, POISON_INUSE, I915_GTT_PAGE_SIZE)) {
> +		pr_err("%s context overwrote trailing red-zone!", engine->name);
> +		err = -EINVAL;
> +	}
> +
> +err_unpin:
> +	i915_gem_object_unpin_map(ce->state->obj);
> +err:
> +	intel_context_put(ce);
> +	return err;
> +}
> +
> +static int live_context_size(void *arg)
> +{
> +	struct intel_gt *gt = arg;
> +	struct intel_engine_cs *engine;
> +	struct i915_gem_context *fixme;
> +	enum intel_engine_id id;
> +	int err = 0;
> +
> +	/*
> +	 * Check that our context sizes are correct by seeing if the
> +	 * HW tries to write past the end of one.
> +	 */
> +
> +	mutex_lock(&gt->i915->drm.struct_mutex);
> +
> +	fixme = kernel_context(gt->i915);
> +	if (IS_ERR(fixme)) {
> +		err = PTR_ERR(fixme);
> +		goto unlock;
> +	}
> +
> +	for_each_engine(engine, gt->i915, id) {
> +		struct {
> +			struct drm_i915_gem_object *state;
> +			void *pinned;
> +		} saved;
> +
> +		if (!engine->context_size)
> +			continue;
> +
> +		intel_engine_pm_get(engine);
> +
> +		/*
> +		 * Hide the old default state -- we lie about the context size
> +		 * and get confused when the default state is smaller than
> +		 * expected. For our do nothing request, inheriting the
> +		 * active state is sufficient, we are only checking that we
> +		 * don't use more than we planned.
> +		 */
> +		saved.state = fetch_and_zero(&engine->default_state);
> +		saved.pinned = fetch_and_zero(&engine->pinned_default_state);
> +
> +		engine->context_size += I915_GTT_PAGE_SIZE;

if CONFIG_DRM_I915_DEBUG_GEM is set we already bump the size inside the 
context_alloc(), do we need to bump it again here?

Daniele

> +
> +		err = __live_context_size(engine, fixme);
> +
> +		engine->context_size -= I915_GTT_PAGE_SIZE;
> +
> +		engine->pinned_default_state = saved.pinned;
> +		engine->default_state = saved.state;
> +
> +		intel_engine_pm_put(engine);
> +
> +		if (err)
> +			break;
> +	}
> +
> +	kernel_context_close(fixme);
> +unlock:
> +	mutex_unlock(&gt->i915->drm.struct_mutex);
> +	return err;
> +}
> +
>   static int __live_active_context(struct intel_engine_cs *engine,
>   				 struct i915_gem_context *fixme)
>   {
> @@ -303,6 +430,7 @@ static int live_remote_context(void *arg)
>   int intel_context_live_selftests(struct drm_i915_private *i915)
>   {
>   	static const struct i915_subtest tests[] = {
> +		SUBTEST(live_context_size),
>   		SUBTEST(live_active_context),
>   		SUBTEST(live_remote_context),
>   	};
> 
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 12+ messages in thread

* Re: [PATCH v3] drm/i915/selftests: Check the context size
  2019-08-16 21:50   ` Daniele Ceraolo Spurio
@ 2019-08-16 22:13     ` Chris Wilson
  2019-08-16 22:24       ` Daniele Ceraolo Spurio
  0 siblings, 1 reply; 12+ messages in thread
From: Chris Wilson @ 2019-08-16 22:13 UTC (permalink / raw)
  To: Daniele Ceraolo Spurio, intel-gfx

Quoting Daniele Ceraolo Spurio (2019-08-16 22:50:43)
> 
> 
> On 8/16/19 12:17 PM, Chris Wilson wrote:
> > +static int live_context_size(void *arg)
> > +{
> > +             /*
> > +              * Hide the old default state -- we lie about the context size
> > +              * and get confused when the default state is smaller than
> > +              * expected. For our do nothing request, inheriting the
> > +              * active state is sufficient, we are only checking that we
> > +              * don't use more than we planned.
> > +              */
> > +             saved.state = fetch_and_zero(&engine->default_state);
> > +             saved.pinned = fetch_and_zero(&engine->pinned_default_state);
> > +
> > +             engine->context_size += I915_GTT_PAGE_SIZE;
> 
> if CONFIG_DRM_I915_DEBUG_GEM is set we already bump the size inside the 
> context_alloc(), do we need to bump it again here?

No, it comes out in the wash as we apply the same redzone twice. At least,
adding and checking a second page after what we believe to be the end of
the context image does not help sensitivity (so makes a worse test imo).

The benefit of this selftest is that we check all submission modes, and
can set up any execution pattern we think might be required (within
reason). So, I think it still has a use even if we need to remind
ourselves of the overlap.
-Chris
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 12+ messages in thread

* Re: [PATCH v3] drm/i915/selftests: Check the context size
  2019-08-16 22:13     ` Chris Wilson
@ 2019-08-16 22:24       ` Daniele Ceraolo Spurio
  0 siblings, 0 replies; 12+ messages in thread
From: Daniele Ceraolo Spurio @ 2019-08-16 22:24 UTC (permalink / raw)
  To: Chris Wilson, intel-gfx



On 8/16/19 3:13 PM, Chris Wilson wrote:
> Quoting Daniele Ceraolo Spurio (2019-08-16 22:50:43)
>>
>>
>> On 8/16/19 12:17 PM, Chris Wilson wrote:
>>> +static int live_context_size(void *arg)
>>> +{
>>> +             /*
>>> +              * Hide the old default state -- we lie about the context size
>>> +              * and get confused when the default state is smaller than
>>> +              * expected. For our do nothing request, inheriting the
>>> +              * active state is sufficient, we are only checking that we
>>> +              * don't use more than we planned.
>>> +              */
>>> +             saved.state = fetch_and_zero(&engine->default_state);
>>> +             saved.pinned = fetch_and_zero(&engine->pinned_default_state);
>>> +
>>> +             engine->context_size += I915_GTT_PAGE_SIZE;
>>
>> if CONFIG_DRM_I915_DEBUG_GEM is set we already bump the size inside the
>> context_alloc(), do we need to bump it again here?
> 
> No, it comes out in the wash as we apply the same redzone twice. At least,
> adding and checking a second page after what we believe to be the end of
> the context image does not help sensitivity (so makes a worse test imo).
> 
> The benefit of this selftest is that we check all submission modes, and
> can set up any execution pattern we think might be required (within
> reason). So, I think it still has a use even if we need to remind
> ourselves of the overlap.
> -Chris
> 

Fair enough. With the above written down as a comment in the code:

Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>

Daniele
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 12+ messages in thread

* ✓ Fi.CI.IGT: success for drm/i915/selftests: Check the context size (rev3)
  2019-08-16 17:58 [PATCH] drm/i915/selftests: Check the context size Chris Wilson
                   ` (5 preceding siblings ...)
  2019-08-16 20:16 ` ✓ Fi.CI.BAT: success " Patchwork
@ 2019-08-17 13:50 ` Patchwork
  6 siblings, 0 replies; 12+ messages in thread
From: Patchwork @ 2019-08-17 13:50 UTC (permalink / raw)
  To: Chris Wilson; +Cc: intel-gfx

== Series Details ==

Series: drm/i915/selftests: Check the context size (rev3)
URL   : https://patchwork.freedesktop.org/series/65323/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_6721_full -> Patchwork_14062_full
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Known issues
------------

  Here are the changes found in Patchwork_14062_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_ctx_isolation@bcs0-s3:
    - shard-skl:          [PASS][1] -> [INCOMPLETE][2] ([fdo#104108]) +2 similar issues
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6721/shard-skl5/igt@gem_ctx_isolation@bcs0-s3.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14062/shard-skl5/igt@gem_ctx_isolation@bcs0-s3.html

  * igt@gem_ctx_switch@legacy-bsd1:
    - shard-iclb:         [PASS][3] -> [INCOMPLETE][4] ([fdo#107713])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6721/shard-iclb8/igt@gem_ctx_switch@legacy-bsd1.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14062/shard-iclb1/igt@gem_ctx_switch@legacy-bsd1.html

  * igt@gem_exec_schedule@out-order-bsd2:
    - shard-iclb:         [PASS][5] -> [SKIP][6] ([fdo#109276]) +19 similar issues
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6721/shard-iclb4/igt@gem_exec_schedule@out-order-bsd2.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14062/shard-iclb6/igt@gem_exec_schedule@out-order-bsd2.html

  * igt@gem_exec_schedule@preemptive-hang-bsd:
    - shard-iclb:         [PASS][7] -> [SKIP][8] ([fdo#111325]) +4 similar issues
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6721/shard-iclb3/igt@gem_exec_schedule@preemptive-hang-bsd.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14062/shard-iclb2/igt@gem_exec_schedule@preemptive-hang-bsd.html

  * igt@gem_pwrite@small-gtt-fbr:
    - shard-apl:          [PASS][9] -> [INCOMPLETE][10] ([fdo#103927]) +3 similar issues
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6721/shard-apl8/igt@gem_pwrite@small-gtt-fbr.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14062/shard-apl6/igt@gem_pwrite@small-gtt-fbr.html

  * igt@kms_cursor_legacy@cursor-vs-flip-atomic:
    - shard-hsw:          [PASS][11] -> [FAIL][12] ([fdo#103355])
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6721/shard-hsw1/igt@kms_cursor_legacy@cursor-vs-flip-atomic.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14062/shard-hsw1/igt@kms_cursor_legacy@cursor-vs-flip-atomic.html

  * igt@kms_flip@plain-flip-fb-recreate-interruptible:
    - shard-skl:          [PASS][13] -> [FAIL][14] ([fdo#100368])
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6721/shard-skl3/igt@kms_flip@plain-flip-fb-recreate-interruptible.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14062/shard-skl2/igt@kms_flip@plain-flip-fb-recreate-interruptible.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-pwrite:
    - shard-iclb:         [PASS][15] -> [FAIL][16] ([fdo#103167]) +2 similar issues
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6721/shard-iclb2/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-pwrite.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14062/shard-iclb2/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-pwrite.html

  * igt@kms_pipe_crc_basic@read-crc-pipe-b-frame-sequence:
    - shard-skl:          [PASS][17] -> [FAIL][18] ([fdo#103191])
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6721/shard-skl2/igt@kms_pipe_crc_basic@read-crc-pipe-b-frame-sequence.html
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14062/shard-skl9/igt@kms_pipe_crc_basic@read-crc-pipe-b-frame-sequence.html

  * igt@kms_plane_alpha_blend@pipe-b-coverage-7efc:
    - shard-skl:          [PASS][19] -> [FAIL][20] ([fdo#108145] / [fdo#110403])
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6721/shard-skl2/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14062/shard-skl9/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html

  * igt@kms_psr@psr2_cursor_mmap_cpu:
    - shard-iclb:         [PASS][21] -> [SKIP][22] ([fdo#109441]) +3 similar issues
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6721/shard-iclb2/igt@kms_psr@psr2_cursor_mmap_cpu.html
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14062/shard-iclb1/igt@kms_psr@psr2_cursor_mmap_cpu.html

  * igt@kms_vblank@pipe-a-ts-continuation-suspend:
    - shard-apl:          [PASS][23] -> [DMESG-WARN][24] ([fdo#108566]) +1 similar issue
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6721/shard-apl1/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14062/shard-apl7/igt@kms_vblank@pipe-a-ts-continuation-suspend.html

  * igt@perf@polling:
    - shard-skl:          [PASS][25] -> [FAIL][26] ([fdo#110728])
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6721/shard-skl4/igt@perf@polling.html
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14062/shard-skl9/igt@perf@polling.html

  
#### Possible fixes ####

  * igt@gem_ctx_shared@exec-single-timeline-bsd:
    - shard-iclb:         [SKIP][27] ([fdo#110841]) -> [PASS][28]
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6721/shard-iclb1/igt@gem_ctx_shared@exec-single-timeline-bsd.html
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14062/shard-iclb6/igt@gem_ctx_shared@exec-single-timeline-bsd.html

  * igt@gem_exec_balancer@smoke:
    - shard-iclb:         [SKIP][29] ([fdo#110854]) -> [PASS][30]
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6721/shard-iclb6/igt@gem_exec_balancer@smoke.html
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14062/shard-iclb4/igt@gem_exec_balancer@smoke.html

  * igt@gem_exec_schedule@in-order-bsd:
    - shard-iclb:         [SKIP][31] ([fdo#111325]) -> [PASS][32] +5 similar issues
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6721/shard-iclb1/igt@gem_exec_schedule@in-order-bsd.html
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14062/shard-iclb3/igt@gem_exec_schedule@in-order-bsd.html

  * igt@gem_exec_schedule@preempt-contexts-bsd2:
    - shard-iclb:         [SKIP][33] ([fdo#109276]) -> [PASS][34] +23 similar issues
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6721/shard-iclb7/igt@gem_exec_schedule@preempt-contexts-bsd2.html
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14062/shard-iclb1/igt@gem_exec_schedule@preempt-contexts-bsd2.html

  * igt@i915_pm_rpm@system-suspend:
    - shard-skl:          [INCOMPLETE][35] ([fdo#104108] / [fdo#107807]) -> [PASS][36]
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6721/shard-skl4/igt@i915_pm_rpm@system-suspend.html
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14062/shard-skl3/igt@i915_pm_rpm@system-suspend.html

  * igt@kms_big_fb@x-tiled-8bpp-rotate-0:
    - shard-iclb:         [INCOMPLETE][37] ([fdo#107713]) -> [PASS][38]
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6721/shard-iclb7/igt@kms_big_fb@x-tiled-8bpp-rotate-0.html
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14062/shard-iclb7/igt@kms_big_fb@x-tiled-8bpp-rotate-0.html

  * igt@kms_cursor_legacy@2x-long-cursor-vs-flip-legacy:
    - shard-hsw:          [FAIL][39] ([fdo#105767]) -> [PASS][40]
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6721/shard-hsw4/igt@kms_cursor_legacy@2x-long-cursor-vs-flip-legacy.html
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14062/shard-hsw2/igt@kms_cursor_legacy@2x-long-cursor-vs-flip-legacy.html

  * igt@kms_flip@flip-vs-absolute-wf_vblank-interruptible:
    - shard-skl:          [FAIL][41] ([fdo#100368]) -> [PASS][42]
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6721/shard-skl1/igt@kms_flip@flip-vs-absolute-wf_vblank-interruptible.html
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14062/shard-skl1/igt@kms_flip@flip-vs-absolute-wf_vblank-interruptible.html

  * igt@kms_flip@flip-vs-suspend-interruptible:
    - shard-skl:          [INCOMPLETE][43] ([fdo#109507]) -> [PASS][44]
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6721/shard-skl6/igt@kms_flip@flip-vs-suspend-interruptible.html
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14062/shard-skl8/igt@kms_flip@flip-vs-suspend-interruptible.html

  * igt@kms_flip@modeset-vs-vblank-race:
    - shard-glk:          [FAIL][45] ([fdo#103060]) -> [PASS][46]
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6721/shard-glk8/igt@kms_flip@modeset-vs-vblank-race.html
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14062/shard-glk7/igt@kms_flip@modeset-vs-vblank-race.html

  * igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-blt:
    - shard-iclb:         [FAIL][47] ([fdo#103167]) -> [PASS][48] +2 similar issues
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6721/shard-iclb2/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-blt.html
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14062/shard-iclb2/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@fbc-suspend:
    - shard-apl:          [DMESG-WARN][49] ([fdo#108566]) -> [PASS][50] +3 similar issues
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6721/shard-apl5/igt@kms_frontbuffer_tracking@fbc-suspend.html
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14062/shard-apl2/igt@kms_frontbuffer_tracking@fbc-suspend.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-rte:
    - shard-iclb:         [FAIL][51] ([fdo#103167] / [fdo#110378]) -> [PASS][52]
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6721/shard-iclb2/igt@kms_frontbuffer_tracking@fbcpsr-1p-rte.html
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14062/shard-iclb2/igt@kms_frontbuffer_tracking@fbcpsr-1p-rte.html

  * igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-indfb-draw-pwrite:
    - shard-skl:          [FAIL][53] ([fdo#103167]) -> [PASS][54]
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6721/shard-skl7/igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-indfb-draw-pwrite.html
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14062/shard-skl8/igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-indfb-draw-pwrite.html

  * igt@kms_psr@psr2_cursor_render:
    - shard-iclb:         [SKIP][55] ([fdo#109441]) -> [PASS][56]
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6721/shard-iclb7/igt@kms_psr@psr2_cursor_render.html
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14062/shard-iclb2/igt@kms_psr@psr2_cursor_render.html

  * igt@kms_setmode@basic:
    - shard-apl:          [FAIL][57] ([fdo#99912]) -> [PASS][58]
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6721/shard-apl3/igt@kms_setmode@basic.html
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14062/shard-apl6/igt@kms_setmode@basic.html

  * igt@kms_vblank@pipe-c-ts-continuation-suspend:
    - shard-kbl:          [INCOMPLETE][59] ([fdo#103665]) -> [PASS][60]
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6721/shard-kbl4/igt@kms_vblank@pipe-c-ts-continuation-suspend.html
   [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14062/shard-kbl6/igt@kms_vblank@pipe-c-ts-continuation-suspend.html

  
#### Warnings ####

  * igt@gem_ctx_isolation@vcs1-nonpriv:
    - shard-iclb:         [FAIL][61] ([fdo#111329]) -> [SKIP][62] ([fdo#109276])
   [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6721/shard-iclb4/igt@gem_ctx_isolation@vcs1-nonpriv.html
   [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14062/shard-iclb6/igt@gem_ctx_isolation@vcs1-nonpriv.html

  * igt@gem_mocs_settings@mocs-settings-bsd2:
    - shard-iclb:         [SKIP][63] ([fdo#109276]) -> [FAIL][64] ([fdo#111330])
   [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6721/shard-iclb7/igt@gem_mocs_settings@mocs-settings-bsd2.html
   [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14062/shard-iclb1/igt@gem_mocs_settings@mocs-settings-bsd2.html

  
  [fdo#100368]: https://bugs.freedesktop.org/show_bug.cgi?id=100368
  [fdo#103060]: https://bugs.freedesktop.org/show_bug.cgi?id=103060
  [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
  [fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191
  [fdo#103355]: https://bugs.freedesktop.org/show_bug.cgi?id=103355
  [fdo#103665]: https://bugs.freedesktop.org/show_bug.cgi?id=103665
  [fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
  [fdo#104108]: https://bugs.freedesktop.org/show_bug.cgi?id=104108
  [fdo#105767]: https://bugs.freedesktop.org/show_bug.cgi?id=105767
  [fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
  [fdo#107807]: https://bugs.freedesktop.org/show_bug.cgi?id=107807
  [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
  [fdo#108566]: https://bugs.freedesktop.org/show_bug.cgi?id=108566
  [fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276
  [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
  [fdo#109507]: https://bugs.freedesktop.org/show_bug.cgi?id=109507
  [fdo#110378]: https://bugs.freedesktop.org/show_bug.cgi?id=110378
  [fdo#110403]: https://bugs.freedesktop.org/show_bug.cgi?id=110403
  [fdo#110728]: https://bugs.freedesktop.org/show_bug.cgi?id=110728
  [fdo#110841]: https://bugs.freedesktop.org/show_bug.cgi?id=110841
  [fdo#110854]: https://bugs.freedesktop.org/show_bug.cgi?id=110854
  [fdo#111325]: https://bugs.freedesktop.org/show_bug.cgi?id=111325
  [fdo#111329]: https://bugs.freedesktop.org/show_bug.cgi?id=111329
  [fdo#111330]: https://bugs.freedesktop.org/show_bug.cgi?id=111330
  [fdo#99912]: https://bugs.freedesktop.org/show_bug.cgi?id=99912


Participating hosts (10 -> 10)
------------------------------

  No changes in participating hosts


Build changes
-------------

  * CI: CI-20190529 -> None
  * Linux: CI_DRM_6721 -> Patchwork_14062

  CI-20190529: 20190529
  CI_DRM_6721: cbf9004bdfce80aff94fbd68ca0feb7fd76af0c4 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5138: b9abe0bf6c478c4f6cac56bff286d6926ad8c0ab @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_14062: 592028b70fabc0065c9c23dc39dd9d4ef57334d8 @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14062/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 12+ messages in thread

end of thread, other threads:[~2019-08-17 13:50 UTC | newest]

Thread overview: 12+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-08-16 17:58 [PATCH] drm/i915/selftests: Check the context size Chris Wilson
2019-08-16 18:43 ` Daniele Ceraolo Spurio
2019-08-16 18:50   ` Chris Wilson
2019-08-16 19:09 ` [PATCH v2] " Chris Wilson
2019-08-16 19:09 ` ✗ Fi.CI.BAT: failure for " Patchwork
2019-08-16 19:17 ` [PATCH v3] " Chris Wilson
2019-08-16 21:50   ` Daniele Ceraolo Spurio
2019-08-16 22:13     ` Chris Wilson
2019-08-16 22:24       ` Daniele Ceraolo Spurio
2019-08-16 19:55 ` ✗ Fi.CI.CHECKPATCH: warning for drm/i915/selftests: Check the context size (rev3) Patchwork
2019-08-16 20:16 ` ✓ Fi.CI.BAT: success " Patchwork
2019-08-17 13:50 ` ✓ Fi.CI.IGT: " Patchwork

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