From: Lucas De Marchi <lucas.demarchi@intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [PATCH v2 01/40] drm/i915/tgl: disable DDIC
Date: Sat, 17 Aug 2019 02:38:23 -0700 [thread overview]
Message-ID: <20190817093902.2171-2-lucas.demarchi@intel.com> (raw)
In-Reply-To: <20190817093902.2171-1-lucas.demarchi@intel.com>
The current SKUs added for Tiger Lake don't have DDIC hooked up, even
though it is supported by the SoC. The current state for these SKUs is
problematic since while enabling the combo phy, PORT_COMP_DW* return
0xFFFFFFFF, which is invalid per register definition.
During initialization we check what phys are not yet enabled by reading
PHY_MISC_C and try to enable it by toggling the "DE to IO Comp Pwr Down"
bit. But after that any read to the PORT_COMP_DW* returns invalid
results. This removes the following warning
[56997.634353] Missing case (val == 4294967295)
[56997.639241] WARNING: CPU: 5 PID: 768 at drivers/gpu/drm/i915/display/intel_combo_phy.c:54 cnl_get_procmon_ref_values+0xc9/0xf0 [i915]
[56997.639808] Modules linked in: i915(+) prime_numbers x86_pkg_temp_thermal coretemp kvm_intel kvm irqbypass crct10dif_pclmul crc32_pclmul ghash_clmulni_intel e1000e [last unloaded: prime_numbers]
[56997.639808] CPU: 5 PID: 768 Comm: insmod Tainted: G U W 5.2.0-demarchi+ #65
[56997.639808] Hardware name: Intel Corporation Tiger Lake Client Platform/TigerLake U DDR4 SODIMM RVP, BIOS TGLSFWI1.R00.2252.A03.1906270154 06/27/2019
[56997.639808] RIP: 0010:cnl_get_procmon_ref_values+0xc9/0xf0 [i915]
[56997.639808] Code: 2c a0 85 c9 74 e0 81 f9 00 00 00 01 75 09 48 c7 c0 0c a4 2c a0 eb cf 48 c7 c6 3c 3a 31 a0 48 c7 c7 40 3a 31 a0 e8 6b 4d ea e0 <0f> 0b 48 c7 c0 00 a4 2c a0 eb b1 48 c7 c0 24 a4 2
c a0 eb a8 e8 be
[56997.639808] RSP: 0018:ffffc9000068f8a8 EFLAGS: 00010286
[56997.639808] RAX: 0000000000000000 RBX: ffff88848fa90000 RCX: 0000000000000000
[56997.639808] RDX: ffff8884a08b5ef8 RSI: ffff8884a08a6658 RDI: 00000000ffffffff
[56997.639808] RBP: 0000000000000002 R08: 0000000000000000 R09: 0000000000000000
[56997.639808] R10: 0000000000000000 R11: 0000000000000000 R12: ffff88848fa90000
[56997.639808] R13: 0000000000000000 R14: 0000000000000002 R15: 0006c00000162000
[56997.639808] FS: 00007f61ca3d12c0(0000) GS:ffff8884a0880000(0000) knlGS:0000000000000000
[56997.639808] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033
[56997.639808] CR2: 00007f71be6a92c0 CR3: 0000000494750006 CR4: 0000000000760ee0
[56997.639808] PKRU: 55555554
[56997.639808] Call Trace:
[56997.639808] cnl_verify_procmon_ref_values+0x36/0xf0 [i915]
[56997.639808] ? rcu_read_lock_sched_held+0x6f/0x80
[56997.639808] ? gen11_fwtable_read32+0x257/0x290 [i915]
[56997.639808] icl_combo_phy_verify_state.part.0+0x22/0xa0 [i915]
[56997.639808] intel_combo_phy_init+0x17e/0x3e0 [i915]
[56997.639808] ? icl_display_core_init+0x2c/0x1a0 [i915]
[56997.639808] ? _raw_spin_unlock_irqrestore+0x4c/0x60
[56997.639808] icl_display_core_init+0x34/0x1a0 [i915]
[56997.639808] intel_power_domains_init_hw+0x200/0x570 [i915]
[56997.639808] i915_driver_probe+0x103b/0x17e0 [i915]
[56997.639808] ? printk+0x53/0x6a
[56997.639808] i915_pci_probe+0x3b/0x190 [i915]
We may or may not need to change the implementation to account for DDIC
being available on other SKUs. For now I think the best thing to do is
to just disable the port.
v2: Fix checkpatch warning on commit message
Cc: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index ee54d9659c99..b51d1ceb8739 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -6667,7 +6667,7 @@ bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy phy)
if (phy == PHY_NONE)
return false;
- if (IS_ELKHARTLAKE(dev_priv) || INTEL_GEN(dev_priv) >= 12)
+ if (IS_ELKHARTLAKE(dev_priv))
return phy <= PHY_C;
if (INTEL_GEN(dev_priv) >= 11)
@@ -15299,7 +15299,6 @@ static void intel_setup_outputs(struct drm_i915_private *dev_priv)
/* TODO: initialize TC ports as well */
intel_ddi_init(dev_priv, PORT_A);
intel_ddi_init(dev_priv, PORT_B);
- intel_ddi_init(dev_priv, PORT_C);
icl_dsi_init(dev_priv);
} else if (IS_ELKHARTLAKE(dev_priv)) {
intel_ddi_init(dev_priv, PORT_A);
--
2.21.0
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next prev parent reply other threads:[~2019-08-17 9:39 UTC|newest]
Thread overview: 90+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-08-17 9:38 [PATCH v2 00/40] Tiger Lake batch 3 Lucas De Marchi
2019-08-17 9:38 ` Lucas De Marchi [this message]
2019-08-19 17:16 ` [PATCH v2 01/40] drm/i915/tgl: disable DDIC Matt Roper
2019-08-17 9:38 ` [PATCH v2 02/40] drm/i915/tgl: add support for reading the timestamp frequency Lucas De Marchi
2019-08-17 9:38 ` [PATCH v2 03/40] drm/i915/tgl: Move transcoders to pipes' powerwells Lucas De Marchi
2019-08-19 11:59 ` Imre Deak
2019-08-17 9:38 ` [PATCH v2 04/40] drm/i915/tgl: update DMC firmware to 2.04 Lucas De Marchi
2019-08-19 17:55 ` Srivatsa, Anusha
2019-08-19 18:03 ` Lucas De Marchi
2019-08-19 18:07 ` Srivatsa, Anusha
2019-08-17 9:38 ` [PATCH v2 05/40] drm/i915/psr: Make PSR registers relative to transcoders Lucas De Marchi
2019-08-20 20:16 ` Lucas De Marchi
2019-08-20 21:15 ` Souza, Jose
2019-08-17 9:38 ` [PATCH v2 06/40] drm/i915: Add transcoder restriction to PSR2 Lucas De Marchi
2019-08-20 20:19 ` Lucas De Marchi
2019-08-21 14:50 ` Ville Syrjälä
2019-08-17 9:38 ` [PATCH v2 07/40] drm/i915: Do not unmask PSR interruption in IRQ postinstall Lucas De Marchi
2019-08-20 20:29 ` Lucas De Marchi
2019-08-20 22:20 ` Souza, Jose
2019-08-17 9:38 ` [PATCH v2 08/40] drm/i915/psr: Only handle interruptions of the transcoder in use Lucas De Marchi
2019-08-17 9:38 ` [PATCH v2 09/40] drm/i915/bdw+: Enable PSR in any eDP port Lucas De Marchi
2019-08-17 9:38 ` [PATCH v2 10/40] drm/i915: Guard and warn if more than one eDP panel is present Lucas De Marchi
2019-08-17 9:38 ` [PATCH v2 11/40] drm/i915: Do not read PSR2 register in transcoders without PSR2 Lucas De Marchi
2019-08-17 9:38 ` [PATCH v2 12/40] drm/i915/tgl: PSR link standby is not supported anymore Lucas De Marchi
2019-08-17 9:38 ` [PATCH v2 13/40] drm/i915/tgl: Access the right register when handling PSR interruptions Lucas De Marchi
2019-08-17 9:38 ` [PATCH v2 14/40] drm/i915/tgl: Add maximum resolution supported by PSR2 HW Lucas De Marchi
2019-08-17 9:38 ` [PATCH v2 15/40] drm/i915: Fix DP-MST crtc_mask Lucas De Marchi
2019-08-17 9:38 ` [PATCH v2 16/40] drm/i915: Add for_each_new_intel_connector_in_state() Lucas De Marchi
2019-08-21 13:13 ` Kahola, Mika
2019-08-17 9:38 ` [PATCH v2 17/40] drm: Add for_each_oldnew_intel_crtc_in_state_reverse() Lucas De Marchi
2019-08-21 11:22 ` Kahola, Mika
2019-08-21 13:32 ` Kahola, Mika
2019-08-17 9:38 ` [PATCH v2 18/40] drm/i915: Disable pipes in reverse order Lucas De Marchi
2019-08-21 11:29 ` Kahola, Mika
2019-08-17 9:38 ` [PATCH v2 19/40] drm/i915/tgl: Select master transcoder in DP MST Lucas De Marchi
2019-08-22 12:43 ` Jani Nikula
2019-08-22 16:44 ` Maarten Lankhorst
2019-08-17 9:38 ` [PATCH v2 20/40] drm/i915/tgl: Introduce initial Tiger Lake workarounds Lucas De Marchi
2019-08-17 9:38 ` [PATCH v2 21/40] drm/i915/tgl: Enable VD HCP/MFX sub-pipe power gating Lucas De Marchi
2019-08-20 20:54 ` Lucas De Marchi
2019-08-21 9:16 ` Ye, Tony
2019-08-17 9:38 ` [PATCH v2 22/40] drm/i915/tgl: Do not apply WaIncreaseDefaultTLBEntries from GEN12 onwards Lucas De Marchi
2019-08-20 23:29 ` Summers, Stuart
2019-08-22 0:25 ` Summers, Stuart
2019-08-17 9:38 ` [PATCH v2 23/40] drm/i915/tgl: Register state context definition for Gen12 Lucas De Marchi
2019-08-21 21:12 ` Daniele Ceraolo Spurio
2019-08-22 13:31 ` Mika Kuoppala
2019-08-22 14:51 ` Chris Wilson
2019-08-17 9:38 ` [PATCH v2 24/40] drm/i915/tgl: move DP_TP_* to transcoder Lucas De Marchi
2019-08-17 9:38 ` [PATCH v2 25/40] drm/i915/tgl: Implement TGL DisplayPort training sequence Lucas De Marchi
2019-08-20 22:01 ` [PATCH v2] " José Roberto de Souza
2019-08-20 23:07 ` Manasi Navare
2019-08-21 20:22 ` Souza, Jose
[not found] ` <20190821213233.1067-1-jose.souza@intel.com>
2019-08-22 11:00 ` [PATCH v3] " Maarten Lankhorst
2019-08-17 9:38 ` [PATCH v2 26/40] HACK: drm/i915/tgl: Gen12 render context size Lucas De Marchi
2019-08-20 10:36 ` Chris Wilson
2019-08-22 13:42 ` Mika Kuoppala
2019-08-22 13:48 ` Chris Wilson
2019-08-17 9:38 ` [PATCH v2 27/40] drm/i915/tgl: add Gen12 default indirect ctx offset Lucas De Marchi
2019-08-17 9:38 ` [PATCH v2 28/40] drm/i915/tgl: add GEN12_MAX_CONTEXT_HW_ID Lucas De Marchi
2019-08-21 14:43 ` Lisovskiy, Stanislav
2019-08-17 9:38 ` [PATCH v2 29/40] drm/i915/tgl: Gen12 csb support Lucas De Marchi
2019-08-17 9:38 ` [PATCH v2 30/40] drm/i915/tgl: Report valid VDBoxes with SFC capability Lucas De Marchi
2019-08-17 9:38 ` [PATCH v2 31/40] rm/i915/tgl: Move GTCR register to cope with GAM MMIO address remap Lucas De Marchi
2019-08-20 20:43 ` Lucas De Marchi
2019-08-22 13:28 ` Mika Kuoppala
2019-08-23 0:44 ` Lucas De Marchi
2019-08-17 9:38 ` [PATCH v2 32/40] drm/i915/tgl: Updated Private PAT programming Lucas De Marchi
2019-08-20 10:33 ` Chris Wilson
2019-08-17 9:38 ` [PATCH v2 33/40] drm/i915/tgl/perf: use the same oa ctx_id format as icl Lucas De Marchi
2019-08-21 12:36 ` Lionel Landwerlin
2019-08-17 9:38 ` [PATCH v2 34/40] drm/i915/perf: add a parameter to control the size of OA buffer Lucas De Marchi
2019-08-17 9:38 ` [PATCH v2 35/40] drm/i915/tgl: Add perf support on TGL Lucas De Marchi
2019-08-17 9:38 ` [PATCH v2 36/40] drm/i915/tgl: Gen-12 display loses Yf tiling and legacy CCS support Lucas De Marchi
2019-08-17 9:38 ` [PATCH v2 37/40] drm/framebuffer/tgl: Format modifier for Intel Gen-12 render compression Lucas De Marchi
2019-08-21 14:34 ` Lisovskiy, Stanislav
2019-08-17 9:39 ` [PATCH v2 38/40] drm/i915/tgl: Gen-12 render decompression Lucas De Marchi
2019-08-17 9:39 ` [PATCH v2 39/40] drm/framebuffer/tgl: Format modifier for Intel Gen-12 media compression Lucas De Marchi
2019-08-21 14:40 ` Lisovskiy, Stanislav
2019-08-17 9:39 ` [PATCH v2 40/40] drm/i915/tgl: " Lucas De Marchi
2019-08-21 14:36 ` Lisovskiy, Stanislav
2019-08-17 9:49 ` ✗ Fi.CI.CHECKPATCH: warning for Tiger Lake batch 3 (rev2) Patchwork
2019-08-17 10:03 ` ✗ Fi.CI.SPARSE: " Patchwork
2019-08-17 10:12 ` ✗ Fi.CI.BAT: failure " Patchwork
2019-08-20 10:28 ` ✗ Fi.CI.CHECKPATCH: warning for Tiger Lake batch 3 (rev3) Patchwork
2019-08-20 10:42 ` ✗ Fi.CI.SPARSE: " Patchwork
2019-08-20 12:15 ` ✗ Fi.CI.BAT: failure " Patchwork
2019-08-20 12:36 ` ✓ Fi.CI.BAT: success " Patchwork
2019-08-20 17:59 ` ✓ Fi.CI.IGT: " Patchwork
2019-08-20 22:30 ` ✗ Fi.CI.BAT: failure for Tiger Lake batch 3 (rev4) Patchwork
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