All of lore.kernel.org
 help / color / mirror / Atom feed
From: Stuart Summers <stuart.summers@intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [PATCH 4/9] drm/i915: Add EU stride runtime parameter
Date: Mon, 19 Aug 2019 14:49:58 -0700	[thread overview]
Message-ID: <20190819215003.48305-5-stuart.summers@intel.com> (raw)
In-Reply-To: <20190819215003.48305-1-stuart.summers@intel.com>

Add a new SSEU runtime parameter, eu_stride, which is
used to mirror the userspace concept of a range of EUs
per subslice.

This patch simply adds the parameter and updates usage
in the QUERY_TOPOLOGY_INFO handler.

Signed-off-by: Stuart Summers <stuart.summers@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_sseu.c     | 1 +
 drivers/gpu/drm/i915/gt/intel_sseu.h     | 1 +
 drivers/gpu/drm/i915/i915_query.c        | 5 ++---
 drivers/gpu/drm/i915/intel_device_info.c | 9 ++++-----
 4 files changed, 8 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.c b/drivers/gpu/drm/i915/gt/intel_sseu.c
index 5b8246138020..3a5c0f7b5a08 100644
--- a/drivers/gpu/drm/i915/gt/intel_sseu.c
+++ b/drivers/gpu/drm/i915/gt/intel_sseu.c
@@ -16,6 +16,7 @@ void intel_sseu_set_info(struct sseu_dev_info *sseu, u8 max_slices,
 	sseu->max_eus_per_subslice = max_eus_per_subslice;
 
 	sseu->ss_stride = GEN_SSEU_STRIDE(sseu->max_subslices);
+	sseu->eu_stride = GEN_SSEU_STRIDE(sseu->max_eus_per_subslice);
 }
 
 unsigned int
diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.h b/drivers/gpu/drm/i915/gt/intel_sseu.h
index b0101e1c69bd..fe22d5b18e67 100644
--- a/drivers/gpu/drm/i915/gt/intel_sseu.h
+++ b/drivers/gpu/drm/i915/gt/intel_sseu.h
@@ -34,6 +34,7 @@ struct sseu_dev_info {
 	u8 max_eus_per_subslice;
 
 	u8 ss_stride;
+	u8 eu_stride;
 
 	/* We don't have more than 8 eus per subslice at the moment and as we
 	 * store eus enabled using bits, no need to multiply by eus per
diff --git a/drivers/gpu/drm/i915/i915_query.c b/drivers/gpu/drm/i915/i915_query.c
index d8e25dcf5f0b..abac5042da2b 100644
--- a/drivers/gpu/drm/i915/i915_query.c
+++ b/drivers/gpu/drm/i915/i915_query.c
@@ -37,7 +37,6 @@ static int query_topology_info(struct drm_i915_private *dev_priv,
 	const struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu;
 	struct drm_i915_query_topology_info topo;
 	u32 slice_length, subslice_length, eu_length, total_length;
-	u8 eu_stride = GEN_SSEU_STRIDE(sseu->max_eus_per_subslice);
 	int ret;
 
 	if (query_item->flags != 0)
@@ -50,7 +49,7 @@ static int query_topology_info(struct drm_i915_private *dev_priv,
 
 	slice_length = sizeof(sseu->slice_mask);
 	subslice_length = sseu->max_slices * sseu->ss_stride;
-	eu_length = sseu->max_slices * sseu->max_subslices * eu_stride;
+	eu_length = sseu->max_slices * sseu->max_subslices * sseu->eu_stride;
 	total_length = sizeof(topo) + slice_length + subslice_length +
 		       eu_length;
 
@@ -70,7 +69,7 @@ static int query_topology_info(struct drm_i915_private *dev_priv,
 	topo.subslice_offset = slice_length;
 	topo.subslice_stride = sseu->ss_stride;
 	topo.eu_offset = slice_length + subslice_length;
-	topo.eu_stride = eu_stride;
+	topo.eu_stride = sseu->eu_stride;
 
 	if (__copy_to_user(u64_to_user_ptr(query_item->data_ptr),
 			   &topo, sizeof(topo)))
diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index 9a79d9d547c5..7de7b7b540cb 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -118,10 +118,9 @@ void intel_device_info_dump_runtime(const struct intel_runtime_info *info,
 static int sseu_eu_idx(const struct sseu_dev_info *sseu, int slice,
 		       int subslice)
 {
-	int subslice_stride = GEN_SSEU_STRIDE(sseu->max_eus_per_subslice);
-	int slice_stride = sseu->max_subslices * subslice_stride;
+	int slice_stride = sseu->max_subslices * sseu->eu_stride;
 
-	return slice * slice_stride + subslice * subslice_stride;
+	return slice * slice_stride + subslice * sseu->eu_stride;
 }
 
 static u16 sseu_get_eus(const struct sseu_dev_info *sseu, int slice,
@@ -130,7 +129,7 @@ static u16 sseu_get_eus(const struct sseu_dev_info *sseu, int slice,
 	int i, offset = sseu_eu_idx(sseu, slice, subslice);
 	u16 eu_mask = 0;
 
-	for (i = 0; i < GEN_SSEU_STRIDE(sseu->max_eus_per_subslice); i++) {
+	for (i = 0; i < sseu->eu_stride; i++) {
 		eu_mask |= ((u16)sseu->eu_mask[offset + i]) <<
 			(i * BITS_PER_BYTE);
 	}
@@ -143,7 +142,7 @@ static void sseu_set_eus(struct sseu_dev_info *sseu, int slice, int subslice,
 {
 	int i, offset = sseu_eu_idx(sseu, slice, subslice);
 
-	for (i = 0; i < GEN_SSEU_STRIDE(sseu->max_eus_per_subslice); i++) {
+	for (i = 0; i < sseu->eu_stride; i++) {
 		sseu->eu_mask[offset + i] =
 			(eu_mask >> (BITS_PER_BYTE * i)) & 0xff;
 	}
-- 
2.22.0

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

  parent reply	other threads:[~2019-08-19 21:49 UTC|newest]

Thread overview: 25+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-08-19 21:49 [PATCH 0/9] Refactor to expand subslice mask (rev 2) Stuart Summers
2019-08-19 21:49 ` [PATCH 1/9] drm/i915: Use variable for debugfs device status Stuart Summers
2019-08-19 21:49 ` [PATCH 2/9] drm/i915: Add function to set SSEU info per platform Stuart Summers
2019-08-20  7:44   ` Mika Kuoppala
2019-08-19 21:49 ` [PATCH 3/9] drm/i915: Add subslice stride runtime parameter Stuart Summers
2019-08-20 10:46   ` Chris Wilson
2019-08-19 21:49 ` Stuart Summers [this message]
2019-08-20 10:47   ` [PATCH 4/9] drm/i915: Add EU " Chris Wilson
2019-08-19 21:49 ` [PATCH 5/9] drm/i915: Add function to set subslices Stuart Summers
2019-08-20 10:51   ` Chris Wilson
2019-08-19 21:50 ` [PATCH 6/9] drm/i915: Add function to determine if a slice has a subslice Stuart Summers
2019-08-20 10:53   ` Chris Wilson
2019-08-20 19:01     ` Summers, Stuart
2019-08-20 19:20       ` Chris Wilson
2019-08-19 21:50 ` [PATCH 7/9] drm/i915: Refactor instdone loops on new subslice functions Stuart Summers
2019-08-19 21:50 ` [PATCH 8/9] drm/i915: Add new function to copy subslices for a slice Stuart Summers
2019-08-19 21:50 ` [PATCH 9/9] drm/i915: Expand subslice mask Stuart Summers
2019-08-19 21:55 ` ✗ Fi.CI.CHECKPATCH: warning for Refactor to expand subslice mask (rev 2) Patchwork
2019-08-19 22:39 ` ✓ Fi.CI.BAT: success " Patchwork
2019-08-20 10:44 ` ✓ Fi.CI.IGT: " Patchwork
2019-08-20 11:10 ` Patchwork
  -- strict thread matches above, loose matches on Subject: below --
2019-08-19 21:18 [PATCH 0/9] " Stuart Summers
2019-08-19 21:18 ` [PATCH 4/9] drm/i915: Add EU stride runtime parameter Stuart Summers
2019-08-07 16:58 [PATCH 0/9] Refactor to expand subslice mask (rev 2) Stuart Summers
2019-08-07 16:58 ` [PATCH 4/9] drm/i915: Add EU stride runtime parameter Stuart Summers
2019-07-24 17:12 [PATCH 0/9] Refactor to expand subslice mask (rev 2) Stuart Summers
2019-07-24 17:12 ` [PATCH 4/9] drm/i915: Add EU stride runtime parameter Stuart Summers
2019-07-23 15:49 [PATCH 0/9] Refactor to expand subslice mask (rev 2) Stuart Summers
2019-07-23 15:49 ` [PATCH 4/9] drm/i915: Add EU stride runtime parameter Stuart Summers

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20190819215003.48305-5-stuart.summers@intel.com \
    --to=stuart.summers@intel.com \
    --cc=intel-gfx@lists.freedesktop.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.