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Violators will be prosecuted; (version=TLSv1/SSLv3 cipher=AES256-GCM-SHA384 bits=256/256) Wed, 21 Aug 2019 14:56:11 +0100 Received: from b01ledav003.gho.pok.ibm.com (b01ledav003.gho.pok.ibm.com [9.57.199.108]) by b01cxnp23034.gho.pok.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id x7LDuAiH33358122 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Wed, 21 Aug 2019 13:56:10 GMT Received: from b01ledav003.gho.pok.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 61457B205F; Wed, 21 Aug 2019 13:56:10 +0000 (GMT) Received: from b01ledav003.gho.pok.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 4314CB2065; Wed, 21 Aug 2019 13:56:10 +0000 (GMT) Received: from paulmck-ThinkPad-W541 (unknown [9.70.82.154]) by b01ledav003.gho.pok.ibm.com (Postfix) with ESMTP; Wed, 21 Aug 2019 13:56:10 +0000 (GMT) Received: by paulmck-ThinkPad-W541 (Postfix, from userid 1000) id D0B6216C1AFD; Wed, 21 Aug 2019 06:56:10 -0700 (PDT) Date: Wed, 21 Aug 2019 06:56:10 -0700 From: "Paul E. McKenney" To: Will Deacon Cc: Peter Zijlstra , Linus Torvalds , Mathieu Desnoyers , Thomas Gleixner , Joel Fernandes , Alan Stern , rostedt , Valentin Schneider , linux-kernel , Boqun Feng , Will Deacon , David Howells Subject: Re: [PATCH 1/1] Fix: trace sched switch start/stop racy updates Reply-To: paulmck@linux.ibm.com References: <1642847744.23403.1566005809759.JavaMail.zimbra@efficios.com> <20190820135612.GS2332@hirez.programming.kicks-ass.net> <20190820202932.GW28441@linux.ibm.com> <20190821103200.kpufwtviqhpbuv2n@willie-the-truck> <20190821132310.GC28441@linux.ibm.com> <20190821133247.vke6fnndm64h2lla@willie-the-truck> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20190821133247.vke6fnndm64h2lla@willie-the-truck> User-Agent: Mutt/1.5.21 (2010-09-15) X-TM-AS-GCONF: 00 x-cbid: 19082113-2213-0000-0000-000003BE74D1 X-IBM-SpamModules-Scores: X-IBM-SpamModules-Versions: BY=3.00011629; HX=3.00000242; KW=3.00000007; PH=3.00000004; SC=3.00000287; SDB=6.01250013; UDB=6.00659928; IPR=6.01031567; MB=3.00028261; MTD=3.00000008; XFM=3.00000015; UTC=2019-08-21 13:56:15 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 19082113-2214-0000-0000-00005FB81C3D Message-Id: <20190821135610.GD28441@linux.ibm.com> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:,, definitions=2019-08-21_05:,, signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=0 phishscore=0 bulkscore=0 spamscore=0 clxscore=1015 lowpriorityscore=0 mlxscore=0 impostorscore=0 mlxlogscore=965 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1906280000 definitions=main-1908210153 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, Aug 21, 2019 at 02:32:48PM +0100, Will Deacon wrote: > On Wed, Aug 21, 2019 at 06:23:10AM -0700, Paul E. McKenney wrote: > > On Wed, Aug 21, 2019 at 11:32:01AM +0100, Will Deacon wrote: > > > void bar(u64 *x) > > > { > > > *(volatile u64 *)x = 0xabcdef10abcdef10; > > > } > > > > > > then I get: > > > > > > bar: > > > mov w1, 61200 > > > movk w1, 0xabcd, lsl 16 > > > str w1, [x0] > > > str w1, [x0, 4] > > > ret > > > > > > so I'm not sure that WRITE_ONCE would even help :/ > > > > Well, I can have the LWN article cite your email, then. So thank you > > very much! > > > > Is generation of this code for a 64-bit volatile store considered a bug? > > I consider it a bug for the volatile case, and the one compiler person I've > spoken to also seems to reckon it's a bug, so hopefully it will be fixed. > I'm led to believe it's an optimisation in the AArch64 backend of GCC. Here is hoping for the fix! > > Or does ARMv8 exclude the possibility of 64-bit MMIO registers? And I > > would guess that Thomas and Linus would ask a similar bugginess question > > for normal stores. ;-) > > We use inline asm for MMIO, fwiw. I should have remembered that, shouldn't I have? ;-) Is that also common practice across other embedded kernels these days? Thanx, Paul