* [PATCH 00/11] Refactor to expand subslice mask (rev 2)
@ 2019-08-20 23:05 Stuart Summers
2019-08-20 23:05 ` [PATCH 01/11] drm/i915: Use variable for debugfs device status Stuart Summers
` (14 more replies)
0 siblings, 15 replies; 32+ messages in thread
From: Stuart Summers @ 2019-08-20 23:05 UTC (permalink / raw)
To: intel-gfx
Currently, the subslice_mask runtime parameter is stored as an
array of subslices per slice. Expand the subslice mask array to
better match what is presented to userspace through the
I915_QUERY_TOPOLOGY_INFO ioctl. The index into this array is
then calculated:
slice * subslice stride + subslice index / 8
Note this is the second iteration of an original patch to implement
the same. There are a couple of minor code changes based on changes
since the first series was posted. Additionally, the original patch
has been split into several smaller patches with more isolated
changes based on review feedback in that first series.
Link to the original series:
https://patchwork.freedesktop.org/series/59742/
v2: Fix 32-bit build
v3: Fix typo in haswell sseu info routine and fix SSEU workaround
print
v4: Merge patch to HSW in previous revision with patch to
set subslice_mask for each platform and address feedback
from Chris
v5: No changes in code. Resending due to unrelated failures - confirmed
no failures with trybot.
v6: Minor change in intel_workarounds.c to use the new helper function
v7: Split set sublice function into multiple more manageable patches
And add a couple of GEM_BUG_ON checks requested by Chris
Stuart Summers (11):
drm/i915: Use variable for debugfs device status
drm/i915: Add function to set SSEU info per platform
drm/i915: Add subslice stride runtime parameter
drm/i915: Add EU stride runtime parameter
drm/i915: Use local variables for subslice_mask for device info
drm/i915: Add function to set subslices
drm/i915: Use subslice stride to set subslices for a given slice
drm/i915: Add function to determine if a slice has a subslice
drm/i915: Refactor instdone loops on new subslice functions
drm/i915: Add new function to copy subslices for a slice
drm/i915: Expand subslice mask
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 3 +-
drivers/gpu/drm/i915/gt/intel_engine_types.h | 31 +++--
drivers/gpu/drm/i915/gt/intel_hangcheck.c | 3 +-
drivers/gpu/drm/i915/gt/intel_sseu.c | 52 +++++++-
drivers/gpu/drm/i915/gt/intel_sseu.h | 30 ++++-
drivers/gpu/drm/i915/gt/intel_workarounds.c | 5 +-
drivers/gpu/drm/i915/i915_debugfs.c | 49 +++++---
drivers/gpu/drm/i915/i915_gpu_error.c | 5 +-
drivers/gpu/drm/i915/i915_query.c | 10 +-
drivers/gpu/drm/i915/intel_device_info.c | 122 +++++++++----------
10 files changed, 196 insertions(+), 114 deletions(-)
--
2.22.0
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 32+ messages in thread
* [PATCH 01/11] drm/i915: Use variable for debugfs device status
2019-08-20 23:05 [PATCH 00/11] Refactor to expand subslice mask (rev 2) Stuart Summers
@ 2019-08-20 23:05 ` Stuart Summers
2019-08-20 23:05 ` [PATCH 02/11] drm/i915: Add function to set SSEU info per platform Stuart Summers
` (13 subsequent siblings)
14 siblings, 0 replies; 32+ messages in thread
From: Stuart Summers @ 2019-08-20 23:05 UTC (permalink / raw)
To: intel-gfx
Use a local variable to find SSEU runtime information
in various debugfs functions.
v2: Remove extra line breaks per feedback from Chris
Signed-off-by: Stuart Summers <stuart.summers@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
---
drivers/gpu/drm/i915/i915_debugfs.c | 26 +++++++++++---------------
1 file changed, 11 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index b39226d7f8d2..b52c04f44f32 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -3844,8 +3844,7 @@ static void gen9_sseu_device_status(struct drm_i915_private *dev_priv,
sseu->slice_mask |= BIT(s);
if (IS_GEN9_BC(dev_priv))
- sseu->subslice_mask[s] =
- RUNTIME_INFO(dev_priv)->sseu.subslice_mask[s];
+ sseu->subslice_mask[s] = info->sseu.subslice_mask[s];
for (ss = 0; ss < info->sseu.max_subslices; ss++) {
unsigned int eu_cnt;
@@ -3872,25 +3871,22 @@ static void gen9_sseu_device_status(struct drm_i915_private *dev_priv,
static void broadwell_sseu_device_status(struct drm_i915_private *dev_priv,
struct sseu_dev_info *sseu)
{
+ const struct intel_runtime_info *info = RUNTIME_INFO(dev_priv);
u32 slice_info = I915_READ(GEN8_GT_SLICE_INFO);
int s;
sseu->slice_mask = slice_info & GEN8_LSLICESTAT_MASK;
if (sseu->slice_mask) {
- sseu->eu_per_subslice =
- RUNTIME_INFO(dev_priv)->sseu.eu_per_subslice;
- for (s = 0; s < fls(sseu->slice_mask); s++) {
- sseu->subslice_mask[s] =
- RUNTIME_INFO(dev_priv)->sseu.subslice_mask[s];
- }
+ sseu->eu_per_subslice = info->sseu.eu_per_subslice;
+ for (s = 0; s < fls(sseu->slice_mask); s++)
+ sseu->subslice_mask[s] = info->sseu.subslice_mask[s];
sseu->eu_total = sseu->eu_per_subslice *
intel_sseu_subslice_total(sseu);
/* subtract fused off EU(s) from enabled slice(s) */
for (s = 0; s < fls(sseu->slice_mask); s++) {
- u8 subslice_7eu =
- RUNTIME_INFO(dev_priv)->sseu.subslice_7eu[s];
+ u8 subslice_7eu = info->sseu.subslice_7eu[s];
sseu->eu_total -= hweight8(subslice_7eu);
}
@@ -3937,6 +3933,7 @@ static void i915_print_sseu_info(struct seq_file *m, bool is_available_info,
static int i915_sseu_status(struct seq_file *m, void *unused)
{
struct drm_i915_private *dev_priv = node_to_i915(m->private);
+ const struct intel_runtime_info *info = RUNTIME_INFO(dev_priv);
struct sseu_dev_info sseu;
intel_wakeref_t wakeref;
@@ -3944,14 +3941,13 @@ static int i915_sseu_status(struct seq_file *m, void *unused)
return -ENODEV;
seq_puts(m, "SSEU Device Info\n");
- i915_print_sseu_info(m, true, &RUNTIME_INFO(dev_priv)->sseu);
+ i915_print_sseu_info(m, true, &info->sseu);
seq_puts(m, "SSEU Device Status\n");
memset(&sseu, 0, sizeof(sseu));
- sseu.max_slices = RUNTIME_INFO(dev_priv)->sseu.max_slices;
- sseu.max_subslices = RUNTIME_INFO(dev_priv)->sseu.max_subslices;
- sseu.max_eus_per_subslice =
- RUNTIME_INFO(dev_priv)->sseu.max_eus_per_subslice;
+ sseu.max_slices = info->sseu.max_slices;
+ sseu.max_subslices = info->sseu.max_subslices;
+ sseu.max_eus_per_subslice = info->sseu.max_eus_per_subslice;
with_intel_runtime_pm(&dev_priv->runtime_pm, wakeref) {
if (IS_CHERRYVIEW(dev_priv))
--
2.22.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [PATCH 02/11] drm/i915: Add function to set SSEU info per platform
2019-08-20 23:05 [PATCH 00/11] Refactor to expand subslice mask (rev 2) Stuart Summers
2019-08-20 23:05 ` [PATCH 01/11] drm/i915: Use variable for debugfs device status Stuart Summers
@ 2019-08-20 23:05 ` Stuart Summers
2019-08-20 23:05 ` [PATCH 03/11] drm/i915: Add subslice stride runtime parameter Stuart Summers
` (12 subsequent siblings)
14 siblings, 0 replies; 32+ messages in thread
From: Stuart Summers @ 2019-08-20 23:05 UTC (permalink / raw)
To: intel-gfx
Add a new function to allow each platform to set maximum
slice, subslice, and EU information to reduce code duplication.
Signed-off-by: Stuart Summers <stuart.summers@intel.com>
Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
---
drivers/gpu/drm/i915/gt/intel_sseu.c | 8 +++++
drivers/gpu/drm/i915/gt/intel_sseu.h | 3 ++
drivers/gpu/drm/i915/i915_debugfs.c | 6 ++--
drivers/gpu/drm/i915/intel_device_info.c | 39 +++++++++---------------
4 files changed, 28 insertions(+), 28 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.c b/drivers/gpu/drm/i915/gt/intel_sseu.c
index 6bf2d87da109..6727079eb9b6 100644
--- a/drivers/gpu/drm/i915/gt/intel_sseu.c
+++ b/drivers/gpu/drm/i915/gt/intel_sseu.c
@@ -8,6 +8,14 @@
#include "intel_lrc_reg.h"
#include "intel_sseu.h"
+void intel_sseu_set_info(struct sseu_dev_info *sseu, u8 max_slices,
+ u8 max_subslices, u8 max_eus_per_subslice)
+{
+ sseu->max_slices = max_slices;
+ sseu->max_subslices = max_subslices;
+ sseu->max_eus_per_subslice = max_eus_per_subslice;
+}
+
unsigned int
intel_sseu_subslice_total(const struct sseu_dev_info *sseu)
{
diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.h b/drivers/gpu/drm/i915/gt/intel_sseu.h
index b50d0401a4e2..64e47dad07be 100644
--- a/drivers/gpu/drm/i915/gt/intel_sseu.h
+++ b/drivers/gpu/drm/i915/gt/intel_sseu.h
@@ -63,6 +63,9 @@ intel_sseu_from_device_info(const struct sseu_dev_info *sseu)
return value;
}
+void intel_sseu_set_info(struct sseu_dev_info *sseu, u8 max_slices,
+ u8 max_subslices, u8 max_eus_per_subslice);
+
unsigned int
intel_sseu_subslice_total(const struct sseu_dev_info *sseu);
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index b52c04f44f32..abf0f6ba213c 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -3945,9 +3945,9 @@ static int i915_sseu_status(struct seq_file *m, void *unused)
seq_puts(m, "SSEU Device Status\n");
memset(&sseu, 0, sizeof(sseu));
- sseu.max_slices = info->sseu.max_slices;
- sseu.max_subslices = info->sseu.max_subslices;
- sseu.max_eus_per_subslice = info->sseu.max_eus_per_subslice;
+ intel_sseu_set_info(&sseu, info->sseu.max_slices,
+ info->sseu.max_subslices,
+ info->sseu.max_eus_per_subslice);
with_intel_runtime_pm(&dev_priv->runtime_pm, wakeref) {
if (IS_CHERRYVIEW(dev_priv))
diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index d0ed44d33484..77d7bbaa49f3 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -191,15 +191,10 @@ static void gen11_sseu_info_init(struct drm_i915_private *dev_priv)
u8 eu_en;
int s;
- if (IS_ELKHARTLAKE(dev_priv)) {
- sseu->max_slices = 1;
- sseu->max_subslices = 4;
- sseu->max_eus_per_subslice = 8;
- } else {
- sseu->max_slices = 1;
- sseu->max_subslices = 8;
- sseu->max_eus_per_subslice = 8;
- }
+ if (IS_ELKHARTLAKE(dev_priv))
+ intel_sseu_set_info(sseu, 1, 4, 8);
+ else
+ intel_sseu_set_info(sseu, 1, 8, 8);
s_en = I915_READ(GEN11_GT_SLICE_ENABLE) & GEN11_GT_S_ENA_MASK;
ss_en = ~I915_READ(GEN11_GT_SUBSLICE_DISABLE);
@@ -236,11 +231,10 @@ static void gen10_sseu_info_init(struct drm_i915_private *dev_priv)
const int eu_mask = 0xff;
u32 subslice_mask, eu_en;
+ intel_sseu_set_info(sseu, 6, 4, 8);
+
sseu->slice_mask = (fuse2 & GEN10_F2_S_ENA_MASK) >>
GEN10_F2_S_ENA_SHIFT;
- sseu->max_slices = 6;
- sseu->max_subslices = 4;
- sseu->max_eus_per_subslice = 8;
subslice_mask = (1 << 4) - 1;
subslice_mask &= ~((fuse2 & GEN10_F2_SS_DIS_MASK) >>
@@ -314,9 +308,7 @@ static void cherryview_sseu_info_init(struct drm_i915_private *dev_priv)
fuse = I915_READ(CHV_FUSE_GT);
sseu->slice_mask = BIT(0);
- sseu->max_slices = 1;
- sseu->max_subslices = 2;
- sseu->max_eus_per_subslice = 8;
+ intel_sseu_set_info(sseu, 1, 2, 8);
if (!(fuse & CHV_FGT_DISABLE_SS0)) {
u8 disabled_mask =
@@ -372,9 +364,8 @@ static void gen9_sseu_info_init(struct drm_i915_private *dev_priv)
sseu->slice_mask = (fuse2 & GEN8_F2_S_ENA_MASK) >> GEN8_F2_S_ENA_SHIFT;
/* BXT has a single slice and at most 3 subslices. */
- sseu->max_slices = IS_GEN9_LP(dev_priv) ? 1 : 3;
- sseu->max_subslices = IS_GEN9_LP(dev_priv) ? 3 : 4;
- sseu->max_eus_per_subslice = 8;
+ intel_sseu_set_info(sseu, IS_GEN9_LP(dev_priv) ? 1 : 3,
+ IS_GEN9_LP(dev_priv) ? 3 : 4, 8);
/*
* The subslice disable field is global, i.e. it applies
@@ -473,9 +464,7 @@ static void broadwell_sseu_info_init(struct drm_i915_private *dev_priv)
fuse2 = I915_READ(GEN8_FUSE2);
sseu->slice_mask = (fuse2 & GEN8_F2_S_ENA_MASK) >> GEN8_F2_S_ENA_SHIFT;
- sseu->max_slices = 3;
- sseu->max_subslices = 3;
- sseu->max_eus_per_subslice = 8;
+ intel_sseu_set_info(sseu, 3, 3, 8);
/*
* The subslice disable field is global, i.e. it applies
@@ -577,9 +566,6 @@ static void haswell_sseu_info_init(struct drm_i915_private *dev_priv)
break;
}
- sseu->max_slices = hweight8(sseu->slice_mask);
- sseu->max_subslices = hweight8(sseu->subslice_mask[0]);
-
fuse1 = I915_READ(HSW_PAVP_FUSE1);
switch ((fuse1 & HSW_F1_EU_DIS_MASK) >> HSW_F1_EU_DIS_SHIFT) {
default:
@@ -596,7 +582,10 @@ static void haswell_sseu_info_init(struct drm_i915_private *dev_priv)
sseu->eu_per_subslice = 6;
break;
}
- sseu->max_eus_per_subslice = sseu->eu_per_subslice;
+
+ intel_sseu_set_info(sseu, hweight8(sseu->slice_mask),
+ hweight8(sseu->subslice_mask[0]),
+ sseu->eu_per_subslice);
for (s = 0; s < sseu->max_slices; s++) {
for (ss = 0; ss < sseu->max_subslices; ss++) {
--
2.22.0
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [PATCH 03/11] drm/i915: Add subslice stride runtime parameter
2019-08-20 23:05 [PATCH 00/11] Refactor to expand subslice mask (rev 2) Stuart Summers
2019-08-20 23:05 ` [PATCH 01/11] drm/i915: Use variable for debugfs device status Stuart Summers
2019-08-20 23:05 ` [PATCH 02/11] drm/i915: Add function to set SSEU info per platform Stuart Summers
@ 2019-08-20 23:05 ` Stuart Summers
2019-08-20 23:05 ` [PATCH 04/11] drm/i915: Add EU " Stuart Summers
` (11 subsequent siblings)
14 siblings, 0 replies; 32+ messages in thread
From: Stuart Summers @ 2019-08-20 23:05 UTC (permalink / raw)
To: intel-gfx
Add a new parameter, ss_stride, to the runtime info
structure. This is used to mirror the userspace concept
of subslice stride, which is a range of subslices per slice.
This patch simply adds the definition and updates usage
in the QUERY_TOPOLOGY_INFO handler.
Signed-off-by: Stuart Summers <stuart.summers@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
---
drivers/gpu/drm/i915/gt/intel_sseu.c | 2 ++
drivers/gpu/drm/i915/gt/intel_sseu.h | 2 ++
drivers/gpu/drm/i915/i915_query.c | 5 ++---
3 files changed, 6 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.c b/drivers/gpu/drm/i915/gt/intel_sseu.c
index 6727079eb9b6..5b8246138020 100644
--- a/drivers/gpu/drm/i915/gt/intel_sseu.c
+++ b/drivers/gpu/drm/i915/gt/intel_sseu.c
@@ -14,6 +14,8 @@ void intel_sseu_set_info(struct sseu_dev_info *sseu, u8 max_slices,
sseu->max_slices = max_slices;
sseu->max_subslices = max_subslices;
sseu->max_eus_per_subslice = max_eus_per_subslice;
+
+ sseu->ss_stride = GEN_SSEU_STRIDE(sseu->max_subslices);
}
unsigned int
diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.h b/drivers/gpu/drm/i915/gt/intel_sseu.h
index 64e47dad07be..b0101e1c69bd 100644
--- a/drivers/gpu/drm/i915/gt/intel_sseu.h
+++ b/drivers/gpu/drm/i915/gt/intel_sseu.h
@@ -33,6 +33,8 @@ struct sseu_dev_info {
u8 max_subslices;
u8 max_eus_per_subslice;
+ u8 ss_stride;
+
/* We don't have more than 8 eus per subslice at the moment and as we
* store eus enabled using bits, no need to multiply by eus per
* subslice.
diff --git a/drivers/gpu/drm/i915/i915_query.c b/drivers/gpu/drm/i915/i915_query.c
index ad9240a0817a..d8e25dcf5f0b 100644
--- a/drivers/gpu/drm/i915/i915_query.c
+++ b/drivers/gpu/drm/i915/i915_query.c
@@ -37,7 +37,6 @@ static int query_topology_info(struct drm_i915_private *dev_priv,
const struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu;
struct drm_i915_query_topology_info topo;
u32 slice_length, subslice_length, eu_length, total_length;
- u8 subslice_stride = GEN_SSEU_STRIDE(sseu->max_subslices);
u8 eu_stride = GEN_SSEU_STRIDE(sseu->max_eus_per_subslice);
int ret;
@@ -50,7 +49,7 @@ static int query_topology_info(struct drm_i915_private *dev_priv,
BUILD_BUG_ON(sizeof(u8) != sizeof(sseu->slice_mask));
slice_length = sizeof(sseu->slice_mask);
- subslice_length = sseu->max_slices * subslice_stride;
+ subslice_length = sseu->max_slices * sseu->ss_stride;
eu_length = sseu->max_slices * sseu->max_subslices * eu_stride;
total_length = sizeof(topo) + slice_length + subslice_length +
eu_length;
@@ -69,7 +68,7 @@ static int query_topology_info(struct drm_i915_private *dev_priv,
topo.max_eus_per_subslice = sseu->max_eus_per_subslice;
topo.subslice_offset = slice_length;
- topo.subslice_stride = subslice_stride;
+ topo.subslice_stride = sseu->ss_stride;
topo.eu_offset = slice_length + subslice_length;
topo.eu_stride = eu_stride;
--
2.22.0
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [PATCH 04/11] drm/i915: Add EU stride runtime parameter
2019-08-20 23:05 [PATCH 00/11] Refactor to expand subslice mask (rev 2) Stuart Summers
` (2 preceding siblings ...)
2019-08-20 23:05 ` [PATCH 03/11] drm/i915: Add subslice stride runtime parameter Stuart Summers
@ 2019-08-20 23:05 ` Stuart Summers
2019-08-20 23:05 ` [PATCH 05/11] drm/i915: Use local variables for subslice_mask for device info Stuart Summers
` (10 subsequent siblings)
14 siblings, 0 replies; 32+ messages in thread
From: Stuart Summers @ 2019-08-20 23:05 UTC (permalink / raw)
To: intel-gfx
Add a new SSEU runtime parameter, eu_stride, which is
used to mirror the userspace concept of a range of EUs
per subslice.
This patch simply adds the parameter and updates usage
in the QUERY_TOPOLOGY_INFO handler.
Signed-off-by: Stuart Summers <stuart.summers@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
---
drivers/gpu/drm/i915/gt/intel_sseu.c | 1 +
drivers/gpu/drm/i915/gt/intel_sseu.h | 1 +
drivers/gpu/drm/i915/i915_query.c | 5 ++---
drivers/gpu/drm/i915/intel_device_info.c | 9 ++++-----
4 files changed, 8 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.c b/drivers/gpu/drm/i915/gt/intel_sseu.c
index 5b8246138020..3a5c0f7b5a08 100644
--- a/drivers/gpu/drm/i915/gt/intel_sseu.c
+++ b/drivers/gpu/drm/i915/gt/intel_sseu.c
@@ -16,6 +16,7 @@ void intel_sseu_set_info(struct sseu_dev_info *sseu, u8 max_slices,
sseu->max_eus_per_subslice = max_eus_per_subslice;
sseu->ss_stride = GEN_SSEU_STRIDE(sseu->max_subslices);
+ sseu->eu_stride = GEN_SSEU_STRIDE(sseu->max_eus_per_subslice);
}
unsigned int
diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.h b/drivers/gpu/drm/i915/gt/intel_sseu.h
index b0101e1c69bd..fe22d5b18e67 100644
--- a/drivers/gpu/drm/i915/gt/intel_sseu.h
+++ b/drivers/gpu/drm/i915/gt/intel_sseu.h
@@ -34,6 +34,7 @@ struct sseu_dev_info {
u8 max_eus_per_subslice;
u8 ss_stride;
+ u8 eu_stride;
/* We don't have more than 8 eus per subslice at the moment and as we
* store eus enabled using bits, no need to multiply by eus per
diff --git a/drivers/gpu/drm/i915/i915_query.c b/drivers/gpu/drm/i915/i915_query.c
index d8e25dcf5f0b..abac5042da2b 100644
--- a/drivers/gpu/drm/i915/i915_query.c
+++ b/drivers/gpu/drm/i915/i915_query.c
@@ -37,7 +37,6 @@ static int query_topology_info(struct drm_i915_private *dev_priv,
const struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu;
struct drm_i915_query_topology_info topo;
u32 slice_length, subslice_length, eu_length, total_length;
- u8 eu_stride = GEN_SSEU_STRIDE(sseu->max_eus_per_subslice);
int ret;
if (query_item->flags != 0)
@@ -50,7 +49,7 @@ static int query_topology_info(struct drm_i915_private *dev_priv,
slice_length = sizeof(sseu->slice_mask);
subslice_length = sseu->max_slices * sseu->ss_stride;
- eu_length = sseu->max_slices * sseu->max_subslices * eu_stride;
+ eu_length = sseu->max_slices * sseu->max_subslices * sseu->eu_stride;
total_length = sizeof(topo) + slice_length + subslice_length +
eu_length;
@@ -70,7 +69,7 @@ static int query_topology_info(struct drm_i915_private *dev_priv,
topo.subslice_offset = slice_length;
topo.subslice_stride = sseu->ss_stride;
topo.eu_offset = slice_length + subslice_length;
- topo.eu_stride = eu_stride;
+ topo.eu_stride = sseu->eu_stride;
if (__copy_to_user(u64_to_user_ptr(query_item->data_ptr),
&topo, sizeof(topo)))
diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index 77d7bbaa49f3..b1a79ed408eb 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -118,10 +118,9 @@ void intel_device_info_dump_runtime(const struct intel_runtime_info *info,
static int sseu_eu_idx(const struct sseu_dev_info *sseu, int slice,
int subslice)
{
- int subslice_stride = GEN_SSEU_STRIDE(sseu->max_eus_per_subslice);
- int slice_stride = sseu->max_subslices * subslice_stride;
+ int slice_stride = sseu->max_subslices * sseu->eu_stride;
- return slice * slice_stride + subslice * subslice_stride;
+ return slice * slice_stride + subslice * sseu->eu_stride;
}
static u16 sseu_get_eus(const struct sseu_dev_info *sseu, int slice,
@@ -130,7 +129,7 @@ static u16 sseu_get_eus(const struct sseu_dev_info *sseu, int slice,
int i, offset = sseu_eu_idx(sseu, slice, subslice);
u16 eu_mask = 0;
- for (i = 0; i < GEN_SSEU_STRIDE(sseu->max_eus_per_subslice); i++) {
+ for (i = 0; i < sseu->eu_stride; i++) {
eu_mask |= ((u16)sseu->eu_mask[offset + i]) <<
(i * BITS_PER_BYTE);
}
@@ -143,7 +142,7 @@ static void sseu_set_eus(struct sseu_dev_info *sseu, int slice, int subslice,
{
int i, offset = sseu_eu_idx(sseu, slice, subslice);
- for (i = 0; i < GEN_SSEU_STRIDE(sseu->max_eus_per_subslice); i++) {
+ for (i = 0; i < sseu->eu_stride; i++) {
sseu->eu_mask[offset + i] =
(eu_mask >> (BITS_PER_BYTE * i)) & 0xff;
}
--
2.22.0
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [PATCH 05/11] drm/i915: Use local variables for subslice_mask for device info
2019-08-20 23:05 [PATCH 00/11] Refactor to expand subslice mask (rev 2) Stuart Summers
` (3 preceding siblings ...)
2019-08-20 23:05 ` [PATCH 04/11] drm/i915: Add EU " Stuart Summers
@ 2019-08-20 23:05 ` Stuart Summers
2019-08-21 22:31 ` Chris Wilson
2019-08-20 23:05 ` [PATCH 06/11] drm/i915: Add function to set subslices Stuart Summers
` (9 subsequent siblings)
14 siblings, 1 reply; 32+ messages in thread
From: Stuart Summers @ 2019-08-20 23:05 UTC (permalink / raw)
To: intel-gfx
When setting up subslice_mask, instead of operating on the slice
array directly, use a local variable to start bits per slice, then
use this to set the per slice array in one step.
Signed-off-by: Stuart Summers <stuart.summers@intel.com>
---
drivers/gpu/drm/i915/intel_device_info.c | 49 +++++++++++++-----------
1 file changed, 26 insertions(+), 23 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index b1a79ed408eb..52515efe9f4e 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -235,18 +235,6 @@ static void gen10_sseu_info_init(struct drm_i915_private *dev_priv)
sseu->slice_mask = (fuse2 & GEN10_F2_S_ENA_MASK) >>
GEN10_F2_S_ENA_SHIFT;
- subslice_mask = (1 << 4) - 1;
- subslice_mask &= ~((fuse2 & GEN10_F2_SS_DIS_MASK) >>
- GEN10_F2_SS_DIS_SHIFT);
-
- /*
- * Slice0 can have up to 3 subslices, but there are only 2 in
- * slice1/2.
- */
- sseu->subslice_mask[0] = subslice_mask;
- for (s = 1; s < sseu->max_slices; s++)
- sseu->subslice_mask[s] = subslice_mask & 0x3;
-
/* Slice0 */
eu_en = ~I915_READ(GEN8_EU_DISABLE0);
for (ss = 0; ss < sseu->max_subslices; ss++)
@@ -270,14 +258,24 @@ static void gen10_sseu_info_init(struct drm_i915_private *dev_priv)
eu_en = ~I915_READ(GEN10_EU_DISABLE3);
sseu_set_eus(sseu, 5, 1, eu_en & eu_mask);
- /* Do a second pass where we mark the subslices disabled if all their
- * eus are off.
- */
+ subslice_mask = (1 << 4) - 1;
+ subslice_mask &= ~((fuse2 & GEN10_F2_SS_DIS_MASK) >>
+ GEN10_F2_SS_DIS_SHIFT);
+
for (s = 0; s < sseu->max_slices; s++) {
+ u32 subslice_mask_with_eus = subslice_mask;
+
for (ss = 0; ss < sseu->max_subslices; ss++) {
if (sseu_get_eus(sseu, s, ss) == 0)
- sseu->subslice_mask[s] &= ~BIT(ss);
+ subslice_mask_with_eus &= ~BIT(ss);
}
+
+ /*
+ * Slice0 can have up to 3 subslices, but there are only 2 in
+ * slice1/2.
+ */
+ sseu->subslice_mask[s] = s == 0 ? subslice_mask_with_eus :
+ subslice_mask_with_eus & 0x3;
}
sseu->eu_total = compute_eu_total(sseu);
@@ -303,6 +301,7 @@ static void cherryview_sseu_info_init(struct drm_i915_private *dev_priv)
{
struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu;
u32 fuse;
+ u8 subslice_mask = 0;
fuse = I915_READ(CHV_FUSE_GT);
@@ -316,7 +315,7 @@ static void cherryview_sseu_info_init(struct drm_i915_private *dev_priv)
(((fuse & CHV_FGT_EU_DIS_SS0_R1_MASK) >>
CHV_FGT_EU_DIS_SS0_R1_SHIFT) << 4);
- sseu->subslice_mask[0] |= BIT(0);
+ subslice_mask |= BIT(0);
sseu_set_eus(sseu, 0, 0, ~disabled_mask);
}
@@ -327,10 +326,12 @@ static void cherryview_sseu_info_init(struct drm_i915_private *dev_priv)
(((fuse & CHV_FGT_EU_DIS_SS1_R1_MASK) >>
CHV_FGT_EU_DIS_SS1_R1_SHIFT) << 4);
- sseu->subslice_mask[0] |= BIT(1);
+ subslice_mask |= BIT(1);
sseu_set_eus(sseu, 0, 1, ~disabled_mask);
}
+ sseu->subslice_mask[0] = subslice_mask;
+
sseu->eu_total = compute_eu_total(sseu);
/*
@@ -540,6 +541,7 @@ static void haswell_sseu_info_init(struct drm_i915_private *dev_priv)
{
struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu;
u32 fuse1;
+ u8 subslice_mask = 0;
int s, ss;
/*
@@ -552,16 +554,15 @@ static void haswell_sseu_info_init(struct drm_i915_private *dev_priv)
/* fall through */
case 1:
sseu->slice_mask = BIT(0);
- sseu->subslice_mask[0] = BIT(0);
+ subslice_mask = BIT(0);
break;
case 2:
sseu->slice_mask = BIT(0);
- sseu->subslice_mask[0] = BIT(0) | BIT(1);
+ subslice_mask = BIT(0) | BIT(1);
break;
case 3:
sseu->slice_mask = BIT(0) | BIT(1);
- sseu->subslice_mask[0] = BIT(0) | BIT(1);
- sseu->subslice_mask[1] = BIT(0) | BIT(1);
+ subslice_mask = BIT(0) | BIT(1);
break;
}
@@ -583,10 +584,12 @@ static void haswell_sseu_info_init(struct drm_i915_private *dev_priv)
}
intel_sseu_set_info(sseu, hweight8(sseu->slice_mask),
- hweight8(sseu->subslice_mask[0]),
+ hweight8(subslice_mask),
sseu->eu_per_subslice);
for (s = 0; s < sseu->max_slices; s++) {
+ sseu->subslice_mask[s] = subslice_mask;
+
for (ss = 0; ss < sseu->max_subslices; ss++) {
sseu_set_eus(sseu, s, ss,
(1UL << sseu->eu_per_subslice) - 1);
--
2.22.0
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [PATCH 06/11] drm/i915: Add function to set subslices
2019-08-20 23:05 [PATCH 00/11] Refactor to expand subslice mask (rev 2) Stuart Summers
` (4 preceding siblings ...)
2019-08-20 23:05 ` [PATCH 05/11] drm/i915: Use local variables for subslice_mask for device info Stuart Summers
@ 2019-08-20 23:05 ` Stuart Summers
2019-08-21 22:32 ` Chris Wilson
2019-08-20 23:05 ` [PATCH 07/11] drm/i915: Use subslice stride to set subslices for a given slice Stuart Summers
` (8 subsequent siblings)
14 siblings, 1 reply; 32+ messages in thread
From: Stuart Summers @ 2019-08-20 23:05 UTC (permalink / raw)
To: intel-gfx
Add a new function to set a set of subslices for a given
slice.
Signed-off-by: Stuart Summers <stuart.summers@intel.com>
---
drivers/gpu/drm/i915/gt/intel_sseu.c | 6 ++++++
drivers/gpu/drm/i915/gt/intel_sseu.h | 3 +++
drivers/gpu/drm/i915/intel_device_info.c | 18 +++++++++++-------
3 files changed, 20 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.c b/drivers/gpu/drm/i915/gt/intel_sseu.c
index 3a5c0f7b5a08..79a9b5f186f9 100644
--- a/drivers/gpu/drm/i915/gt/intel_sseu.c
+++ b/drivers/gpu/drm/i915/gt/intel_sseu.c
@@ -30,6 +30,12 @@ intel_sseu_subslice_total(const struct sseu_dev_info *sseu)
return total;
}
+void intel_sseu_set_subslices(struct sseu_dev_info *sseu, int slice,
+ u8 ss_mask)
+{
+ sseu->subslice_mask[i] = ss_mask & 0xff;
+}
+
unsigned int
intel_sseu_subslices_per_slice(const struct sseu_dev_info *sseu, u8 slice)
{
diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.h b/drivers/gpu/drm/i915/gt/intel_sseu.h
index fe22d5b18e67..3099e04611ce 100644
--- a/drivers/gpu/drm/i915/gt/intel_sseu.h
+++ b/drivers/gpu/drm/i915/gt/intel_sseu.h
@@ -75,6 +75,9 @@ intel_sseu_subslice_total(const struct sseu_dev_info *sseu);
unsigned int
intel_sseu_subslices_per_slice(const struct sseu_dev_info *sseu, u8 slice);
+void intel_sseu_set_subslices(struct sseu_dev_info *sseu, int slice,
+ u8 ss_mask);
+
u32 intel_sseu_make_rpcs(struct drm_i915_private *i915,
const struct intel_sseu *req_sseu);
diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index 52515efe9f4e..1a45728ac712 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -206,7 +206,10 @@ static void gen11_sseu_info_init(struct drm_i915_private *dev_priv)
int ss;
sseu->slice_mask |= BIT(s);
- sseu->subslice_mask[s] = (ss_en >> ss_idx) & ss_en_mask;
+
+ intel_sseu_set_subslices(sseu, s, (ss_en >> ss_idx) &
+ ss_en_mask);
+
for (ss = 0; ss < sseu->max_subslices; ss++) {
if (sseu->subslice_mask[s] & BIT(ss))
sseu_set_eus(sseu, s, ss, eu_en);
@@ -274,8 +277,9 @@ static void gen10_sseu_info_init(struct drm_i915_private *dev_priv)
* Slice0 can have up to 3 subslices, but there are only 2 in
* slice1/2.
*/
- sseu->subslice_mask[s] = s == 0 ? subslice_mask_with_eus :
- subslice_mask_with_eus & 0x3;
+ intel_sseu_set_subslices(sseu, s, s == 0 ?
+ subslice_mask_with_eus :
+ subslice_mask_with_eus & 0x3);
}
sseu->eu_total = compute_eu_total(sseu);
@@ -330,7 +334,7 @@ static void cherryview_sseu_info_init(struct drm_i915_private *dev_priv)
sseu_set_eus(sseu, 0, 1, ~disabled_mask);
}
- sseu->subslice_mask[0] = subslice_mask;
+ intel_sseu_set_subslices(sseu, 0, subslice_mask);
sseu->eu_total = compute_eu_total(sseu);
@@ -384,7 +388,7 @@ static void gen9_sseu_info_init(struct drm_i915_private *dev_priv)
/* skip disabled slice */
continue;
- sseu->subslice_mask[s] = subslice_mask;
+ intel_sseu_set_subslices(sseu, s, subslice_mask);
eu_disable = I915_READ(GEN9_EU_DISABLE(s));
for (ss = 0; ss < sseu->max_subslices; ss++) {
@@ -491,7 +495,7 @@ static void broadwell_sseu_info_init(struct drm_i915_private *dev_priv)
/* skip disabled slice */
continue;
- sseu->subslice_mask[s] = subslice_mask;
+ intel_sseu_set_subslices(sseu, s, subslice_mask);
for (ss = 0; ss < sseu->max_subslices; ss++) {
u8 eu_disabled_mask;
@@ -588,7 +592,7 @@ static void haswell_sseu_info_init(struct drm_i915_private *dev_priv)
sseu->eu_per_subslice);
for (s = 0; s < sseu->max_slices; s++) {
- sseu->subslice_mask[s] = subslice_mask;
+ intel_sseu_set_subslices(sseu, s, subslice_mask);
for (ss = 0; ss < sseu->max_subslices; ss++) {
sseu_set_eus(sseu, s, ss,
--
2.22.0
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [PATCH 07/11] drm/i915: Use subslice stride to set subslices for a given slice
2019-08-20 23:05 [PATCH 00/11] Refactor to expand subslice mask (rev 2) Stuart Summers
` (5 preceding siblings ...)
2019-08-20 23:05 ` [PATCH 06/11] drm/i915: Add function to set subslices Stuart Summers
@ 2019-08-20 23:05 ` Stuart Summers
2019-08-21 22:36 ` Chris Wilson
2019-08-20 23:05 ` [PATCH 08/11] drm/i915: Add function to determine if a slice has a subslice Stuart Summers
` (7 subsequent siblings)
14 siblings, 1 reply; 32+ messages in thread
From: Stuart Summers @ 2019-08-20 23:05 UTC (permalink / raw)
To: intel-gfx
Add a subslice stride calculation when setting subslices. This
aligns more closely with the userspace expectation of the subslice
mask structure.
v2: Use local variable for subslice_mask on HSW and
clean up a few other subslice_mask local variable
changes
v3: Add GEM_BUG_ON for ss_stride to prevent array overflow (Chris)
Split main set function and refactors in intel_device_info.c
into separate patches (Chris)
Signed-off-by: Stuart Summers <stuart.summers@intel.com>
---
drivers/gpu/drm/i915/gt/intel_sseu.c | 12 ++++++++++--
drivers/gpu/drm/i915/gt/intel_sseu.h | 2 +-
2 files changed, 11 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.c b/drivers/gpu/drm/i915/gt/intel_sseu.c
index 79a9b5f186f9..5d537ec97fcc 100644
--- a/drivers/gpu/drm/i915/gt/intel_sseu.c
+++ b/drivers/gpu/drm/i915/gt/intel_sseu.c
@@ -31,9 +31,17 @@ intel_sseu_subslice_total(const struct sseu_dev_info *sseu)
}
void intel_sseu_set_subslices(struct sseu_dev_info *sseu, int slice,
- u8 ss_mask)
+ u32 ss_mask)
{
- sseu->subslice_mask[i] = ss_mask & 0xff;
+ int i, offset;
+
+ GEM_BUG_ON(sseu->ss_stride > 32);
+
+ offset = slice * sseu->ss_stride;
+
+ for (i = 0; i < sseu->ss_stride; i++)
+ sseu->subslice_mask[offset + i] =
+ (ss_mask >> (BITS_PER_BYTE * i)) & 0xff;
}
unsigned int
diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.h b/drivers/gpu/drm/i915/gt/intel_sseu.h
index 3099e04611ce..2261d4e7d98b 100644
--- a/drivers/gpu/drm/i915/gt/intel_sseu.h
+++ b/drivers/gpu/drm/i915/gt/intel_sseu.h
@@ -76,7 +76,7 @@ unsigned int
intel_sseu_subslices_per_slice(const struct sseu_dev_info *sseu, u8 slice);
void intel_sseu_set_subslices(struct sseu_dev_info *sseu, int slice,
- u8 ss_mask);
+ u32 ss_mask);
u32 intel_sseu_make_rpcs(struct drm_i915_private *i915,
const struct intel_sseu *req_sseu);
--
2.22.0
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [PATCH 08/11] drm/i915: Add function to determine if a slice has a subslice
2019-08-20 23:05 [PATCH 00/11] Refactor to expand subslice mask (rev 2) Stuart Summers
` (6 preceding siblings ...)
2019-08-20 23:05 ` [PATCH 07/11] drm/i915: Use subslice stride to set subslices for a given slice Stuart Summers
@ 2019-08-20 23:05 ` Stuart Summers
2019-08-20 23:05 ` [PATCH 09/11] drm/i915: Refactor instdone loops on new subslice functions Stuart Summers
` (6 subsequent siblings)
14 siblings, 0 replies; 32+ messages in thread
From: Stuart Summers @ 2019-08-20 23:05 UTC (permalink / raw)
To: intel-gfx
Add a new function to determine whether a particular slice
has a given subslice.
Signed-off-by: Stuart Summers <stuart.summers@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
---
drivers/gpu/drm/i915/gt/intel_sseu.h | 16 ++++++++++++++++
drivers/gpu/drm/i915/intel_device_info.c | 9 ++++-----
2 files changed, 20 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.h b/drivers/gpu/drm/i915/gt/intel_sseu.h
index 2261d4e7d98b..3a146a33a22e 100644
--- a/drivers/gpu/drm/i915/gt/intel_sseu.h
+++ b/drivers/gpu/drm/i915/gt/intel_sseu.h
@@ -10,6 +10,8 @@
#include <linux/types.h>
#include <linux/kernel.h>
+#include "i915_gem.h"
+
struct drm_i915_private;
#define GEN_MAX_SLICES (6) /* CNL upper bound */
@@ -66,6 +68,20 @@ intel_sseu_from_device_info(const struct sseu_dev_info *sseu)
return value;
}
+static inline bool
+intel_sseu_has_subslice(const struct sseu_dev_info *sseu, int slice,
+ int subslice)
+{
+ u8 mask;
+ int ss_idx = subslice / BITS_PER_BYTE;
+
+ GEM_BUG_ON(ss_idx >= sseu->ss_stride);
+
+ mask = sseu->subslice_mask[slice * sseu->ss_stride + ss_idx];
+
+ return mask & BIT(subslice % BITS_PER_BYTE);
+}
+
void intel_sseu_set_info(struct sseu_dev_info *sseu, u8 max_slices,
u8 max_subslices, u8 max_eus_per_subslice);
diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index 1a45728ac712..c20f74ee5f22 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -210,10 +210,9 @@ static void gen11_sseu_info_init(struct drm_i915_private *dev_priv)
intel_sseu_set_subslices(sseu, s, (ss_en >> ss_idx) &
ss_en_mask);
- for (ss = 0; ss < sseu->max_subslices; ss++) {
- if (sseu->subslice_mask[s] & BIT(ss))
+ for (ss = 0; ss < sseu->max_subslices; ss++)
+ if (intel_sseu_has_subslice(sseu, s, ss))
sseu_set_eus(sseu, s, ss, eu_en);
- }
}
}
sseu->eu_per_subslice = hweight8(eu_en);
@@ -395,7 +394,7 @@ static void gen9_sseu_info_init(struct drm_i915_private *dev_priv)
int eu_per_ss;
u8 eu_disabled_mask;
- if (!(sseu->subslice_mask[s] & BIT(ss)))
+ if (!intel_sseu_has_subslice(sseu, s, ss))
/* skip disabled subslice */
continue;
@@ -501,7 +500,7 @@ static void broadwell_sseu_info_init(struct drm_i915_private *dev_priv)
u8 eu_disabled_mask;
u32 n_disabled;
- if (!(sseu->subslice_mask[s] & BIT(ss)))
+ if (!intel_sseu_has_subslice(sseu, s, ss))
/* skip disabled subslice */
continue;
--
2.22.0
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [PATCH 09/11] drm/i915: Refactor instdone loops on new subslice functions
2019-08-20 23:05 [PATCH 00/11] Refactor to expand subslice mask (rev 2) Stuart Summers
` (7 preceding siblings ...)
2019-08-20 23:05 ` [PATCH 08/11] drm/i915: Add function to determine if a slice has a subslice Stuart Summers
@ 2019-08-20 23:05 ` Stuart Summers
2019-08-21 22:56 ` Chris Wilson
2019-08-20 23:05 ` [PATCH 10/11] drm/i915: Add new function to copy subslices for a slice Stuart Summers
` (5 subsequent siblings)
14 siblings, 1 reply; 32+ messages in thread
From: Stuart Summers @ 2019-08-20 23:05 UTC (permalink / raw)
To: intel-gfx
Refactor instdone loops to use the new intel_sseu_has_subslice
function.
Signed-off-by: Stuart Summers <stuart.summers@intel.com>
---
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 3 +-
drivers/gpu/drm/i915/gt/intel_engine_types.h | 31 ++++++++++----------
drivers/gpu/drm/i915/gt/intel_hangcheck.c | 3 +-
drivers/gpu/drm/i915/i915_debugfs.c | 5 ++--
drivers/gpu/drm/i915/i915_gpu_error.c | 5 ++--
5 files changed, 25 insertions(+), 22 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index 82630db0394b..17006d50b63f 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -948,6 +948,7 @@ void intel_engine_get_instdone(struct intel_engine_cs *engine,
struct intel_instdone *instdone)
{
struct drm_i915_private *i915 = engine->i915;
+ const struct sseu_dev_info *sseu = &RUNTIME_INFO(i915)->sseu;
struct intel_uncore *uncore = engine->uncore;
u32 mmio_base = engine->mmio_base;
int slice;
@@ -965,7 +966,7 @@ void intel_engine_get_instdone(struct intel_engine_cs *engine,
instdone->slice_common =
intel_uncore_read(uncore, GEN7_SC_INSTDONE);
- for_each_instdone_slice_subslice(i915, slice, subslice) {
+ for_each_instdone_slice_subslice(i915, sseu, slice, subslice) {
instdone->sampler[slice][subslice] =
read_subslice_reg(engine, slice, subslice,
GEN7_SAMPLER_INSTDONE);
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h b/drivers/gpu/drm/i915/gt/intel_engine_types.h
index a82cea95c2f2..99bee06cdbdb 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h
@@ -576,20 +576,19 @@ intel_engine_is_virtual(const struct intel_engine_cs *engine)
return engine->flags & I915_ENGINE_IS_VIRTUAL;
}
-#define instdone_slice_mask(dev_priv__) \
- (IS_GEN(dev_priv__, 7) ? \
- 1 : RUNTIME_INFO(dev_priv__)->sseu.slice_mask)
-
-#define instdone_subslice_mask(dev_priv__) \
- (IS_GEN(dev_priv__, 7) ? \
- 1 : RUNTIME_INFO(dev_priv__)->sseu.subslice_mask[0])
-
-#define for_each_instdone_slice_subslice(dev_priv__, slice__, subslice__) \
- for ((slice__) = 0, (subslice__) = 0; \
- (slice__) < I915_MAX_SLICES; \
- (subslice__) = ((subslice__) + 1) < I915_MAX_SUBSLICES ? (subslice__) + 1 : 0, \
- (slice__) += ((subslice__) == 0)) \
- for_each_if((BIT(slice__) & instdone_slice_mask(dev_priv__)) && \
- (BIT(subslice__) & instdone_subslice_mask(dev_priv__)))
-
+#define instdone_has_slice(dev_priv___, sseu___, slice___) \
+ ((IS_GEN(dev_priv___, 7) ? 1 : ((sseu___)->slice_mask)) & \
+ BIT(slice___))
+
+#define instdone_has_subslice(dev_priv__, sseu__, slice__, subslice__) \
+ (IS_GEN(dev_priv__, 7) ? (1 & BIT(subslice__)) : \
+ intel_sseu_has_subslice(sseu__, 0, subslice__))
+
+#define for_each_instdone_slice_subslice(dev_priv_, sseu_, slice_, subslice_) \
+ for ((slice_) = 0, (subslice_) = 0; (slice_) < I915_MAX_SLICES; \
+ (subslice_) = ((subslice_) + 1) % I915_MAX_SUBSLICES, \
+ (slice_) += ((subslice_) == 0)) \
+ for_each_if((instdone_has_slice(dev_priv_, sseu_, slice_)) && \
+ (instdone_has_subslice(dev_priv_, sseu_, slice_, \
+ subslice_)))
#endif /* __INTEL_ENGINE_TYPES_H__ */
diff --git a/drivers/gpu/drm/i915/gt/intel_hangcheck.c b/drivers/gpu/drm/i915/gt/intel_hangcheck.c
index 05d042cdefe2..40f62f780be5 100644
--- a/drivers/gpu/drm/i915/gt/intel_hangcheck.c
+++ b/drivers/gpu/drm/i915/gt/intel_hangcheck.c
@@ -53,6 +53,7 @@ static bool instdone_unchanged(u32 current_instdone, u32 *old_instdone)
static bool subunits_stuck(struct intel_engine_cs *engine)
{
struct drm_i915_private *dev_priv = engine->i915;
+ const struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu;
struct intel_instdone instdone;
struct intel_instdone *accu_instdone = &engine->hangcheck.instdone;
bool stuck;
@@ -71,7 +72,7 @@ static bool subunits_stuck(struct intel_engine_cs *engine)
stuck &= instdone_unchanged(instdone.slice_common,
&accu_instdone->slice_common);
- for_each_instdone_slice_subslice(dev_priv, slice, subslice) {
+ for_each_instdone_slice_subslice(dev_priv, sseu, slice, subslice) {
stuck &= instdone_unchanged(instdone.sampler[slice][subslice],
&accu_instdone->sampler[slice][subslice]);
stuck &= instdone_unchanged(instdone.row[slice][subslice],
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index abf0f6ba213c..8c5eca72ff5e 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -995,6 +995,7 @@ static void i915_instdone_info(struct drm_i915_private *dev_priv,
struct seq_file *m,
struct intel_instdone *instdone)
{
+ const struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu;
int slice;
int subslice;
@@ -1010,11 +1011,11 @@ static void i915_instdone_info(struct drm_i915_private *dev_priv,
if (INTEL_GEN(dev_priv) <= 6)
return;
- for_each_instdone_slice_subslice(dev_priv, slice, subslice)
+ for_each_instdone_slice_subslice(dev_priv, sseu, slice, subslice)
seq_printf(m, "\t\tSAMPLER_INSTDONE[%d][%d]: 0x%08x\n",
slice, subslice, instdone->sampler[slice][subslice]);
- for_each_instdone_slice_subslice(dev_priv, slice, subslice)
+ for_each_instdone_slice_subslice(dev_priv, sseu, slice, subslice)
seq_printf(m, "\t\tROW_INSTDONE[%d][%d]: 0x%08x\n",
slice, subslice, instdone->row[slice][subslice]);
}
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c
index e284bd76fa86..4aff342b8944 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -421,6 +421,7 @@ static void err_compression_marker(struct drm_i915_error_state_buf *m)
static void error_print_instdone(struct drm_i915_error_state_buf *m,
const struct drm_i915_error_engine *ee)
{
+ const struct sseu_dev_info *sseu = &RUNTIME_INFO(m->i915)->sseu;
int slice;
int subslice;
@@ -436,12 +437,12 @@ static void error_print_instdone(struct drm_i915_error_state_buf *m,
if (INTEL_GEN(m->i915) <= 6)
return;
- for_each_instdone_slice_subslice(m->i915, slice, subslice)
+ for_each_instdone_slice_subslice(m->i915, sseu, slice, subslice)
err_printf(m, " SAMPLER_INSTDONE[%d][%d]: 0x%08x\n",
slice, subslice,
ee->instdone.sampler[slice][subslice]);
- for_each_instdone_slice_subslice(m->i915, slice, subslice)
+ for_each_instdone_slice_subslice(m->i915, sseu, slice, subslice)
err_printf(m, " ROW_INSTDONE[%d][%d]: 0x%08x\n",
slice, subslice,
ee->instdone.row[slice][subslice]);
--
2.22.0
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [PATCH 10/11] drm/i915: Add new function to copy subslices for a slice
2019-08-20 23:05 [PATCH 00/11] Refactor to expand subslice mask (rev 2) Stuart Summers
` (8 preceding siblings ...)
2019-08-20 23:05 ` [PATCH 09/11] drm/i915: Refactor instdone loops on new subslice functions Stuart Summers
@ 2019-08-20 23:05 ` Stuart Summers
2019-08-21 22:41 ` Chris Wilson
2019-08-20 23:05 ` [PATCH 11/11] drm/i915: Expand subslice mask Stuart Summers
` (4 subsequent siblings)
14 siblings, 1 reply; 32+ messages in thread
From: Stuart Summers @ 2019-08-20 23:05 UTC (permalink / raw)
To: intel-gfx
Add a new function to copy subslices for a specified slice
between intel_sseu structures for the purpose of determining
power-gate status.
Signed-off-by: Stuart Summers <stuart.summers@intel.com>
---
drivers/gpu/drm/i915/i915_debugfs.c | 17 ++++++++++++++---
1 file changed, 14 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 8c5eca72ff5e..e975cad03e39 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -3721,6 +3721,15 @@ i915_cache_sharing_set(void *data, u64 val)
return 0;
}
+static void
+intel_sseu_copy_subslices(const struct sseu_dev_info *sseu, int slice,
+ u8 *to_mask)
+{
+ int offset = slice * sseu->ss_stride;
+
+ memcpy(&to_mask[offset], &sseu->subslice_mask[offset], sseu->ss_stride);
+}
+
DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops,
i915_cache_sharing_get, i915_cache_sharing_set,
"%llu\n");
@@ -3794,7 +3803,7 @@ static void gen10_sseu_device_status(struct drm_i915_private *dev_priv,
continue;
sseu->slice_mask |= BIT(s);
- sseu->subslice_mask[s] = info->sseu.subslice_mask[s];
+ intel_sseu_copy_subslices(&info->sseu, s, sseu->subslice_mask);
for (ss = 0; ss < info->sseu.max_subslices; ss++) {
unsigned int eu_cnt;
@@ -3845,7 +3854,8 @@ static void gen9_sseu_device_status(struct drm_i915_private *dev_priv,
sseu->slice_mask |= BIT(s);
if (IS_GEN9_BC(dev_priv))
- sseu->subslice_mask[s] = info->sseu.subslice_mask[s];
+ intel_sseu_copy_subslices(&info->sseu, s,
+ sseu->subslice_mask);
for (ss = 0; ss < info->sseu.max_subslices; ss++) {
unsigned int eu_cnt;
@@ -3881,7 +3891,8 @@ static void broadwell_sseu_device_status(struct drm_i915_private *dev_priv,
if (sseu->slice_mask) {
sseu->eu_per_subslice = info->sseu.eu_per_subslice;
for (s = 0; s < fls(sseu->slice_mask); s++)
- sseu->subslice_mask[s] = info->sseu.subslice_mask[s];
+ intel_sseu_copy_subslices(&info->sseu, s,
+ sseu->subslice_mask);
sseu->eu_total = sseu->eu_per_subslice *
intel_sseu_subslice_total(sseu);
--
2.22.0
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [PATCH 11/11] drm/i915: Expand subslice mask
2019-08-20 23:05 [PATCH 00/11] Refactor to expand subslice mask (rev 2) Stuart Summers
` (9 preceding siblings ...)
2019-08-20 23:05 ` [PATCH 10/11] drm/i915: Add new function to copy subslices for a slice Stuart Summers
@ 2019-08-20 23:05 ` Stuart Summers
2019-08-21 22:49 ` Chris Wilson
2019-08-20 23:59 ` ✗ Fi.CI.CHECKPATCH: warning for Refactor to expand subslice mask (rev 2) Patchwork
` (3 subsequent siblings)
14 siblings, 1 reply; 32+ messages in thread
From: Stuart Summers @ 2019-08-20 23:05 UTC (permalink / raw)
To: intel-gfx
Currently, the subslice_mask runtime parameter is stored as an
array of subslices per slice. Expand the subslice mask array to
better match what is presented to userspace through the
I915_QUERY_TOPOLOGY_INFO ioctl. The index into this array is
then calculated:
slice * subslice stride + subslice index / 8
v2: Fix 32-bit build
v3: Use new helper function in SSEU workaround warning message
Signed-off-by: Stuart Summers <stuart.summers@intel.com>
---
drivers/gpu/drm/i915/gt/intel_sseu.c | 27 ++++++++++++++++++++-
drivers/gpu/drm/i915/gt/intel_sseu.h | 5 +++-
drivers/gpu/drm/i915/gt/intel_workarounds.c | 5 ++--
drivers/gpu/drm/i915/i915_debugfs.c | 5 +++-
drivers/gpu/drm/i915/intel_device_info.c | 8 +++---
5 files changed, 40 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.c b/drivers/gpu/drm/i915/gt/intel_sseu.c
index 5d537ec97fcc..eae1c7b20688 100644
--- a/drivers/gpu/drm/i915/gt/intel_sseu.c
+++ b/drivers/gpu/drm/i915/gt/intel_sseu.c
@@ -30,6 +30,31 @@ intel_sseu_subslice_total(const struct sseu_dev_info *sseu)
return total;
}
+u32 intel_sseu_get_subslices(const struct sseu_dev_info *sseu, u8 slice)
+{
+ int i, offset = slice * sseu->ss_stride;
+ u32 mask = 0;
+
+ if (slice >= sseu->max_slices) {
+ DRM_ERROR("%s: invalid slice %d, max: %d\n",
+ __func__, slice, sseu->max_slices);
+ return 0;
+ }
+
+ if (sseu->ss_stride > sizeof(mask)) {
+ DRM_ERROR("%s: invalid subslice stride %d, max: %u\n",
+ __func__, sseu->ss_stride,
+ (unsigned int)sizeof(mask));
+ return 0;
+ }
+
+ for (i = 0; i < sseu->ss_stride; i++)
+ mask |= (u32)sseu->subslice_mask[offset + i] <<
+ i * BITS_PER_BYTE;
+
+ return mask;
+}
+
void intel_sseu_set_subslices(struct sseu_dev_info *sseu, int slice,
u32 ss_mask)
{
@@ -47,7 +72,7 @@ void intel_sseu_set_subslices(struct sseu_dev_info *sseu, int slice,
unsigned int
intel_sseu_subslices_per_slice(const struct sseu_dev_info *sseu, u8 slice)
{
- return hweight8(sseu->subslice_mask[slice]);
+ return hweight32(intel_sseu_get_subslices(sseu, slice));
}
u32 intel_sseu_make_rpcs(struct drm_i915_private *i915,
diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.h b/drivers/gpu/drm/i915/gt/intel_sseu.h
index 3a146a33a22e..edf77f07ffb3 100644
--- a/drivers/gpu/drm/i915/gt/intel_sseu.h
+++ b/drivers/gpu/drm/i915/gt/intel_sseu.h
@@ -17,10 +17,11 @@ struct drm_i915_private;
#define GEN_MAX_SLICES (6) /* CNL upper bound */
#define GEN_MAX_SUBSLICES (8) /* ICL upper bound */
#define GEN_SSEU_STRIDE(max_entries) DIV_ROUND_UP(max_entries, BITS_PER_BYTE)
+#define GEN_MAX_SUBSLICE_STRIDE GEN_SSEU_STRIDE(GEN_MAX_SUBSLICES)
struct sseu_dev_info {
u8 slice_mask;
- u8 subslice_mask[GEN_MAX_SLICES];
+ u8 subslice_mask[GEN_MAX_SLICES * GEN_MAX_SUBSLICE_STRIDE];
u16 eu_total;
u8 eu_per_subslice;
u8 min_eu_in_pool;
@@ -91,6 +92,8 @@ intel_sseu_subslice_total(const struct sseu_dev_info *sseu);
unsigned int
intel_sseu_subslices_per_slice(const struct sseu_dev_info *sseu, u8 slice);
+u32 intel_sseu_get_subslices(const struct sseu_dev_info *sseu, u8 slice);
+
void intel_sseu_set_subslices(struct sseu_dev_info *sseu, int slice,
u32 ss_mask);
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 126ab3667919..ad2261e0cba8 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -801,11 +801,10 @@ wa_init_mcr(struct drm_i915_private *i915, struct i915_wa_list *wal)
}
slice = fls(sseu->slice_mask) - 1;
- GEM_BUG_ON(slice >= ARRAY_SIZE(sseu->subslice_mask));
- subslice = fls(l3_en & sseu->subslice_mask[slice]);
+ subslice = fls(l3_en & intel_sseu_get_subslices(sseu, slice));
if (!subslice) {
DRM_WARN("No common index found between subslice mask %x and L3 bank mask %x!\n",
- sseu->subslice_mask[slice], l3_en);
+ intel_sseu_get_subslices(sseu, slice), l3_en);
subslice = fls(l3_en);
WARN_ON(!subslice);
}
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index e975cad03e39..112c8a305971 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -3859,13 +3859,16 @@ static void gen9_sseu_device_status(struct drm_i915_private *dev_priv,
for (ss = 0; ss < info->sseu.max_subslices; ss++) {
unsigned int eu_cnt;
+ u8 ss_idx = s * info->sseu.ss_stride +
+ ss / BITS_PER_BYTE;
if (IS_GEN9_LP(dev_priv)) {
if (!(s_reg[s] & (GEN9_PGCTL_SS_ACK(ss))))
/* skip disabled subslice */
continue;
- sseu->subslice_mask[s] |= BIT(ss);
+ sseu->subslice_mask[ss_idx] |=
+ BIT(ss % BITS_PER_BYTE);
}
eu_cnt = 2 * hweight32(eu_reg[2*s + ss/2] &
diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index c20f74ee5f22..d9b5baaef5d0 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -93,9 +93,9 @@ static void sseu_dump(const struct sseu_dev_info *sseu, struct drm_printer *p)
hweight8(sseu->slice_mask), sseu->slice_mask);
drm_printf(p, "subslice total: %u\n", intel_sseu_subslice_total(sseu));
for (s = 0; s < sseu->max_slices; s++) {
- drm_printf(p, "slice%d: %u subslices, mask=%04x\n",
+ drm_printf(p, "slice%d: %u subslices, mask=%08x\n",
s, intel_sseu_subslices_per_slice(sseu, s),
- sseu->subslice_mask[s]);
+ intel_sseu_get_subslices(sseu, s));
}
drm_printf(p, "EU total: %u\n", sseu->eu_total);
drm_printf(p, "EU per subslice: %u\n", sseu->eu_per_subslice);
@@ -159,9 +159,9 @@ void intel_device_info_dump_topology(const struct sseu_dev_info *sseu,
}
for (s = 0; s < sseu->max_slices; s++) {
- drm_printf(p, "slice%d: %u subslice(s) (0x%hhx):\n",
+ drm_printf(p, "slice%d: %u subslice(s) (0x%08x):\n",
s, intel_sseu_subslices_per_slice(sseu, s),
- sseu->subslice_mask[s]);
+ intel_sseu_get_subslices(sseu, s));
for (ss = 0; ss < sseu->max_subslices; ss++) {
u16 enabled_eus = sseu_get_eus(sseu, s, ss);
--
2.22.0
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 32+ messages in thread
* ✗ Fi.CI.CHECKPATCH: warning for Refactor to expand subslice mask (rev 2)
2019-08-20 23:05 [PATCH 00/11] Refactor to expand subslice mask (rev 2) Stuart Summers
` (10 preceding siblings ...)
2019-08-20 23:05 ` [PATCH 11/11] drm/i915: Expand subslice mask Stuart Summers
@ 2019-08-20 23:59 ` Patchwork
2019-08-21 0:02 ` ✗ Fi.CI.SPARSE: " Patchwork
` (2 subsequent siblings)
14 siblings, 0 replies; 32+ messages in thread
From: Patchwork @ 2019-08-20 23:59 UTC (permalink / raw)
To: Summers, Stuart; +Cc: intel-gfx
== Series Details ==
Series: Refactor to expand subslice mask (rev 2)
URL : https://patchwork.freedesktop.org/series/65509/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
f87889b5f343 drm/i915: Use variable for debugfs device status
c0f971db0755 drm/i915: Add function to set SSEU info per platform
9643e69d50cb drm/i915: Add subslice stride runtime parameter
2c816f59af0c drm/i915: Add EU stride runtime parameter
9dc275ae6383 drm/i915: Use local variables for subslice_mask for device info
82d66cf37071 drm/i915: Add function to set subslices
3f42b57ebeb7 drm/i915: Use subslice stride to set subslices for a given slice
e8185bff8829 drm/i915: Add function to determine if a slice has a subslice
a8484fd14a66 drm/i915: Refactor instdone loops on new subslice functions
-:60: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'subslice__' - possible side-effects?
#60: FILE: drivers/gpu/drm/i915/gt/intel_engine_types.h:583:
+#define instdone_has_subslice(dev_priv__, sseu__, slice__, subslice__) \
+ (IS_GEN(dev_priv__, 7) ? (1 & BIT(subslice__)) : \
+ intel_sseu_has_subslice(sseu__, 0, subslice__))
-:64: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'dev_priv_' - possible side-effects?
#64: FILE: drivers/gpu/drm/i915/gt/intel_engine_types.h:587:
+#define for_each_instdone_slice_subslice(dev_priv_, sseu_, slice_, subslice_) \
+ for ((slice_) = 0, (subslice_) = 0; (slice_) < I915_MAX_SLICES; \
+ (subslice_) = ((subslice_) + 1) % I915_MAX_SUBSLICES, \
+ (slice_) += ((subslice_) == 0)) \
+ for_each_if((instdone_has_slice(dev_priv_, sseu_, slice_)) && \
+ (instdone_has_subslice(dev_priv_, sseu_, slice_, \
+ subslice_)))
-:64: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'sseu_' - possible side-effects?
#64: FILE: drivers/gpu/drm/i915/gt/intel_engine_types.h:587:
+#define for_each_instdone_slice_subslice(dev_priv_, sseu_, slice_, subslice_) \
+ for ((slice_) = 0, (subslice_) = 0; (slice_) < I915_MAX_SLICES; \
+ (subslice_) = ((subslice_) + 1) % I915_MAX_SUBSLICES, \
+ (slice_) += ((subslice_) == 0)) \
+ for_each_if((instdone_has_slice(dev_priv_, sseu_, slice_)) && \
+ (instdone_has_subslice(dev_priv_, sseu_, slice_, \
+ subslice_)))
-:64: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'slice_' - possible side-effects?
#64: FILE: drivers/gpu/drm/i915/gt/intel_engine_types.h:587:
+#define for_each_instdone_slice_subslice(dev_priv_, sseu_, slice_, subslice_) \
+ for ((slice_) = 0, (subslice_) = 0; (slice_) < I915_MAX_SLICES; \
+ (subslice_) = ((subslice_) + 1) % I915_MAX_SUBSLICES, \
+ (slice_) += ((subslice_) == 0)) \
+ for_each_if((instdone_has_slice(dev_priv_, sseu_, slice_)) && \
+ (instdone_has_subslice(dev_priv_, sseu_, slice_, \
+ subslice_)))
-:64: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'subslice_' - possible side-effects?
#64: FILE: drivers/gpu/drm/i915/gt/intel_engine_types.h:587:
+#define for_each_instdone_slice_subslice(dev_priv_, sseu_, slice_, subslice_) \
+ for ((slice_) = 0, (subslice_) = 0; (slice_) < I915_MAX_SLICES; \
+ (subslice_) = ((subslice_) + 1) % I915_MAX_SUBSLICES, \
+ (slice_) += ((subslice_) == 0)) \
+ for_each_if((instdone_has_slice(dev_priv_, sseu_, slice_)) && \
+ (instdone_has_subslice(dev_priv_, sseu_, slice_, \
+ subslice_)))
total: 0 errors, 0 warnings, 5 checks, 106 lines checked
abc23c9fc169 drm/i915: Add new function to copy subslices for a slice
771aa4749697 drm/i915: Expand subslice mask
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 32+ messages in thread
* ✗ Fi.CI.SPARSE: warning for Refactor to expand subslice mask (rev 2)
2019-08-20 23:05 [PATCH 00/11] Refactor to expand subslice mask (rev 2) Stuart Summers
` (11 preceding siblings ...)
2019-08-20 23:59 ` ✗ Fi.CI.CHECKPATCH: warning for Refactor to expand subslice mask (rev 2) Patchwork
@ 2019-08-21 0:02 ` Patchwork
2019-08-21 0:20 ` ✓ Fi.CI.BAT: success " Patchwork
2019-08-21 15:15 ` ✓ Fi.CI.IGT: " Patchwork
14 siblings, 0 replies; 32+ messages in thread
From: Patchwork @ 2019-08-21 0:02 UTC (permalink / raw)
To: Summers, Stuart; +Cc: intel-gfx
== Series Details ==
Series: Refactor to expand subslice mask (rev 2)
URL : https://patchwork.freedesktop.org/series/65509/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.6.0
Commit: drm/i915: Use variable for debugfs device status
Okay!
Commit: drm/i915: Add function to set SSEU info per platform
Okay!
Commit: drm/i915: Add subslice stride runtime parameter
Okay!
Commit: drm/i915: Add EU stride runtime parameter
Okay!
Commit: drm/i915: Use local variables for subslice_mask for device info
Okay!
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 32+ messages in thread
* ✓ Fi.CI.BAT: success for Refactor to expand subslice mask (rev 2)
2019-08-20 23:05 [PATCH 00/11] Refactor to expand subslice mask (rev 2) Stuart Summers
` (12 preceding siblings ...)
2019-08-21 0:02 ` ✗ Fi.CI.SPARSE: " Patchwork
@ 2019-08-21 0:20 ` Patchwork
2019-08-21 15:15 ` ✓ Fi.CI.IGT: " Patchwork
14 siblings, 0 replies; 32+ messages in thread
From: Patchwork @ 2019-08-21 0:20 UTC (permalink / raw)
To: Summers, Stuart; +Cc: intel-gfx
== Series Details ==
Series: Refactor to expand subslice mask (rev 2)
URL : https://patchwork.freedesktop.org/series/65509/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6750 -> Patchwork_14114
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14114/
Known issues
------------
Here are the changes found in Patchwork_14114 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_ctx_switch@legacy-render:
- fi-bxt-dsi: [PASS][1] -> [INCOMPLETE][2] ([fdo#103927])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6750/fi-bxt-dsi/igt@gem_ctx_switch@legacy-render.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14114/fi-bxt-dsi/igt@gem_ctx_switch@legacy-render.html
- fi-icl-u3: [PASS][3] -> [INCOMPLETE][4] ([fdo#107713])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6750/fi-icl-u3/igt@gem_ctx_switch@legacy-render.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14114/fi-icl-u3/igt@gem_ctx_switch@legacy-render.html
* igt@kms_chamelium@common-hpd-after-suspend:
- fi-cml-u2: [PASS][5] -> [DMESG-WARN][6] ([fdo#102505])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6750/fi-cml-u2/igt@kms_chamelium@common-hpd-after-suspend.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14114/fi-cml-u2/igt@kms_chamelium@common-hpd-after-suspend.html
#### Possible fixes ####
* igt@i915_selftest@live_reset:
- fi-icl-u2: [INCOMPLETE][7] ([fdo#107713]) -> [PASS][8]
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6750/fi-icl-u2/igt@i915_selftest@live_reset.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14114/fi-icl-u2/igt@i915_selftest@live_reset.html
* igt@kms_frontbuffer_tracking@basic:
- fi-icl-u2: [FAIL][9] ([fdo#103167]) -> [PASS][10]
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6750/fi-icl-u2/igt@kms_frontbuffer_tracking@basic.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14114/fi-icl-u2/igt@kms_frontbuffer_tracking@basic.html
[fdo#102505]: https://bugs.freedesktop.org/show_bug.cgi?id=102505
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
Participating hosts (50 -> 42)
------------------------------
Additional (2): fi-skl-guc fi-pnv-d510
Missing (10): fi-kbl-soraka fi-ilk-m540 fi-icl-u4 fi-hsw-4200u fi-glk-dsi fi-byt-squawks fi-bsw-cyan fi-icl-y fi-byt-clapper fi-bdw-samus
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_6750 -> Patchwork_14114
CI-20190529: 20190529
CI_DRM_6750: ba37f74dbdc1e78e70a5a2e5f4ce8d762d06eaa7 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5146: 357dbe1869d88a2f08bcee4eebceff4ee9014424 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_14114: 771aa4749697794e7898522473b266d9a85352f9 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
771aa4749697 drm/i915: Expand subslice mask
abc23c9fc169 drm/i915: Add new function to copy subslices for a slice
a8484fd14a66 drm/i915: Refactor instdone loops on new subslice functions
e8185bff8829 drm/i915: Add function to determine if a slice has a subslice
3f42b57ebeb7 drm/i915: Use subslice stride to set subslices for a given slice
82d66cf37071 drm/i915: Add function to set subslices
9dc275ae6383 drm/i915: Use local variables for subslice_mask for device info
2c816f59af0c drm/i915: Add EU stride runtime parameter
9643e69d50cb drm/i915: Add subslice stride runtime parameter
c0f971db0755 drm/i915: Add function to set SSEU info per platform
f87889b5f343 drm/i915: Use variable for debugfs device status
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14114/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 32+ messages in thread
* ✓ Fi.CI.IGT: success for Refactor to expand subslice mask (rev 2)
2019-08-20 23:05 [PATCH 00/11] Refactor to expand subslice mask (rev 2) Stuart Summers
` (13 preceding siblings ...)
2019-08-21 0:20 ` ✓ Fi.CI.BAT: success " Patchwork
@ 2019-08-21 15:15 ` Patchwork
14 siblings, 0 replies; 32+ messages in thread
From: Patchwork @ 2019-08-21 15:15 UTC (permalink / raw)
To: Summers, Stuart; +Cc: intel-gfx
== Series Details ==
Series: Refactor to expand subslice mask (rev 2)
URL : https://patchwork.freedesktop.org/series/65509/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6750_full -> Patchwork_14114_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Known issues
------------
Here are the changes found in Patchwork_14114_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_ctx_shared@exec-single-timeline-bsd:
- shard-iclb: [PASS][1] -> [SKIP][2] ([fdo#110841])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6750/shard-iclb8/igt@gem_ctx_shared@exec-single-timeline-bsd.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14114/shard-iclb4/igt@gem_ctx_shared@exec-single-timeline-bsd.html
* igt@gem_exec_schedule@preempt-hang-bsd:
- shard-iclb: [PASS][3] -> [SKIP][4] ([fdo#111325]) +1 similar issue
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6750/shard-iclb8/igt@gem_exec_schedule@preempt-hang-bsd.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14114/shard-iclb1/igt@gem_exec_schedule@preempt-hang-bsd.html
* igt@i915_suspend@fence-restore-tiled2untiled:
- shard-apl: [PASS][5] -> [DMESG-WARN][6] ([fdo#108566]) +8 similar issues
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6750/shard-apl5/igt@i915_suspend@fence-restore-tiled2untiled.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14114/shard-apl2/igt@i915_suspend@fence-restore-tiled2untiled.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size:
- shard-skl: [PASS][7] -> [FAIL][8] ([fdo#102670])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6750/shard-skl10/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14114/shard-skl3/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible:
- shard-skl: [PASS][9] -> [FAIL][10] ([fdo#105363])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6750/shard-skl6/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14114/shard-skl10/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
- shard-glk: [PASS][11] -> [FAIL][12] ([fdo#105363])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6750/shard-glk9/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14114/shard-glk4/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-pwrite:
- shard-iclb: [PASS][13] -> [FAIL][14] ([fdo#103167]) +5 similar issues
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6750/shard-iclb8/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-pwrite.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14114/shard-iclb4/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-pwrite.html
* igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes:
- shard-skl: [PASS][15] -> [INCOMPLETE][16] ([fdo#104108])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6750/shard-skl3/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14114/shard-skl1/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html
* igt@kms_plane_lowres@pipe-a-tiling-y:
- shard-iclb: [PASS][17] -> [FAIL][18] ([fdo#103166])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6750/shard-iclb3/igt@kms_plane_lowres@pipe-a-tiling-y.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14114/shard-iclb7/igt@kms_plane_lowres@pipe-a-tiling-y.html
* igt@kms_psr2_su@frontbuffer:
- shard-iclb: [PASS][19] -> [SKIP][20] ([fdo#109642] / [fdo#111068])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6750/shard-iclb2/igt@kms_psr2_su@frontbuffer.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14114/shard-iclb8/igt@kms_psr2_su@frontbuffer.html
* igt@kms_psr@psr2_cursor_mmap_cpu:
- shard-iclb: [PASS][21] -> [SKIP][22] ([fdo#109441]) +3 similar issues
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6750/shard-iclb2/igt@kms_psr@psr2_cursor_mmap_cpu.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14114/shard-iclb8/igt@kms_psr@psr2_cursor_mmap_cpu.html
* igt@prime_busy@hang-bsd2:
- shard-iclb: [PASS][23] -> [SKIP][24] ([fdo#109276]) +15 similar issues
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6750/shard-iclb4/igt@prime_busy@hang-bsd2.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14114/shard-iclb7/igt@prime_busy@hang-bsd2.html
* igt@syncobj_wait@wait-any-snapshot:
- shard-apl: [PASS][25] -> [INCOMPLETE][26] ([fdo#103927]) +1 similar issue
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6750/shard-apl6/igt@syncobj_wait@wait-any-snapshot.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14114/shard-apl1/igt@syncobj_wait@wait-any-snapshot.html
#### Possible fixes ####
* igt@gem_ctx_isolation@vecs0-s3:
- shard-apl: [DMESG-WARN][27] ([fdo#108566]) -> [PASS][28] +3 similar issues
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6750/shard-apl4/igt@gem_ctx_isolation@vecs0-s3.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14114/shard-apl6/igt@gem_ctx_isolation@vecs0-s3.html
* igt@gem_eio@reset-stress:
- shard-skl: [FAIL][29] ([fdo#109661]) -> [PASS][30]
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6750/shard-skl5/igt@gem_eio@reset-stress.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14114/shard-skl8/igt@gem_eio@reset-stress.html
* igt@gem_exec_balancer@smoke:
- shard-iclb: [SKIP][31] ([fdo#110854]) -> [PASS][32]
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6750/shard-iclb8/igt@gem_exec_balancer@smoke.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14114/shard-iclb1/igt@gem_exec_balancer@smoke.html
* igt@gem_exec_schedule@preempt-queue-bsd1:
- shard-iclb: [SKIP][33] ([fdo#109276]) -> [PASS][34] +17 similar issues
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6750/shard-iclb7/igt@gem_exec_schedule@preempt-queue-bsd1.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14114/shard-iclb4/igt@gem_exec_schedule@preempt-queue-bsd1.html
* igt@gem_exec_schedule@preemptive-hang-bsd:
- shard-iclb: [SKIP][35] ([fdo#111325]) -> [PASS][36] +7 similar issues
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6750/shard-iclb1/igt@gem_exec_schedule@preemptive-hang-bsd.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14114/shard-iclb5/igt@gem_exec_schedule@preemptive-hang-bsd.html
* igt@kms_cursor_crc@pipe-c-cursor-256x85-sliding:
- shard-iclb: [INCOMPLETE][37] ([fdo#107713]) -> [PASS][38]
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6750/shard-iclb7/igt@kms_cursor_crc@pipe-c-cursor-256x85-sliding.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14114/shard-iclb7/igt@kms_cursor_crc@pipe-c-cursor-256x85-sliding.html
* igt@kms_cursor_legacy@pipe-c-single-move:
- shard-apl: [INCOMPLETE][39] ([fdo#103927]) -> [PASS][40] +1 similar issue
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6750/shard-apl1/igt@kms_cursor_legacy@pipe-c-single-move.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14114/shard-apl8/igt@kms_cursor_legacy@pipe-c-single-move.html
* igt@kms_fbcon_fbt@psr-suspend:
- shard-skl: [INCOMPLETE][41] ([fdo#104108]) -> [PASS][42]
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6750/shard-skl10/igt@kms_fbcon_fbt@psr-suspend.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14114/shard-skl1/igt@kms_fbcon_fbt@psr-suspend.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-shrfb-plflip-blt:
- shard-iclb: [FAIL][43] ([fdo#103167]) -> [PASS][44] +3 similar issues
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6750/shard-iclb4/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-shrfb-plflip-blt.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14114/shard-iclb7/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-shrfb-plflip-blt.html
* igt@kms_plane_lowres@pipe-a-tiling-x:
- shard-iclb: [FAIL][45] ([fdo#103166]) -> [PASS][46]
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6750/shard-iclb1/igt@kms_plane_lowres@pipe-a-tiling-x.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14114/shard-iclb2/igt@kms_plane_lowres@pipe-a-tiling-x.html
* igt@kms_psr@psr2_suspend:
- shard-iclb: [SKIP][47] ([fdo#109441]) -> [PASS][48] +2 similar issues
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6750/shard-iclb1/igt@kms_psr@psr2_suspend.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14114/shard-iclb2/igt@kms_psr@psr2_suspend.html
* igt@kms_setmode@basic:
- shard-apl: [FAIL][49] ([fdo#99912]) -> [PASS][50]
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6750/shard-apl5/igt@kms_setmode@basic.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14114/shard-apl6/igt@kms_setmode@basic.html
* igt@perf@blocking:
- shard-skl: [FAIL][51] ([fdo#110728]) -> [PASS][52]
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6750/shard-skl10/igt@perf@blocking.html
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14114/shard-skl9/igt@perf@blocking.html
#### Warnings ####
* igt@gem_mocs_settings@mocs-reset-bsd2:
- shard-iclb: [FAIL][53] ([fdo#111330]) -> [SKIP][54] ([fdo#109276]) +1 similar issue
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6750/shard-iclb2/igt@gem_mocs_settings@mocs-reset-bsd2.html
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14114/shard-iclb8/igt@gem_mocs_settings@mocs-reset-bsd2.html
* igt@i915_suspend@sysfs-reader:
- shard-apl: [DMESG-WARN][55] ([fdo#108566]) -> [INCOMPLETE][56] ([fdo#103927])
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6750/shard-apl7/igt@i915_suspend@sysfs-reader.html
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14114/shard-apl3/igt@i915_suspend@sysfs-reader.html
* igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-blt:
- shard-skl: [FAIL][57] ([fdo#108040]) -> [FAIL][58] ([fdo#103167])
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6750/shard-skl7/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-blt.html
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14114/shard-skl8/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-blt.html
[fdo#102670]: https://bugs.freedesktop.org/show_bug.cgi?id=102670
[fdo#103166]: https://bugs.freedesktop.org/show_bug.cgi?id=103166
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
[fdo#104108]: https://bugs.freedesktop.org/show_bug.cgi?id=104108
[fdo#105363]: https://bugs.freedesktop.org/show_bug.cgi?id=105363
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#108040]: https://bugs.freedesktop.org/show_bug.cgi?id=108040
[fdo#108566]: https://bugs.freedesktop.org/show_bug.cgi?id=108566
[fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642
[fdo#109661]: https://bugs.freedesktop.org/show_bug.cgi?id=109661
[fdo#110728]: https://bugs.freedesktop.org/show_bug.cgi?id=110728
[fdo#110841]: https://bugs.freedesktop.org/show_bug.cgi?id=110841
[fdo#110854]: https://bugs.freedesktop.org/show_bug.cgi?id=110854
[fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
[fdo#111325]: https://bugs.freedesktop.org/show_bug.cgi?id=111325
[fdo#111330]: https://bugs.freedesktop.org/show_bug.cgi?id=111330
[fdo#99912]: https://bugs.freedesktop.org/show_bug.cgi?id=99912
Participating hosts (10 -> 10)
------------------------------
No changes in participating hosts
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_6750 -> Patchwork_14114
CI-20190529: 20190529
CI_DRM_6750: ba37f74dbdc1e78e70a5a2e5f4ce8d762d06eaa7 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5146: 357dbe1869d88a2f08bcee4eebceff4ee9014424 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_14114: 771aa4749697794e7898522473b266d9a85352f9 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14114/
_______________________________________________
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^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH 05/11] drm/i915: Use local variables for subslice_mask for device info
2019-08-20 23:05 ` [PATCH 05/11] drm/i915: Use local variables for subslice_mask for device info Stuart Summers
@ 2019-08-21 22:31 ` Chris Wilson
0 siblings, 0 replies; 32+ messages in thread
From: Chris Wilson @ 2019-08-21 22:31 UTC (permalink / raw)
To: Stuart Summers, intel-gfx
Quoting Stuart Summers (2019-08-21 00:05:38)
> When setting up subslice_mask, instead of operating on the slice
> array directly, use a local variable to start bits per slice, then
> use this to set the per slice array in one step.
>
> Signed-off-by: Stuart Summers <stuart.summers@intel.com>
> ---
> drivers/gpu/drm/i915/intel_device_info.c | 49 +++++++++++++-----------
> 1 file changed, 26 insertions(+), 23 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
> index b1a79ed408eb..52515efe9f4e 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.c
> +++ b/drivers/gpu/drm/i915/intel_device_info.c
> @@ -235,18 +235,6 @@ static void gen10_sseu_info_init(struct drm_i915_private *dev_priv)
> sseu->slice_mask = (fuse2 & GEN10_F2_S_ENA_MASK) >>
> GEN10_F2_S_ENA_SHIFT;
>
> - subslice_mask = (1 << 4) - 1;
> - subslice_mask &= ~((fuse2 & GEN10_F2_SS_DIS_MASK) >>
> - GEN10_F2_SS_DIS_SHIFT);
> -
> - /*
> - * Slice0 can have up to 3 subslices, but there are only 2 in
> - * slice1/2.
> - */
> - sseu->subslice_mask[0] = subslice_mask;
> - for (s = 1; s < sseu->max_slices; s++)
> - sseu->subslice_mask[s] = subslice_mask & 0x3;
> -
> /* Slice0 */
> eu_en = ~I915_READ(GEN8_EU_DISABLE0);
> for (ss = 0; ss < sseu->max_subslices; ss++)
> @@ -270,14 +258,24 @@ static void gen10_sseu_info_init(struct drm_i915_private *dev_priv)
> eu_en = ~I915_READ(GEN10_EU_DISABLE3);
> sseu_set_eus(sseu, 5, 1, eu_en & eu_mask);
>
> - /* Do a second pass where we mark the subslices disabled if all their
> - * eus are off.
> - */
> + subslice_mask = (1 << 4) - 1;
> + subslice_mask &= ~((fuse2 & GEN10_F2_SS_DIS_MASK) >>
> + GEN10_F2_SS_DIS_SHIFT);
> +
> for (s = 0; s < sseu->max_slices; s++) {
> + u32 subslice_mask_with_eus = subslice_mask;
> +
> for (ss = 0; ss < sseu->max_subslices; ss++) {
> if (sseu_get_eus(sseu, s, ss) == 0)
> - sseu->subslice_mask[s] &= ~BIT(ss);
> + subslice_mask_with_eus &= ~BIT(ss);
> }
> +
> + /*
> + * Slice0 can have up to 3 subslices, but there are only 2 in
> + * slice1/2.
> + */
> + sseu->subslice_mask[s] = s == 0 ? subslice_mask_with_eus :
> + subslice_mask_with_eus & 0x3;
Ok. I have no idea what the topology is or why, but I followed the code
and it should not be any logic changes.
> }
>
> sseu->eu_total = compute_eu_total(sseu);
> @@ -303,6 +301,7 @@ static void cherryview_sseu_info_init(struct drm_i915_private *dev_priv)
> {
> struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu;
> u32 fuse;
> + u8 subslice_mask = 0;
>
> fuse = I915_READ(CHV_FUSE_GT);
>
> @@ -316,7 +315,7 @@ static void cherryview_sseu_info_init(struct drm_i915_private *dev_priv)
> (((fuse & CHV_FGT_EU_DIS_SS0_R1_MASK) >>
> CHV_FGT_EU_DIS_SS0_R1_SHIFT) << 4);
>
> - sseu->subslice_mask[0] |= BIT(0);
> + subslice_mask |= BIT(0);
> sseu_set_eus(sseu, 0, 0, ~disabled_mask);
> }
>
> @@ -327,10 +326,12 @@ static void cherryview_sseu_info_init(struct drm_i915_private *dev_priv)
> (((fuse & CHV_FGT_EU_DIS_SS1_R1_MASK) >>
> CHV_FGT_EU_DIS_SS1_R1_SHIFT) << 4);
>
> - sseu->subslice_mask[0] |= BIT(1);
> + subslice_mask |= BIT(1);
> sseu_set_eus(sseu, 0, 1, ~disabled_mask);
> }
>
> + sseu->subslice_mask[0] = subslice_mask;
> +
> sseu->eu_total = compute_eu_total(sseu);
Ok.
>
> /*
> @@ -540,6 +541,7 @@ static void haswell_sseu_info_init(struct drm_i915_private *dev_priv)
> {
> struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu;
> u32 fuse1;
> + u8 subslice_mask = 0;
> int s, ss;
>
> /*
> @@ -552,16 +554,15 @@ static void haswell_sseu_info_init(struct drm_i915_private *dev_priv)
> /* fall through */
> case 1:
> sseu->slice_mask = BIT(0);
> - sseu->subslice_mask[0] = BIT(0);
> + subslice_mask = BIT(0);
> break;
> case 2:
> sseu->slice_mask = BIT(0);
> - sseu->subslice_mask[0] = BIT(0) | BIT(1);
> + subslice_mask = BIT(0) | BIT(1);
> break;
> case 3:
> sseu->slice_mask = BIT(0) | BIT(1);
> - sseu->subslice_mask[0] = BIT(0) | BIT(1);
> - sseu->subslice_mask[1] = BIT(0) | BIT(1);
> + subslice_mask = BIT(0) | BIT(1);
> break;
> }
>
> @@ -583,10 +584,12 @@ static void haswell_sseu_info_init(struct drm_i915_private *dev_priv)
> }
>
> intel_sseu_set_info(sseu, hweight8(sseu->slice_mask),
> - hweight8(sseu->subslice_mask[0]),
> + hweight8(subslice_mask),
> sseu->eu_per_subslice);
>
> for (s = 0; s < sseu->max_slices; s++) {
> + sseu->subslice_mask[s] = subslice_mask;
> +
> for (ss = 0; ss < sseu->max_subslices; ss++) {
> sseu_set_eus(sseu, s, ss,
> (1UL << sseu->eu_per_subslice) - 1);
Ok.
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
-Chris
_______________________________________________
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^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH 06/11] drm/i915: Add function to set subslices
2019-08-20 23:05 ` [PATCH 06/11] drm/i915: Add function to set subslices Stuart Summers
@ 2019-08-21 22:32 ` Chris Wilson
2019-08-21 22:37 ` Summers, Stuart
0 siblings, 1 reply; 32+ messages in thread
From: Chris Wilson @ 2019-08-21 22:32 UTC (permalink / raw)
To: Stuart Summers, intel-gfx
Quoting Stuart Summers (2019-08-21 00:05:39)
> Add a new function to set a set of subslices for a given
> slice.
>
> Signed-off-by: Stuart Summers <stuart.summers@intel.com>
> ---
> drivers/gpu/drm/i915/gt/intel_sseu.c | 6 ++++++
> drivers/gpu/drm/i915/gt/intel_sseu.h | 3 +++
> drivers/gpu/drm/i915/intel_device_info.c | 18 +++++++++++-------
> 3 files changed, 20 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.c b/drivers/gpu/drm/i915/gt/intel_sseu.c
> index 3a5c0f7b5a08..79a9b5f186f9 100644
> --- a/drivers/gpu/drm/i915/gt/intel_sseu.c
> +++ b/drivers/gpu/drm/i915/gt/intel_sseu.c
> @@ -30,6 +30,12 @@ intel_sseu_subslice_total(const struct sseu_dev_info *sseu)
> return total;
> }
>
> +void intel_sseu_set_subslices(struct sseu_dev_info *sseu, int slice,
> + u8 ss_mask)
> +{
> + sseu->subslice_mask[i] = ss_mask & 0xff;
What's i?
-Chris
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^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH 07/11] drm/i915: Use subslice stride to set subslices for a given slice
2019-08-20 23:05 ` [PATCH 07/11] drm/i915: Use subslice stride to set subslices for a given slice Stuart Summers
@ 2019-08-21 22:36 ` Chris Wilson
2019-08-21 22:46 ` Summers, Stuart
0 siblings, 1 reply; 32+ messages in thread
From: Chris Wilson @ 2019-08-21 22:36 UTC (permalink / raw)
To: Stuart Summers, intel-gfx
Quoting Stuart Summers (2019-08-21 00:05:40)
> Add a subslice stride calculation when setting subslices. This
> aligns more closely with the userspace expectation of the subslice
> mask structure.
>
> v2: Use local variable for subslice_mask on HSW and
> clean up a few other subslice_mask local variable
> changes
> v3: Add GEM_BUG_ON for ss_stride to prevent array overflow (Chris)
> Split main set function and refactors in intel_device_info.c
> into separate patches (Chris)
>
> Signed-off-by: Stuart Summers <stuart.summers@intel.com>
> ---
> drivers/gpu/drm/i915/gt/intel_sseu.c | 12 ++++++++++--
> drivers/gpu/drm/i915/gt/intel_sseu.h | 2 +-
> 2 files changed, 11 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.c b/drivers/gpu/drm/i915/gt/intel_sseu.c
> index 79a9b5f186f9..5d537ec97fcc 100644
> --- a/drivers/gpu/drm/i915/gt/intel_sseu.c
> +++ b/drivers/gpu/drm/i915/gt/intel_sseu.c
> @@ -31,9 +31,17 @@ intel_sseu_subslice_total(const struct sseu_dev_info *sseu)
> }
>
> void intel_sseu_set_subslices(struct sseu_dev_info *sseu, int slice,
> - u8 ss_mask)
> + u32 ss_mask)
> {
> - sseu->subslice_mask[i] = ss_mask & 0xff;
> + int i, offset;
> +
> + GEM_BUG_ON(sseu->ss_stride > 32);
> +
> + offset = slice * sseu->ss_stride;
> +
> + for (i = 0; i < sseu->ss_stride; i++)
You are saying that i can be a maximum of 32, and
u32 >> (8 * 32) is legal?
> + sseu->subslice_mask[offset + i] =
> + (ss_mask >> (BITS_PER_BYTE * i)) & 0xff;
The 0xff is, and was, superfluous. Shrug.
-Chris
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^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH 06/11] drm/i915: Add function to set subslices
2019-08-21 22:32 ` Chris Wilson
@ 2019-08-21 22:37 ` Summers, Stuart
0 siblings, 0 replies; 32+ messages in thread
From: Summers, Stuart @ 2019-08-21 22:37 UTC (permalink / raw)
To: intel-gfx, chris
On Wed, 2019-08-21 at 23:32 +0100, Chris Wilson wrote:
> Quoting Stuart Summers (2019-08-21 00:05:39)
> > Add a new function to set a set of subslices for a given
> > slice.
> >
> > Signed-off-by: Stuart Summers <stuart.summers@intel.com>
> > ---
> > drivers/gpu/drm/i915/gt/intel_sseu.c | 6 ++++++
> > drivers/gpu/drm/i915/gt/intel_sseu.h | 3 +++
> > drivers/gpu/drm/i915/intel_device_info.c | 18 +++++++++++-------
> > 3 files changed, 20 insertions(+), 7 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.c
> > b/drivers/gpu/drm/i915/gt/intel_sseu.c
> > index 3a5c0f7b5a08..79a9b5f186f9 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_sseu.c
> > +++ b/drivers/gpu/drm/i915/gt/intel_sseu.c
> > @@ -30,6 +30,12 @@ intel_sseu_subslice_total(const struct
> > sseu_dev_info *sseu)
> > return total;
> > }
> >
> > +void intel_sseu_set_subslices(struct sseu_dev_info *sseu, int
> > slice,
> > + u8 ss_mask)
> > +{
> > + sseu->subslice_mask[i] = ss_mask & 0xff;
>
> What's i?
Should be slice, not i :( not sure why the build wasn't catching this.
I'll fix in the next revision, thanks for the catch!
- Stuart
> -Chris
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^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH 10/11] drm/i915: Add new function to copy subslices for a slice
2019-08-20 23:05 ` [PATCH 10/11] drm/i915: Add new function to copy subslices for a slice Stuart Summers
@ 2019-08-21 22:41 ` Chris Wilson
2019-08-22 16:36 ` Summers, Stuart
0 siblings, 1 reply; 32+ messages in thread
From: Chris Wilson @ 2019-08-21 22:41 UTC (permalink / raw)
To: Stuart Summers, intel-gfx
Quoting Stuart Summers (2019-08-21 00:05:43)
> Add a new function to copy subslices for a specified slice
> between intel_sseu structures for the purpose of determining
> power-gate status.
And ss_stride happens to be one in all cases so far?
For one hsw variant, it is 2 if I am not mistaken. But that isn't
converted.
Could you please drop a note saying that ss_stride is 1!
> Signed-off-by: Stuart Summers <stuart.summers@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
_______________________________________________
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^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH 07/11] drm/i915: Use subslice stride to set subslices for a given slice
2019-08-21 22:36 ` Chris Wilson
@ 2019-08-21 22:46 ` Summers, Stuart
0 siblings, 0 replies; 32+ messages in thread
From: Summers, Stuart @ 2019-08-21 22:46 UTC (permalink / raw)
To: intel-gfx, chris
On Wed, 2019-08-21 at 23:36 +0100, Chris Wilson wrote:
> Quoting Stuart Summers (2019-08-21 00:05:40)
> > Add a subslice stride calculation when setting subslices. This
> > aligns more closely with the userspace expectation of the subslice
> > mask structure.
> >
> > v2: Use local variable for subslice_mask on HSW and
> > clean up a few other subslice_mask local variable
> > changes
> > v3: Add GEM_BUG_ON for ss_stride to prevent array overflow (Chris)
> > Split main set function and refactors in intel_device_info.c
> > into separate patches (Chris)
> >
> > Signed-off-by: Stuart Summers <stuart.summers@intel.com>
> > ---
> > drivers/gpu/drm/i915/gt/intel_sseu.c | 12 ++++++++++--
> > drivers/gpu/drm/i915/gt/intel_sseu.h | 2 +-
> > 2 files changed, 11 insertions(+), 3 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.c
> > b/drivers/gpu/drm/i915/gt/intel_sseu.c
> > index 79a9b5f186f9..5d537ec97fcc 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_sseu.c
> > +++ b/drivers/gpu/drm/i915/gt/intel_sseu.c
> > @@ -31,9 +31,17 @@ intel_sseu_subslice_total(const struct
> > sseu_dev_info *sseu)
> > }
> >
> > void intel_sseu_set_subslices(struct sseu_dev_info *sseu, int
> > slice,
> > - u8 ss_mask)
> > + u32 ss_mask)
> > {
> > - sseu->subslice_mask[i] = ss_mask & 0xff;
> > + int i, offset;
> > +
> > + GEM_BUG_ON(sseu->ss_stride > 32);
> > +
> > + offset = slice * sseu->ss_stride;
> > +
> > + for (i = 0; i < sseu->ss_stride; i++)
>
> You are saying that i can be a maximum of 32, and
> u32 >> (8 * 32) is legal?
Yeah the stride is calculated as a div-by-8, so really this should be
max of 4, not 32. I'll fix this and repost.
>
> > + sseu->subslice_mask[offset + i] =
> > + (ss_mask >> (BITS_PER_BYTE * i)) & 0xff;
>
> The 0xff is, and was, superfluous. Shrug.
I agree in the previous patch this wasn't really interesting. I can
remove that. But here, IMO, having the explicit AND makes this clearer.
Thanks,
Stuart
> -Chris
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^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH 11/11] drm/i915: Expand subslice mask
2019-08-20 23:05 ` [PATCH 11/11] drm/i915: Expand subslice mask Stuart Summers
@ 2019-08-21 22:49 ` Chris Wilson
2019-08-22 0:01 ` Summers, Stuart
0 siblings, 1 reply; 32+ messages in thread
From: Chris Wilson @ 2019-08-21 22:49 UTC (permalink / raw)
To: Stuart Summers, intel-gfx
Quoting Stuart Summers (2019-08-21 00:05:44)
> Currently, the subslice_mask runtime parameter is stored as an
> array of subslices per slice. Expand the subslice mask array to
> better match what is presented to userspace through the
> I915_QUERY_TOPOLOGY_INFO ioctl. The index into this array is
> then calculated:
> slice * subslice stride + subslice index / 8
>
> v2: Fix 32-bit build
> v3: Use new helper function in SSEU workaround warning message
>
> Signed-off-by: Stuart Summers <stuart.summers@intel.com>
> ---
> drivers/gpu/drm/i915/gt/intel_sseu.c | 27 ++++++++++++++++++++-
> drivers/gpu/drm/i915/gt/intel_sseu.h | 5 +++-
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 5 ++--
> drivers/gpu/drm/i915/i915_debugfs.c | 5 +++-
> drivers/gpu/drm/i915/intel_device_info.c | 8 +++---
> 5 files changed, 40 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.c b/drivers/gpu/drm/i915/gt/intel_sseu.c
> index 5d537ec97fcc..eae1c7b20688 100644
> --- a/drivers/gpu/drm/i915/gt/intel_sseu.c
> +++ b/drivers/gpu/drm/i915/gt/intel_sseu.c
> @@ -30,6 +30,31 @@ intel_sseu_subslice_total(const struct sseu_dev_info *sseu)
> return total;
> }
>
> +u32 intel_sseu_get_subslices(const struct sseu_dev_info *sseu, u8 slice)
> +{
> + int i, offset = slice * sseu->ss_stride;
> + u32 mask = 0;
> +
> + if (slice >= sseu->max_slices) {
> + DRM_ERROR("%s: invalid slice %d, max: %d\n",
> + __func__, slice, sseu->max_slices);
> + return 0;
> + }
That's a programmer error, we only need it during development. I am a
proponent of making it explode as early as possible and make people fix
it rather than ignore it.
> + if (sseu->ss_stride > sizeof(mask)) {
> + DRM_ERROR("%s: invalid subslice stride %d, max: %u\n",
> + __func__, sseu->ss_stride,
> + (unsigned int)sizeof(mask));
> + return 0;
> + }
Put the assertion in the constructor (set_sseu_info or whatever it was
called)
> +
> + for (i = 0; i < sseu->ss_stride; i++)
> + mask |= (u32)sseu->subslice_mask[offset + i] <<
> + i * BITS_PER_BYTE;
Otherwise, the actual conversions look fairly straightforward,
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
-Chris
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH 09/11] drm/i915: Refactor instdone loops on new subslice functions
2019-08-20 23:05 ` [PATCH 09/11] drm/i915: Refactor instdone loops on new subslice functions Stuart Summers
@ 2019-08-21 22:56 ` Chris Wilson
2019-08-21 23:32 ` Summers, Stuart
0 siblings, 1 reply; 32+ messages in thread
From: Chris Wilson @ 2019-08-21 22:56 UTC (permalink / raw)
To: Stuart Summers, intel-gfx
Quoting Stuart Summers (2019-08-21 00:05:42)
> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h b/drivers/gpu/drm/i915/gt/intel_engine_types.h
> index a82cea95c2f2..99bee06cdbdb 100644
> --- a/drivers/gpu/drm/i915/gt/intel_engine_types.h
> +++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h
> @@ -576,20 +576,19 @@ intel_engine_is_virtual(const struct intel_engine_cs *engine)
> return engine->flags & I915_ENGINE_IS_VIRTUAL;
> }
>
> -#define instdone_slice_mask(dev_priv__) \
> - (IS_GEN(dev_priv__, 7) ? \
> - 1 : RUNTIME_INFO(dev_priv__)->sseu.slice_mask)
> -
> -#define instdone_subslice_mask(dev_priv__) \
> - (IS_GEN(dev_priv__, 7) ? \
> - 1 : RUNTIME_INFO(dev_priv__)->sseu.subslice_mask[0])
> -
> -#define for_each_instdone_slice_subslice(dev_priv__, slice__, subslice__) \
> - for ((slice__) = 0, (subslice__) = 0; \
> - (slice__) < I915_MAX_SLICES; \
> - (subslice__) = ((subslice__) + 1) < I915_MAX_SUBSLICES ? (subslice__) + 1 : 0, \
> - (slice__) += ((subslice__) == 0)) \
> - for_each_if((BIT(slice__) & instdone_slice_mask(dev_priv__)) && \
> - (BIT(subslice__) & instdone_subslice_mask(dev_priv__)))
> -
> +#define instdone_has_slice(dev_priv___, sseu___, slice___) \
> + ((IS_GEN(dev_priv___, 7) ? 1 : ((sseu___)->slice_mask)) & \
> + BIT(slice___))
((IS_GEN(dev_priv___, 7) ? 1 : \
((sseu___)->slice_mask)) & BIT(slice___))
That split is marginally easier to read
So much for hoping the gen7 special case just disappears.
> +#define instdone_has_subslice(dev_priv__, sseu__, slice__, subslice__) \
> + (IS_GEN(dev_priv__, 7) ? (1 & BIT(subslice__)) : \
> + intel_sseu_has_subslice(sseu__, 0, subslice__))
> +
> +#define for_each_instdone_slice_subslice(dev_priv_, sseu_, slice_, subslice_) \
> + for ((slice_) = 0, (subslice_) = 0; (slice_) < I915_MAX_SLICES; \
> + (subslice_) = ((subslice_) + 1) % I915_MAX_SUBSLICES, \
> + (slice_) += ((subslice_) == 0)) \
> + for_each_if((instdone_has_slice(dev_priv_, sseu_, slice_)) && \
> + (instdone_has_subslice(dev_priv_, sseu_, slice_, \
> + subslice_)))
That was less convoluted than I was expecting from previous skims.
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
-Chris
_______________________________________________
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^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH 09/11] drm/i915: Refactor instdone loops on new subslice functions
2019-08-21 22:56 ` Chris Wilson
@ 2019-08-21 23:32 ` Summers, Stuart
0 siblings, 0 replies; 32+ messages in thread
From: Summers, Stuart @ 2019-08-21 23:32 UTC (permalink / raw)
To: intel-gfx, chris
On Wed, 2019-08-21 at 23:56 +0100, Chris Wilson wrote:
> Quoting Stuart Summers (2019-08-21 00:05:42)
> > diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h
> > b/drivers/gpu/drm/i915/gt/intel_engine_types.h
> > index a82cea95c2f2..99bee06cdbdb 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_engine_types.h
> > +++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h
> > @@ -576,20 +576,19 @@ intel_engine_is_virtual(const struct
> > intel_engine_cs *engine)
> > return engine->flags & I915_ENGINE_IS_VIRTUAL;
> > }
> >
> > -#define instdone_slice_mask(dev_priv__) \
> > - (IS_GEN(dev_priv__, 7) ? \
> > - 1 : RUNTIME_INFO(dev_priv__)->sseu.slice_mask)
> > -
> > -#define instdone_subslice_mask(dev_priv__) \
> > - (IS_GEN(dev_priv__, 7) ? \
> > - 1 : RUNTIME_INFO(dev_priv__)->sseu.subslice_mask[0])
> > -
> > -#define for_each_instdone_slice_subslice(dev_priv__, slice__,
> > subslice__) \
> > - for ((slice__) = 0, (subslice__) = 0; \
> > - (slice__) < I915_MAX_SLICES; \
> > - (subslice__) = ((subslice__) + 1) < I915_MAX_SUBSLICES
> > ? (subslice__) + 1 : 0, \
> > - (slice__) += ((subslice__) == 0)) \
> > - for_each_if((BIT(slice__) &
> > instdone_slice_mask(dev_priv__)) && \
> > - (BIT(subslice__) &
> > instdone_subslice_mask(dev_priv__)))
> > -
> > +#define instdone_has_slice(dev_priv___, sseu___, slice___) \
> > + ((IS_GEN(dev_priv___, 7) ? 1 : ((sseu___)->slice_mask)) & \
> > + BIT(slice___))
>
> ((IS_GEN(dev_priv___, 7) ? 1 : \
> ((sseu___)->slice_mask)) & BIT(slice___))
>
> That split is marginally easier to read
Makes sense, and I agree what I have is a little ugly... I'll change in
the next revision.
>
> So much for hoping the gen7 special case just disappears.
>
> > +#define instdone_has_subslice(dev_priv__, sseu__, slice__,
> > subslice__) \
> > + (IS_GEN(dev_priv__, 7) ? (1 & BIT(subslice__)) : \
> > + intel_sseu_has_subslice(sseu__, 0, subslice__))
> > +
> > +#define for_each_instdone_slice_subslice(dev_priv_, sseu_, slice_,
> > subslice_) \
> > + for ((slice_) = 0, (subslice_) = 0; (slice_) <
> > I915_MAX_SLICES; \
> > + (subslice_) = ((subslice_) + 1) % I915_MAX_SUBSLICES,
> > \
> > + (slice_) += ((subslice_) == 0)) \
> > + for_each_if((instdone_has_slice(dev_priv_, sseu_,
> > slice_)) && \
> > + (instdone_has_subslice(dev_priv_,
> > sseu_, slice_, \
> > + subslice_)))
>
> That was less convoluted than I was expecting from previous skims.
> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Thanks!
-Stuart
> -Chris
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH 11/11] drm/i915: Expand subslice mask
2019-08-21 22:49 ` Chris Wilson
@ 2019-08-22 0:01 ` Summers, Stuart
0 siblings, 0 replies; 32+ messages in thread
From: Summers, Stuart @ 2019-08-22 0:01 UTC (permalink / raw)
To: intel-gfx, chris
[-- Attachment #1.1: Type: text/plain, Size: 2945 bytes --]
On Wed, 2019-08-21 at 23:49 +0100, Chris Wilson wrote:
> Quoting Stuart Summers (2019-08-21 00:05:44)
> > Currently, the subslice_mask runtime parameter is stored as an
> > array of subslices per slice. Expand the subslice mask array to
> > better match what is presented to userspace through the
> > I915_QUERY_TOPOLOGY_INFO ioctl. The index into this array is
> > then calculated:
> > slice * subslice stride + subslice index / 8
> >
> > v2: Fix 32-bit build
> > v3: Use new helper function in SSEU workaround warning message
> >
> > Signed-off-by: Stuart Summers <stuart.summers@intel.com>
> > ---
> > drivers/gpu/drm/i915/gt/intel_sseu.c | 27
> > ++++++++++++++++++++-
> > drivers/gpu/drm/i915/gt/intel_sseu.h | 5 +++-
> > drivers/gpu/drm/i915/gt/intel_workarounds.c | 5 ++--
> > drivers/gpu/drm/i915/i915_debugfs.c | 5 +++-
> > drivers/gpu/drm/i915/intel_device_info.c | 8 +++---
> > 5 files changed, 40 insertions(+), 10 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.c
> > b/drivers/gpu/drm/i915/gt/intel_sseu.c
> > index 5d537ec97fcc..eae1c7b20688 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_sseu.c
> > +++ b/drivers/gpu/drm/i915/gt/intel_sseu.c
> > @@ -30,6 +30,31 @@ intel_sseu_subslice_total(const struct
> > sseu_dev_info *sseu)
> > return total;
> > }
> >
> > +u32 intel_sseu_get_subslices(const struct sseu_dev_info *sseu, u8
> > slice)
> > +{
> > + int i, offset = slice * sseu->ss_stride;
> > + u32 mask = 0;
> > +
> > + if (slice >= sseu->max_slices) {
> > + DRM_ERROR("%s: invalid slice %d, max: %d\n",
> > + __func__, slice, sseu->max_slices);
> > + return 0;
> > + }
>
> That's a programmer error, we only need it during development. I am a
> proponent of making it explode as early as possible and make people
> fix
> it rather than ignore it.
I guess this was trigger shyness on my part after bringing some of the
ICL machines down with my first post of this series :) I agree this
seems like the right thing to do though. I'll make the change in the
next revision.
>
> > + if (sseu->ss_stride > sizeof(mask)) {
> > + DRM_ERROR("%s: invalid subslice stride %d, max:
> > %u\n",
> > + __func__, sseu->ss_stride,
> > + (unsigned int)sizeof(mask));
> > + return 0;
> > + }
>
> Put the assertion in the constructor (set_sseu_info or whatever it
> was
> called)
Makes sense.
>
> > +
> > + for (i = 0; i < sseu->ss_stride; i++)
> > + mask |= (u32)sseu->subslice_mask[offset + i] <<
> > + i * BITS_PER_BYTE;
>
> Otherwise, the actual conversions look fairly straightforward,
> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Thanks!
-Stuart
> -Chris
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^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH 10/11] drm/i915: Add new function to copy subslices for a slice
2019-08-21 22:41 ` Chris Wilson
@ 2019-08-22 16:36 ` Summers, Stuart
0 siblings, 0 replies; 32+ messages in thread
From: Summers, Stuart @ 2019-08-22 16:36 UTC (permalink / raw)
To: intel-gfx, chris
[-- Attachment #1.1: Type: text/plain, Size: 813 bytes --]
On Wed, 2019-08-21 at 23:41 +0100, Chris Wilson wrote:
> Quoting Stuart Summers (2019-08-21 00:05:43)
> > Add a new function to copy subslices for a specified slice
> > between intel_sseu structures for the purpose of determining
> > power-gate status.
>
> And ss_stride happens to be one in all cases so far?
True.
>
> For one hsw variant, it is 2 if I am not mistaken. But that isn't
> converted.
I believe this is for the eu stride, not the subslice stride. We have
the HSW_F1_EU_DIS_10EUS flag to represent this.
>
> Could you please drop a note saying that ss_stride is 1!
No problem though. I'll add this to the commit message.
>
> > Signed-off-by: Stuart Summers <stuart.summers@intel.com>
>
> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Thanks!
-Stuart
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^ permalink raw reply [flat|nested] 32+ messages in thread
* ✓ Fi.CI.IGT: success for Refactor to expand subslice mask (rev 2)
2019-08-23 16:02 [PATCH 00/11] " Stuart Summers
@ 2019-08-24 18:47 ` Patchwork
0 siblings, 0 replies; 32+ messages in thread
From: Patchwork @ 2019-08-24 18:47 UTC (permalink / raw)
To: Stuart Summers; +Cc: intel-gfx
== Series Details ==
Series: Refactor to expand subslice mask (rev 2)
URL : https://patchwork.freedesktop.org/series/65709/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6777_full -> Patchwork_14171_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Known issues
------------
Here are the changes found in Patchwork_14171_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_exec_parallel@fds:
- shard-iclb: [PASS][1] -> [INCOMPLETE][2] ([fdo#107713])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6777/shard-iclb2/igt@gem_exec_parallel@fds.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14171/shard-iclb5/igt@gem_exec_parallel@fds.html
* igt@gem_exec_schedule@preempt-other-chain-bsd:
- shard-iclb: [PASS][3] -> [SKIP][4] ([fdo#111325]) +4 similar issues
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6777/shard-iclb8/igt@gem_exec_schedule@preempt-other-chain-bsd.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14171/shard-iclb1/igt@gem_exec_schedule@preempt-other-chain-bsd.html
* igt@gem_workarounds@suspend-resume-context:
- shard-apl: [PASS][5] -> [DMESG-WARN][6] ([fdo#108566]) +5 similar issues
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6777/shard-apl4/igt@gem_workarounds@suspend-resume-context.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14171/shard-apl1/igt@gem_workarounds@suspend-resume-context.html
* igt@kms_flip@flip-vs-wf_vblank-interruptible:
- shard-hsw: [PASS][7] -> [INCOMPLETE][8] ([fdo#103540])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6777/shard-hsw5/igt@kms_flip@flip-vs-wf_vblank-interruptible.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14171/shard-hsw2/igt@kms_flip@flip-vs-wf_vblank-interruptible.html
* igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-pwrite:
- shard-iclb: [PASS][9] -> [FAIL][10] ([fdo#103167]) +4 similar issues
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6777/shard-iclb3/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-pwrite.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14171/shard-iclb5/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-pwrite.html
* igt@kms_plane@pixel-format-pipe-a-planes-source-clamping:
- shard-apl: [PASS][11] -> [INCOMPLETE][12] ([fdo#103927])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6777/shard-apl2/igt@kms_plane@pixel-format-pipe-a-planes-source-clamping.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14171/shard-apl7/igt@kms_plane@pixel-format-pipe-a-planes-source-clamping.html
* igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
- shard-skl: [PASS][13] -> [FAIL][14] ([fdo#108145] / [fdo#110403])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6777/shard-skl9/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14171/shard-skl5/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
* igt@kms_psr@psr2_primary_page_flip:
- shard-iclb: [PASS][15] -> [SKIP][16] ([fdo#109441])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6777/shard-iclb2/igt@kms_psr@psr2_primary_page_flip.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14171/shard-iclb3/igt@kms_psr@psr2_primary_page_flip.html
* igt@kms_setmode@basic:
- shard-apl: [PASS][17] -> [FAIL][18] ([fdo#99912])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6777/shard-apl8/igt@kms_setmode@basic.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14171/shard-apl3/igt@kms_setmode@basic.html
* igt@prime_busy@after-bsd2:
- shard-iclb: [PASS][19] -> [SKIP][20] ([fdo#109276]) +18 similar issues
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6777/shard-iclb1/igt@prime_busy@after-bsd2.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14171/shard-iclb6/igt@prime_busy@after-bsd2.html
#### Possible fixes ####
* igt@gem_ctx_isolation@rcs0-s3:
- shard-apl: [DMESG-WARN][21] ([fdo#108566]) -> [PASS][22] +1 similar issue
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6777/shard-apl7/igt@gem_ctx_isolation@rcs0-s3.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14171/shard-apl4/igt@gem_ctx_isolation@rcs0-s3.html
* igt@gem_exec_parallel@contexts:
- shard-hsw: [FAIL][23] ([fdo#111469]) -> [PASS][24]
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6777/shard-hsw1/igt@gem_exec_parallel@contexts.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14171/shard-hsw2/igt@gem_exec_parallel@contexts.html
* igt@gem_exec_schedule@preempt-queue-contexts-render:
- shard-apl: [INCOMPLETE][25] ([fdo#103927]) -> [PASS][26]
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6777/shard-apl2/igt@gem_exec_schedule@preempt-queue-contexts-render.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14171/shard-apl2/igt@gem_exec_schedule@preempt-queue-contexts-render.html
* igt@gem_exec_schedule@preemptive-hang-bsd:
- shard-iclb: [SKIP][27] ([fdo#111325]) -> [PASS][28] +2 similar issues
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6777/shard-iclb1/igt@gem_exec_schedule@preemptive-hang-bsd.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14171/shard-iclb7/igt@gem_exec_schedule@preemptive-hang-bsd.html
* igt@kms_flip@2x-flip-vs-suspend:
- shard-hsw: [INCOMPLETE][29] ([fdo#103540]) -> [PASS][30]
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6777/shard-hsw2/igt@kms_flip@2x-flip-vs-suspend.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14171/shard-hsw1/igt@kms_flip@2x-flip-vs-suspend.html
* igt@kms_flip@flip-vs-expired-vblank:
- shard-skl: [FAIL][31] ([fdo#105363]) -> [PASS][32]
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6777/shard-skl2/igt@kms_flip@flip-vs-expired-vblank.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14171/shard-skl9/igt@kms_flip@flip-vs-expired-vblank.html
* igt@kms_frontbuffer_tracking@fbc-1p-pri-indfb-multidraw:
- shard-iclb: [FAIL][33] ([fdo#103167]) -> [PASS][34] +3 similar issues
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6777/shard-iclb5/igt@kms_frontbuffer_tracking@fbc-1p-pri-indfb-multidraw.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14171/shard-iclb3/igt@kms_frontbuffer_tracking@fbc-1p-pri-indfb-multidraw.html
* igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes:
- shard-kbl: [FAIL][35] ([fdo#103375]) -> [PASS][36]
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6777/shard-kbl2/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14171/shard-kbl7/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html
* igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min:
- shard-skl: [FAIL][37] ([fdo#108145]) -> [PASS][38]
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6777/shard-skl9/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14171/shard-skl3/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min.html
* igt@kms_psr@psr2_sprite_mmap_gtt:
- shard-iclb: [SKIP][39] ([fdo#109441]) -> [PASS][40] +3 similar issues
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6777/shard-iclb7/igt@kms_psr@psr2_sprite_mmap_gtt.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14171/shard-iclb2/igt@kms_psr@psr2_sprite_mmap_gtt.html
* igt@kms_setmode@basic:
- shard-hsw: [FAIL][41] ([fdo#99912]) -> [PASS][42]
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6777/shard-hsw2/igt@kms_setmode@basic.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14171/shard-hsw2/igt@kms_setmode@basic.html
* igt@prime_busy@hang-bsd2:
- shard-iclb: [SKIP][43] ([fdo#109276]) -> [PASS][44] +12 similar issues
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6777/shard-iclb6/igt@prime_busy@hang-bsd2.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14171/shard-iclb1/igt@prime_busy@hang-bsd2.html
#### Warnings ####
* igt@gem_ctx_isolation@vcs1-nonpriv:
- shard-iclb: [FAIL][45] ([fdo#111329]) -> [SKIP][46] ([fdo#109276])
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6777/shard-iclb4/igt@gem_ctx_isolation@vcs1-nonpriv.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14171/shard-iclb8/igt@gem_ctx_isolation@vcs1-nonpriv.html
* igt@gem_mocs_settings@mocs-rc6-bsd2:
- shard-iclb: [FAIL][47] ([fdo#111330]) -> [SKIP][48] ([fdo#109276])
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6777/shard-iclb2/igt@gem_mocs_settings@mocs-rc6-bsd2.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14171/shard-iclb5/igt@gem_mocs_settings@mocs-rc6-bsd2.html
* igt@gem_mocs_settings@mocs-settings-bsd2:
- shard-iclb: [SKIP][49] ([fdo#109276]) -> [FAIL][50] ([fdo#111330]) +1 similar issue
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6777/shard-iclb3/igt@gem_mocs_settings@mocs-settings-bsd2.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14171/shard-iclb2/igt@gem_mocs_settings@mocs-settings-bsd2.html
* igt@gem_tiled_swapping@non-threaded:
- shard-skl: [FAIL][51] ([fdo#108686]) -> [SKIP][52] ([fdo#109271])
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6777/shard-skl9/igt@gem_tiled_swapping@non-threaded.html
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14171/shard-skl5/igt@gem_tiled_swapping@non-threaded.html
* igt@kms_dp_dsc@basic-dsc-enable-edp:
- shard-iclb: [SKIP][53] ([fdo#109349]) -> [DMESG-WARN][54] ([fdo#107724])
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6777/shard-iclb8/igt@kms_dp_dsc@basic-dsc-enable-edp.html
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14171/shard-iclb2/igt@kms_dp_dsc@basic-dsc-enable-edp.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-mmap-wc:
- shard-skl: [FAIL][55] ([fdo#103167]) -> [FAIL][56] ([fdo#108040])
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6777/shard-skl7/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-mmap-wc.html
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14171/shard-skl6/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-mmap-wc.html
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#103375]: https://bugs.freedesktop.org/show_bug.cgi?id=103375
[fdo#103540]: https://bugs.freedesktop.org/show_bug.cgi?id=103540
[fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
[fdo#105363]: https://bugs.freedesktop.org/show_bug.cgi?id=105363
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#108040]: https://bugs.freedesktop.org/show_bug.cgi?id=108040
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#108566]: https://bugs.freedesktop.org/show_bug.cgi?id=108566
[fdo#108686]: https://bugs.freedesktop.org/show_bug.cgi?id=108686
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276
[fdo#109349]: https://bugs.freedesktop.org/show_bug.cgi?id=109349
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#110403]: https://bugs.freedesktop.org/show_bug.cgi?id=110403
[fdo#111325]: https://bugs.freedesktop.org/show_bug.cgi?id=111325
[fdo#111329]: https://bugs.freedesktop.org/show_bug.cgi?id=111329
[fdo#111330]: https://bugs.freedesktop.org/show_bug.cgi?id=111330
[fdo#111469]: https://bugs.freedesktop.org/show_bug.cgi?id=111469
[fdo#99912]: https://bugs.freedesktop.org/show_bug.cgi?id=99912
Participating hosts (8 -> 9)
------------------------------
Additional (1): pig-hsw-4770r
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_6777 -> Patchwork_14171
CI-20190529: 20190529
CI_DRM_6777: f3035d74f2d44bab3dbc6673f6660b447cbefd54 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5148: 50390dd7adaccae21cafa85b866c17606cec94c3 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_14171: b8f92343cb4569743e06a5e30b9debab26b742a5 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14171/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 32+ messages in thread
* ✓ Fi.CI.IGT: success for Refactor to expand subslice mask (rev 2)
2019-08-19 21:18 [PATCH 0/9] " Stuart Summers
@ 2019-08-20 11:16 ` Patchwork
0 siblings, 0 replies; 32+ messages in thread
From: Patchwork @ 2019-08-20 11:16 UTC (permalink / raw)
To: Summers, Stuart; +Cc: intel-gfx
== Series Details ==
Series: Refactor to expand subslice mask (rev 2)
URL : https://patchwork.freedesktop.org/series/65435/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6741_full -> Patchwork_14088_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Known issues
------------
Here are the changes found in Patchwork_14088_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_exec_schedule@fifo-bsd1:
- shard-iclb: [PASS][1] -> [SKIP][2] ([fdo#109276]) +10 similar issues
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6741/shard-iclb4/igt@gem_exec_schedule@fifo-bsd1.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14088/shard-iclb3/igt@gem_exec_schedule@fifo-bsd1.html
* igt@gem_exec_schedule@reorder-wide-bsd:
- shard-iclb: [PASS][3] -> [SKIP][4] ([fdo#111325]) +4 similar issues
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6741/shard-iclb3/igt@gem_exec_schedule@reorder-wide-bsd.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14088/shard-iclb1/igt@gem_exec_schedule@reorder-wide-bsd.html
* igt@kms_cursor_crc@pipe-c-cursor-suspend:
- shard-apl: [PASS][5] -> [DMESG-WARN][6] ([fdo#108566]) +2 similar issues
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6741/shard-apl2/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14088/shard-apl7/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
* igt@kms_cursor_legacy@2x-long-cursor-vs-flip-atomic:
- shard-hsw: [PASS][7] -> [FAIL][8] ([fdo#105767])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6741/shard-hsw8/igt@kms_cursor_legacy@2x-long-cursor-vs-flip-atomic.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14088/shard-hsw8/igt@kms_cursor_legacy@2x-long-cursor-vs-flip-atomic.html
* igt@kms_flip@flip-vs-blocking-wf-vblank:
- shard-glk: [PASS][9] -> [INCOMPLETE][10] ([fdo#103359] / [k.org#198133])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6741/shard-glk8/igt@kms_flip@flip-vs-blocking-wf-vblank.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14088/shard-glk3/igt@kms_flip@flip-vs-blocking-wf-vblank.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible:
- shard-glk: [PASS][11] -> [FAIL][12] ([fdo#105363]) +1 similar issue
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6741/shard-glk9/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14088/shard-glk9/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
* igt@kms_flip_tiling@flip-to-x-tiled:
- shard-skl: [PASS][13] -> [FAIL][14] ([fdo#108134])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6741/shard-skl4/igt@kms_flip_tiling@flip-to-x-tiled.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14088/shard-skl9/igt@kms_flip_tiling@flip-to-x-tiled.html
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-mmap-cpu:
- shard-iclb: [PASS][15] -> [FAIL][16] ([fdo#103167]) +2 similar issues
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6741/shard-iclb3/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-mmap-cpu.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14088/shard-iclb2/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-mmap-cpu.html
* igt@kms_plane_alpha_blend@pipe-a-coverage-7efc:
- shard-skl: [PASS][17] -> [FAIL][18] ([fdo#108145])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6741/shard-skl5/igt@kms_plane_alpha_blend@pipe-a-coverage-7efc.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14088/shard-skl7/igt@kms_plane_alpha_blend@pipe-a-coverage-7efc.html
* igt@kms_psr@psr2_primary_mmap_gtt:
- shard-iclb: [PASS][19] -> [SKIP][20] ([fdo#109441])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6741/shard-iclb2/igt@kms_psr@psr2_primary_mmap_gtt.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14088/shard-iclb3/igt@kms_psr@psr2_primary_mmap_gtt.html
* igt@kms_vblank@pipe-a-ts-continuation-dpms-suspend:
- shard-skl: [PASS][21] -> [INCOMPLETE][22] ([fdo#104108])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6741/shard-skl8/igt@kms_vblank@pipe-a-ts-continuation-dpms-suspend.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14088/shard-skl10/igt@kms_vblank@pipe-a-ts-continuation-dpms-suspend.html
* igt@tools_test@tools_test:
- shard-kbl: [PASS][23] -> [SKIP][24] ([fdo#109271])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6741/shard-kbl4/igt@tools_test@tools_test.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14088/shard-kbl2/igt@tools_test@tools_test.html
#### Possible fixes ####
* igt@gem_exec_balancer@smoke:
- shard-iclb: [SKIP][25] ([fdo#110854]) -> [PASS][26]
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6741/shard-iclb8/igt@gem_exec_balancer@smoke.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14088/shard-iclb4/igt@gem_exec_balancer@smoke.html
* igt@gem_exec_schedule@deep-bsd:
- shard-iclb: [SKIP][27] ([fdo#111325]) -> [PASS][28] +1 similar issue
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6741/shard-iclb2/igt@gem_exec_schedule@deep-bsd.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14088/shard-iclb8/igt@gem_exec_schedule@deep-bsd.html
* igt@gem_mmap_gtt@forked-big-copy:
- shard-apl: [INCOMPLETE][29] ([fdo#103927]) -> [PASS][30] +4 similar issues
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6741/shard-apl4/igt@gem_mmap_gtt@forked-big-copy.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14088/shard-apl6/igt@gem_mmap_gtt@forked-big-copy.html
* igt@i915_suspend@sysfs-reader:
- shard-apl: [DMESG-WARN][31] ([fdo#108566]) -> [PASS][32] +5 similar issues
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6741/shard-apl3/igt@i915_suspend@sysfs-reader.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14088/shard-apl2/igt@i915_suspend@sysfs-reader.html
* igt@kms_cursor_legacy@cursor-vs-flip-atomic-transitions:
- shard-hsw: [FAIL][33] ([fdo#103355]) -> [PASS][34]
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6741/shard-hsw6/igt@kms_cursor_legacy@cursor-vs-flip-atomic-transitions.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14088/shard-hsw6/igt@kms_cursor_legacy@cursor-vs-flip-atomic-transitions.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size:
- shard-skl: [FAIL][35] ([fdo#102670]) -> [PASS][36]
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6741/shard-skl1/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14088/shard-skl1/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible:
- shard-skl: [FAIL][37] ([fdo#105363]) -> [PASS][38]
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6741/shard-skl7/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14088/shard-skl7/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-shrfb-plflip-blt:
- shard-iclb: [FAIL][39] ([fdo#103167]) -> [PASS][40] +5 similar issues
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6741/shard-iclb3/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-shrfb-plflip-blt.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14088/shard-iclb7/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-shrfb-plflip-blt.html
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b:
- shard-skl: [INCOMPLETE][41] ([fdo#104108]) -> [PASS][42] +1 similar issue
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6741/shard-skl9/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14088/shard-skl3/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b.html
* igt@kms_plane_lowres@pipe-a-tiling-y:
- shard-iclb: [FAIL][43] ([fdo#103166]) -> [PASS][44]
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6741/shard-iclb6/igt@kms_plane_lowres@pipe-a-tiling-y.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14088/shard-iclb7/igt@kms_plane_lowres@pipe-a-tiling-y.html
* igt@kms_psr@psr2_sprite_plane_move:
- shard-iclb: [SKIP][45] ([fdo#109441]) -> [PASS][46]
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6741/shard-iclb3/igt@kms_psr@psr2_sprite_plane_move.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14088/shard-iclb2/igt@kms_psr@psr2_sprite_plane_move.html
* igt@perf@blocking:
- shard-skl: [FAIL][47] ([fdo#110728]) -> [PASS][48]
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6741/shard-skl5/igt@perf@blocking.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14088/shard-skl6/igt@perf@blocking.html
* igt@prime_vgem@fence-wait-bsd2:
- shard-iclb: [SKIP][49] ([fdo#109276]) -> [PASS][50] +16 similar issues
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6741/shard-iclb7/igt@prime_vgem@fence-wait-bsd2.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14088/shard-iclb1/igt@prime_vgem@fence-wait-bsd2.html
#### Warnings ####
* igt@gem_mocs_settings@mocs-isolation-bsd2:
- shard-iclb: [FAIL][51] ([fdo#111330]) -> [SKIP][52] ([fdo#109276])
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6741/shard-iclb2/igt@gem_mocs_settings@mocs-isolation-bsd2.html
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14088/shard-iclb8/igt@gem_mocs_settings@mocs-isolation-bsd2.html
[fdo#102670]: https://bugs.freedesktop.org/show_bug.cgi?id=102670
[fdo#103166]: https://bugs.freedesktop.org/show_bug.cgi?id=103166
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#103355]: https://bugs.freedesktop.org/show_bug.cgi?id=103355
[fdo#103359]: https://bugs.freedesktop.org/show_bug.cgi?id=103359
[fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
[fdo#104108]: https://bugs.freedesktop.org/show_bug.cgi?id=104108
[fdo#105363]: https://bugs.freedesktop.org/show_bug.cgi?id=105363
[fdo#105767]: https://bugs.freedesktop.org/show_bug.cgi?id=105767
[fdo#108134]: https://bugs.freedesktop.org/show_bug.cgi?id=108134
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#108566]: https://bugs.freedesktop.org/show_bug.cgi?id=108566
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#110728]: https://bugs.freedesktop.org/show_bug.cgi?id=110728
[fdo#110854]: https://bugs.freedesktop.org/show_bug.cgi?id=110854
[fdo#111325]: https://bugs.freedesktop.org/show_bug.cgi?id=111325
[fdo#111330]: https://bugs.freedesktop.org/show_bug.cgi?id=111330
[k.org#198133]: https://bugzilla.kernel.org/show_bug.cgi?id=198133
Participating hosts (10 -> 10)
------------------------------
No changes in participating hosts
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_6741 -> Patchwork_14088
CI-20190529: 20190529
CI_DRM_6741: 0db9333be821acadbf8c476e13b160522d252d77 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5141: 7102b417fedc2a1ea6f72d768a9f1bd100a34f13 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_14088: 2c1643492533ca547351bb56eee2b3b79c1da36c @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14088/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 32+ messages in thread
* ✓ Fi.CI.IGT: success for Refactor to expand subslice mask (rev 2)
2019-08-19 21:49 [PATCH 0/9] " Stuart Summers
2019-08-20 10:44 ` ✓ Fi.CI.IGT: success for " Patchwork
@ 2019-08-20 11:10 ` Patchwork
1 sibling, 0 replies; 32+ messages in thread
From: Patchwork @ 2019-08-20 11:10 UTC (permalink / raw)
To: Summers, Stuart; +Cc: intel-gfx
== Series Details ==
Series: Refactor to expand subslice mask (rev 2)
URL : https://patchwork.freedesktop.org/series/65437/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6741_full -> Patchwork_14089_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Known issues
------------
Here are the changes found in Patchwork_14089_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_exec_blt@dumb-buf:
- shard-apl: [PASS][1] -> [INCOMPLETE][2] ([fdo#103927]) +2 similar issues
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6741/shard-apl1/igt@gem_exec_blt@dumb-buf.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14089/shard-apl7/igt@gem_exec_blt@dumb-buf.html
* igt@gem_exec_schedule@in-order-bsd2:
- shard-iclb: [PASS][3] -> [SKIP][4] ([fdo#109276]) +14 similar issues
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6741/shard-iclb1/igt@gem_exec_schedule@in-order-bsd2.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14089/shard-iclb3/igt@gem_exec_schedule@in-order-bsd2.html
* igt@gem_exec_schedule@preempt-other-chain-bsd:
- shard-iclb: [PASS][5] -> [SKIP][6] ([fdo#111325]) +7 similar issues
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6741/shard-iclb7/igt@gem_exec_schedule@preempt-other-chain-bsd.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14089/shard-iclb4/igt@gem_exec_schedule@preempt-other-chain-bsd.html
* igt@i915_pm_rpm@system-suspend:
- shard-skl: [PASS][7] -> [INCOMPLETE][8] ([fdo#104108] / [fdo#107807])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6741/shard-skl3/igt@i915_pm_rpm@system-suspend.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14089/shard-skl2/igt@i915_pm_rpm@system-suspend.html
* igt@kms_flip@2x-modeset-vs-vblank-race:
- shard-glk: [PASS][9] -> [FAIL][10] ([fdo#103060])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6741/shard-glk1/igt@kms_flip@2x-modeset-vs-vblank-race.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14089/shard-glk5/igt@kms_flip@2x-modeset-vs-vblank-race.html
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-indfb-pgflip-blt:
- shard-iclb: [PASS][11] -> [FAIL][12] ([fdo#103167]) +2 similar issues
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6741/shard-iclb2/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-indfb-pgflip-blt.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14089/shard-iclb2/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-indfb-pgflip-blt.html
* igt@kms_frontbuffer_tracking@fbc-suspend:
- shard-apl: [PASS][13] -> [DMESG-WARN][14] ([fdo#108566]) +2 similar issues
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6741/shard-apl2/igt@kms_frontbuffer_tracking@fbc-suspend.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14089/shard-apl7/igt@kms_frontbuffer_tracking@fbc-suspend.html
* igt@kms_plane_alpha_blend@pipe-a-coverage-7efc:
- shard-skl: [PASS][15] -> [FAIL][16] ([fdo#108145])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6741/shard-skl5/igt@kms_plane_alpha_blend@pipe-a-coverage-7efc.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14089/shard-skl6/igt@kms_plane_alpha_blend@pipe-a-coverage-7efc.html
* igt@kms_psr2_su@frontbuffer:
- shard-iclb: [PASS][17] -> [SKIP][18] ([fdo#109642] / [fdo#111068])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6741/shard-iclb2/igt@kms_psr2_su@frontbuffer.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14089/shard-iclb1/igt@kms_psr2_su@frontbuffer.html
* igt@kms_psr@no_drrs:
- shard-iclb: [PASS][19] -> [FAIL][20] ([fdo#108341])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6741/shard-iclb2/igt@kms_psr@no_drrs.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14089/shard-iclb1/igt@kms_psr@no_drrs.html
* igt@perf_pmu@busy-accuracy-2-bcs0:
- shard-iclb: [PASS][21] -> [INCOMPLETE][22] ([fdo#107713])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6741/shard-iclb8/igt@perf_pmu@busy-accuracy-2-bcs0.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14089/shard-iclb1/igt@perf_pmu@busy-accuracy-2-bcs0.html
#### Possible fixes ####
* igt@gem_exec_schedule@promotion-bsd:
- shard-iclb: [SKIP][23] ([fdo#111325]) -> [PASS][24]
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6741/shard-iclb1/igt@gem_exec_schedule@promotion-bsd.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14089/shard-iclb3/igt@gem_exec_schedule@promotion-bsd.html
* igt@gem_mmap_gtt@forked-big-copy:
- shard-apl: [INCOMPLETE][25] ([fdo#103927]) -> [PASS][26] +2 similar issues
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6741/shard-apl4/igt@gem_mmap_gtt@forked-big-copy.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14089/shard-apl8/igt@gem_mmap_gtt@forked-big-copy.html
* igt@i915_suspend@sysfs-reader:
- shard-apl: [DMESG-WARN][27] ([fdo#108566]) -> [PASS][28] +3 similar issues
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6741/shard-apl3/igt@i915_suspend@sysfs-reader.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14089/shard-apl8/igt@i915_suspend@sysfs-reader.html
* igt@kms_cursor_legacy@cursor-vs-flip-atomic-transitions:
- shard-hsw: [FAIL][29] ([fdo#103355]) -> [PASS][30]
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6741/shard-hsw6/igt@kms_cursor_legacy@cursor-vs-flip-atomic-transitions.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14089/shard-hsw1/igt@kms_cursor_legacy@cursor-vs-flip-atomic-transitions.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size:
- shard-skl: [FAIL][31] ([fdo#102670]) -> [PASS][32]
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6741/shard-skl1/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14089/shard-skl3/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible:
- shard-skl: [FAIL][33] ([fdo#105363]) -> [PASS][34]
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6741/shard-skl7/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14089/shard-skl1/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-shrfb-plflip-blt:
- shard-iclb: [FAIL][35] ([fdo#103167]) -> [PASS][36] +3 similar issues
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6741/shard-iclb3/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-shrfb-plflip-blt.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14089/shard-iclb4/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-shrfb-plflip-blt.html
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b:
- shard-skl: [INCOMPLETE][37] ([fdo#104108]) -> [PASS][38] +1 similar issue
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6741/shard-skl9/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14089/shard-skl10/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b.html
* igt@kms_plane_alpha_blend@pipe-b-coverage-7efc:
- shard-skl: [FAIL][39] ([fdo#108145] / [fdo#110403]) -> [PASS][40]
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6741/shard-skl6/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14089/shard-skl3/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
* igt@kms_plane_lowres@pipe-a-tiling-y:
- shard-iclb: [FAIL][41] ([fdo#103166]) -> [PASS][42]
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6741/shard-iclb6/igt@kms_plane_lowres@pipe-a-tiling-y.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14089/shard-iclb7/igt@kms_plane_lowres@pipe-a-tiling-y.html
* igt@kms_psr@psr2_no_drrs:
- shard-iclb: [SKIP][43] ([fdo#109441]) -> [PASS][44] +1 similar issue
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6741/shard-iclb1/igt@kms_psr@psr2_no_drrs.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14089/shard-iclb2/igt@kms_psr@psr2_no_drrs.html
* igt@perf@blocking:
- shard-skl: [FAIL][45] ([fdo#110728]) -> [PASS][46]
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6741/shard-skl5/igt@perf@blocking.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14089/shard-skl8/igt@perf@blocking.html
* igt@prime_vgem@fence-wait-bsd2:
- shard-iclb: [SKIP][47] ([fdo#109276]) -> [PASS][48] +15 similar issues
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6741/shard-iclb7/igt@prime_vgem@fence-wait-bsd2.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14089/shard-iclb2/igt@prime_vgem@fence-wait-bsd2.html
#### Warnings ####
* igt@gem_mocs_settings@mocs-settings-bsd2:
- shard-iclb: [SKIP][49] ([fdo#109276]) -> [FAIL][50] ([fdo#111330])
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6741/shard-iclb3/igt@gem_mocs_settings@mocs-settings-bsd2.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14089/shard-iclb4/igt@gem_mocs_settings@mocs-settings-bsd2.html
[fdo#102670]: https://bugs.freedesktop.org/show_bug.cgi?id=102670
[fdo#103060]: https://bugs.freedesktop.org/show_bug.cgi?id=103060
[fdo#103166]: https://bugs.freedesktop.org/show_bug.cgi?id=103166
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#103355]: https://bugs.freedesktop.org/show_bug.cgi?id=103355
[fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
[fdo#104108]: https://bugs.freedesktop.org/show_bug.cgi?id=104108
[fdo#105363]: https://bugs.freedesktop.org/show_bug.cgi?id=105363
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107807]: https://bugs.freedesktop.org/show_bug.cgi?id=107807
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#108341]: https://bugs.freedesktop.org/show_bug.cgi?id=108341
[fdo#108566]: https://bugs.freedesktop.org/show_bug.cgi?id=108566
[fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642
[fdo#110403]: https://bugs.freedesktop.org/show_bug.cgi?id=110403
[fdo#110728]: https://bugs.freedesktop.org/show_bug.cgi?id=110728
[fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
[fdo#111325]: https://bugs.freedesktop.org/show_bug.cgi?id=111325
[fdo#111330]: https://bugs.freedesktop.org/show_bug.cgi?id=111330
Participating hosts (10 -> 10)
------------------------------
No changes in participating hosts
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_6741 -> Patchwork_14089
CI-20190529: 20190529
CI_DRM_6741: 0db9333be821acadbf8c476e13b160522d252d77 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5141: 7102b417fedc2a1ea6f72d768a9f1bd100a34f13 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_14089: 974b8ca59175df1e480372d134a39187f42cd060 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14089/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 32+ messages in thread
* ✓ Fi.CI.IGT: success for Refactor to expand subslice mask (rev 2)
2019-08-19 21:49 [PATCH 0/9] " Stuart Summers
@ 2019-08-20 10:44 ` Patchwork
2019-08-20 11:10 ` Patchwork
1 sibling, 0 replies; 32+ messages in thread
From: Patchwork @ 2019-08-20 10:44 UTC (permalink / raw)
To: Summers, Stuart; +Cc: intel-gfx
== Series Details ==
Series: Refactor to expand subslice mask (rev 2)
URL : https://patchwork.freedesktop.org/series/65437/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6741_full -> Patchwork_14089_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Known issues
------------
Here are the changes found in Patchwork_14089_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_exec_blt@dumb-buf:
- shard-apl: [PASS][1] -> [INCOMPLETE][2] ([fdo#103927]) +2 similar issues
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6741/shard-apl1/igt@gem_exec_blt@dumb-buf.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14089/shard-apl7/igt@gem_exec_blt@dumb-buf.html
* igt@gem_exec_schedule@in-order-bsd2:
- shard-iclb: [PASS][3] -> [SKIP][4] ([fdo#109276]) +14 similar issues
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6741/shard-iclb1/igt@gem_exec_schedule@in-order-bsd2.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14089/shard-iclb3/igt@gem_exec_schedule@in-order-bsd2.html
* igt@gem_exec_schedule@preempt-other-chain-bsd:
- shard-iclb: [PASS][5] -> [SKIP][6] ([fdo#111325]) +7 similar issues
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6741/shard-iclb7/igt@gem_exec_schedule@preempt-other-chain-bsd.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14089/shard-iclb4/igt@gem_exec_schedule@preempt-other-chain-bsd.html
* igt@i915_pm_rpm@system-suspend:
- shard-skl: [PASS][7] -> [INCOMPLETE][8] ([fdo#104108] / [fdo#107807])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6741/shard-skl3/igt@i915_pm_rpm@system-suspend.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14089/shard-skl2/igt@i915_pm_rpm@system-suspend.html
* igt@kms_flip@2x-modeset-vs-vblank-race:
- shard-glk: [PASS][9] -> [FAIL][10] ([fdo#103060])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6741/shard-glk1/igt@kms_flip@2x-modeset-vs-vblank-race.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14089/shard-glk5/igt@kms_flip@2x-modeset-vs-vblank-race.html
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-indfb-pgflip-blt:
- shard-iclb: [PASS][11] -> [FAIL][12] ([fdo#103167]) +2 similar issues
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6741/shard-iclb2/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-indfb-pgflip-blt.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14089/shard-iclb2/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-indfb-pgflip-blt.html
* igt@kms_frontbuffer_tracking@fbc-suspend:
- shard-apl: [PASS][13] -> [DMESG-WARN][14] ([fdo#108566]) +2 similar issues
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6741/shard-apl2/igt@kms_frontbuffer_tracking@fbc-suspend.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14089/shard-apl7/igt@kms_frontbuffer_tracking@fbc-suspend.html
* igt@kms_plane_alpha_blend@pipe-a-coverage-7efc:
- shard-skl: [PASS][15] -> [FAIL][16] ([fdo#108145])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6741/shard-skl5/igt@kms_plane_alpha_blend@pipe-a-coverage-7efc.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14089/shard-skl6/igt@kms_plane_alpha_blend@pipe-a-coverage-7efc.html
* igt@kms_psr2_su@frontbuffer:
- shard-iclb: [PASS][17] -> [SKIP][18] ([fdo#109642] / [fdo#111068])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6741/shard-iclb2/igt@kms_psr2_su@frontbuffer.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14089/shard-iclb1/igt@kms_psr2_su@frontbuffer.html
* igt@kms_psr@no_drrs:
- shard-iclb: [PASS][19] -> [FAIL][20] ([fdo#108341])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6741/shard-iclb2/igt@kms_psr@no_drrs.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14089/shard-iclb1/igt@kms_psr@no_drrs.html
* igt@perf_pmu@busy-accuracy-2-bcs0:
- shard-iclb: [PASS][21] -> [INCOMPLETE][22] ([fdo#107713])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6741/shard-iclb8/igt@perf_pmu@busy-accuracy-2-bcs0.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14089/shard-iclb1/igt@perf_pmu@busy-accuracy-2-bcs0.html
#### Possible fixes ####
* igt@gem_exec_schedule@promotion-bsd:
- shard-iclb: [SKIP][23] ([fdo#111325]) -> [PASS][24]
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6741/shard-iclb1/igt@gem_exec_schedule@promotion-bsd.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14089/shard-iclb3/igt@gem_exec_schedule@promotion-bsd.html
* igt@gem_mmap_gtt@forked-big-copy:
- shard-apl: [INCOMPLETE][25] ([fdo#103927]) -> [PASS][26] +2 similar issues
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6741/shard-apl4/igt@gem_mmap_gtt@forked-big-copy.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14089/shard-apl8/igt@gem_mmap_gtt@forked-big-copy.html
* igt@i915_suspend@sysfs-reader:
- shard-apl: [DMESG-WARN][27] ([fdo#108566]) -> [PASS][28] +3 similar issues
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6741/shard-apl3/igt@i915_suspend@sysfs-reader.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14089/shard-apl8/igt@i915_suspend@sysfs-reader.html
* igt@kms_cursor_legacy@cursor-vs-flip-atomic-transitions:
- shard-hsw: [FAIL][29] ([fdo#103355]) -> [PASS][30]
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6741/shard-hsw6/igt@kms_cursor_legacy@cursor-vs-flip-atomic-transitions.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14089/shard-hsw1/igt@kms_cursor_legacy@cursor-vs-flip-atomic-transitions.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size:
- shard-skl: [FAIL][31] ([fdo#102670]) -> [PASS][32]
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6741/shard-skl1/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14089/shard-skl3/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible:
- shard-skl: [FAIL][33] ([fdo#105363]) -> [PASS][34]
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6741/shard-skl7/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14089/shard-skl1/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-shrfb-plflip-blt:
- shard-iclb: [FAIL][35] ([fdo#103167]) -> [PASS][36] +3 similar issues
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6741/shard-iclb3/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-shrfb-plflip-blt.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14089/shard-iclb4/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-shrfb-plflip-blt.html
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b:
- shard-skl: [INCOMPLETE][37] ([fdo#104108]) -> [PASS][38] +1 similar issue
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6741/shard-skl9/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14089/shard-skl10/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b.html
* igt@kms_plane_alpha_blend@pipe-b-coverage-7efc:
- shard-skl: [FAIL][39] ([fdo#108145] / [fdo#110403]) -> [PASS][40]
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6741/shard-skl6/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14089/shard-skl3/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
* igt@kms_plane_lowres@pipe-a-tiling-y:
- shard-iclb: [FAIL][41] ([fdo#103166]) -> [PASS][42]
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6741/shard-iclb6/igt@kms_plane_lowres@pipe-a-tiling-y.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14089/shard-iclb7/igt@kms_plane_lowres@pipe-a-tiling-y.html
* igt@kms_psr@psr2_no_drrs:
- shard-iclb: [SKIP][43] ([fdo#109441]) -> [PASS][44] +1 similar issue
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6741/shard-iclb1/igt@kms_psr@psr2_no_drrs.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14089/shard-iclb2/igt@kms_psr@psr2_no_drrs.html
* igt@perf@blocking:
- shard-skl: [FAIL][45] ([fdo#110728]) -> [PASS][46]
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6741/shard-skl5/igt@perf@blocking.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14089/shard-skl8/igt@perf@blocking.html
* igt@prime_vgem@fence-wait-bsd2:
- shard-iclb: [SKIP][47] ([fdo#109276]) -> [PASS][48] +15 similar issues
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6741/shard-iclb7/igt@prime_vgem@fence-wait-bsd2.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14089/shard-iclb2/igt@prime_vgem@fence-wait-bsd2.html
#### Warnings ####
* igt@gem_mocs_settings@mocs-settings-bsd2:
- shard-iclb: [SKIP][49] ([fdo#109276]) -> [FAIL][50] ([fdo#111330])
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6741/shard-iclb3/igt@gem_mocs_settings@mocs-settings-bsd2.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14089/shard-iclb4/igt@gem_mocs_settings@mocs-settings-bsd2.html
[fdo#102670]: https://bugs.freedesktop.org/show_bug.cgi?id=102670
[fdo#103060]: https://bugs.freedesktop.org/show_bug.cgi?id=103060
[fdo#103166]: https://bugs.freedesktop.org/show_bug.cgi?id=103166
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#103355]: https://bugs.freedesktop.org/show_bug.cgi?id=103355
[fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
[fdo#104108]: https://bugs.freedesktop.org/show_bug.cgi?id=104108
[fdo#105363]: https://bugs.freedesktop.org/show_bug.cgi?id=105363
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107807]: https://bugs.freedesktop.org/show_bug.cgi?id=107807
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#108341]: https://bugs.freedesktop.org/show_bug.cgi?id=108341
[fdo#108566]: https://bugs.freedesktop.org/show_bug.cgi?id=108566
[fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642
[fdo#110403]: https://bugs.freedesktop.org/show_bug.cgi?id=110403
[fdo#110728]: https://bugs.freedesktop.org/show_bug.cgi?id=110728
[fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
[fdo#111325]: https://bugs.freedesktop.org/show_bug.cgi?id=111325
[fdo#111330]: https://bugs.freedesktop.org/show_bug.cgi?id=111330
Participating hosts (10 -> 10)
------------------------------
No changes in participating hosts
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_6741 -> Patchwork_14089
CI-20190529: 20190529
CI_DRM_6741: 0db9333be821acadbf8c476e13b160522d252d77 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5141: 7102b417fedc2a1ea6f72d768a9f1bd100a34f13 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_14089: 974b8ca59175df1e480372d134a39187f42cd060 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14089/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 32+ messages in thread
* ✓ Fi.CI.IGT: success for Refactor to expand subslice mask (rev 2)
2019-08-02 20:51 [PATCH 00/10] " Stuart Summers
@ 2019-08-04 13:45 ` Patchwork
0 siblings, 0 replies; 32+ messages in thread
From: Patchwork @ 2019-08-04 13:45 UTC (permalink / raw)
To: Stuart Summers; +Cc: intel-gfx
== Series Details ==
Series: Refactor to expand subslice mask (rev 2)
URL : https://patchwork.freedesktop.org/series/64636/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6618_full -> Patchwork_13858_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Known issues
------------
Here are the changes found in Patchwork_13858_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@kms_cursor_crc@pipe-c-cursor-128x128-offscreen:
- shard-hsw: [PASS][1] -> [INCOMPLETE][2] ([fdo#103540])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6618/shard-hsw5/igt@kms_cursor_crc@pipe-c-cursor-128x128-offscreen.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13858/shard-hsw2/igt@kms_cursor_crc@pipe-c-cursor-128x128-offscreen.html
* igt@kms_cursor_legacy@2x-long-cursor-vs-flip-legacy:
- shard-hsw: [PASS][3] -> [FAIL][4] ([fdo#105767])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6618/shard-hsw2/igt@kms_cursor_legacy@2x-long-cursor-vs-flip-legacy.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13858/shard-hsw4/igt@kms_cursor_legacy@2x-long-cursor-vs-flip-legacy.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions:
- shard-skl: [PASS][5] -> [FAIL][6] ([fdo#102670])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6618/shard-skl6/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13858/shard-skl6/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible:
- shard-skl: [PASS][7] -> [FAIL][8] ([fdo#105363])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6618/shard-skl3/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13858/shard-skl2/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-pwrite:
- shard-iclb: [PASS][9] -> [FAIL][10] ([fdo#103167]) +5 similar issues
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6618/shard-iclb3/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-pwrite.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13858/shard-iclb7/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-pwrite.html
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-shrfb-plflip-blt:
- shard-skl: [PASS][11] -> [FAIL][12] ([fdo#103167])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6618/shard-skl9/igt@kms_frontbuffer_tracking@psr-1p-primscrn-shrfb-plflip-blt.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13858/shard-skl7/igt@kms_frontbuffer_tracking@psr-1p-primscrn-shrfb-plflip-blt.html
* igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min:
- shard-skl: [PASS][13] -> [FAIL][14] ([fdo#108145])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6618/shard-skl9/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13858/shard-skl7/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min.html
* igt@kms_plane_lowres@pipe-a-tiling-y:
- shard-iclb: [PASS][15] -> [FAIL][16] ([fdo#103166])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6618/shard-iclb2/igt@kms_plane_lowres@pipe-a-tiling-y.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13858/shard-iclb6/igt@kms_plane_lowres@pipe-a-tiling-y.html
* igt@kms_psr@psr2_sprite_plane_move:
- shard-iclb: [PASS][17] -> [SKIP][18] ([fdo#109441]) +2 similar issues
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6618/shard-iclb2/igt@kms_psr@psr2_sprite_plane_move.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13858/shard-iclb6/igt@kms_psr@psr2_sprite_plane_move.html
* igt@kms_setmode@basic:
- shard-apl: [PASS][19] -> [FAIL][20] ([fdo#99912])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6618/shard-apl4/igt@kms_setmode@basic.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13858/shard-apl8/igt@kms_setmode@basic.html
* igt@kms_vblank@pipe-a-ts-continuation-suspend:
- shard-apl: [PASS][21] -> [DMESG-WARN][22] ([fdo#108566]) +5 similar issues
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6618/shard-apl8/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13858/shard-apl4/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
- shard-skl: [PASS][23] -> [INCOMPLETE][24] ([fdo#104108])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6618/shard-skl9/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13858/shard-skl7/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
* igt@perf@blocking:
- shard-skl: [PASS][25] -> [FAIL][26] ([fdo#110728])
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6618/shard-skl3/igt@perf@blocking.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13858/shard-skl2/igt@perf@blocking.html
#### Possible fixes ####
* igt@gem_eio@reset-stress:
- shard-skl: [FAIL][27] ([fdo#109661]) -> [PASS][28]
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6618/shard-skl9/igt@gem_eio@reset-stress.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13858/shard-skl7/igt@gem_eio@reset-stress.html
* igt@i915_suspend@fence-restore-tiled2untiled:
- shard-apl: [DMESG-WARN][29] ([fdo#108566]) -> [PASS][30] +3 similar issues
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6618/shard-apl7/igt@i915_suspend@fence-restore-tiled2untiled.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13858/shard-apl2/igt@i915_suspend@fence-restore-tiled2untiled.html
* igt@kms_cursor_crc@pipe-c-cursor-256x256-sliding:
- shard-skl: [FAIL][31] ([fdo#103232]) -> [PASS][32] +1 similar issue
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6618/shard-skl3/igt@kms_cursor_crc@pipe-c-cursor-256x256-sliding.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13858/shard-skl2/igt@kms_cursor_crc@pipe-c-cursor-256x256-sliding.html
* igt@kms_cursor_edge_walk@pipe-b-64x64-top-edge:
- shard-iclb: [INCOMPLETE][33] ([fdo#107713]) -> [PASS][34]
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6618/shard-iclb4/igt@kms_cursor_edge_walk@pipe-b-64x64-top-edge.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13858/shard-iclb6/igt@kms_cursor_edge_walk@pipe-b-64x64-top-edge.html
* igt@kms_flip@plain-flip-fb-recreate:
- shard-skl: [FAIL][35] ([fdo#100368]) -> [PASS][36]
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6618/shard-skl7/igt@kms_flip@plain-flip-fb-recreate.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13858/shard-skl9/igt@kms_flip@plain-flip-fb-recreate.html
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-blt:
- shard-iclb: [FAIL][37] ([fdo#103167]) -> [PASS][38] +4 similar issues
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6618/shard-iclb1/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-blt.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13858/shard-iclb8/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-blt.html
* igt@kms_plane@pixel-format-pipe-b-planes-source-clamping:
- shard-iclb: [INCOMPLETE][39] ([fdo#107713] / [fdo#110036 ]) -> [PASS][40]
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6618/shard-iclb7/igt@kms_plane@pixel-format-pipe-b-planes-source-clamping.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13858/shard-iclb2/igt@kms_plane@pixel-format-pipe-b-planes-source-clamping.html
* igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
- shard-skl: [FAIL][41] ([fdo#108145] / [fdo#110403]) -> [PASS][42]
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6618/shard-skl7/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13858/shard-skl3/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
* igt@kms_psr@no_drrs:
- shard-iclb: [FAIL][43] ([fdo#108341]) -> [PASS][44]
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6618/shard-iclb1/igt@kms_psr@no_drrs.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13858/shard-iclb6/igt@kms_psr@no_drrs.html
* igt@kms_psr@psr2_primary_mmap_gtt:
- shard-iclb: [SKIP][45] ([fdo#109441]) -> [PASS][46] +3 similar issues
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6618/shard-iclb7/igt@kms_psr@psr2_primary_mmap_gtt.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13858/shard-iclb2/igt@kms_psr@psr2_primary_mmap_gtt.html
[fdo#100368]: https://bugs.freedesktop.org/show_bug.cgi?id=100368
[fdo#102670]: https://bugs.freedesktop.org/show_bug.cgi?id=102670
[fdo#103166]: https://bugs.freedesktop.org/show_bug.cgi?id=103166
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#103232]: https://bugs.freedesktop.org/show_bug.cgi?id=103232
[fdo#103540]: https://bugs.freedesktop.org/show_bug.cgi?id=103540
[fdo#104108]: https://bugs.freedesktop.org/show_bug.cgi?id=104108
[fdo#105363]: https://bugs.freedesktop.org/show_bug.cgi?id=105363
[fdo#105767]: https://bugs.freedesktop.org/show_bug.cgi?id=105767
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#108341]: https://bugs.freedesktop.org/show_bug.cgi?id=108341
[fdo#108566]: https://bugs.freedesktop.org/show_bug.cgi?id=108566
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#109661]: https://bugs.freedesktop.org/show_bug.cgi?id=109661
[fdo#110036 ]: https://bugs.freedesktop.org/show_bug.cgi?id=110036
[fdo#110403]: https://bugs.freedesktop.org/show_bug.cgi?id=110403
[fdo#110728]: https://bugs.freedesktop.org/show_bug.cgi?id=110728
[fdo#99912]: https://bugs.freedesktop.org/show_bug.cgi?id=99912
Participating hosts (9 -> 9)
------------------------------
No changes in participating hosts
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_6618 -> Patchwork_13858
CI-20190529: 20190529
CI_DRM_6618: 7bef836acab541f26d5806697c13181df22f71a1 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5120: b3138fbea79d5d7935e53530b90efe3e816236f4 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_13858: 39b89e427a09312070728bbec82701dc3df3bb77 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13858/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 32+ messages in thread
end of thread, other threads:[~2019-08-24 18:47 UTC | newest]
Thread overview: 32+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-08-20 23:05 [PATCH 00/11] Refactor to expand subslice mask (rev 2) Stuart Summers
2019-08-20 23:05 ` [PATCH 01/11] drm/i915: Use variable for debugfs device status Stuart Summers
2019-08-20 23:05 ` [PATCH 02/11] drm/i915: Add function to set SSEU info per platform Stuart Summers
2019-08-20 23:05 ` [PATCH 03/11] drm/i915: Add subslice stride runtime parameter Stuart Summers
2019-08-20 23:05 ` [PATCH 04/11] drm/i915: Add EU " Stuart Summers
2019-08-20 23:05 ` [PATCH 05/11] drm/i915: Use local variables for subslice_mask for device info Stuart Summers
2019-08-21 22:31 ` Chris Wilson
2019-08-20 23:05 ` [PATCH 06/11] drm/i915: Add function to set subslices Stuart Summers
2019-08-21 22:32 ` Chris Wilson
2019-08-21 22:37 ` Summers, Stuart
2019-08-20 23:05 ` [PATCH 07/11] drm/i915: Use subslice stride to set subslices for a given slice Stuart Summers
2019-08-21 22:36 ` Chris Wilson
2019-08-21 22:46 ` Summers, Stuart
2019-08-20 23:05 ` [PATCH 08/11] drm/i915: Add function to determine if a slice has a subslice Stuart Summers
2019-08-20 23:05 ` [PATCH 09/11] drm/i915: Refactor instdone loops on new subslice functions Stuart Summers
2019-08-21 22:56 ` Chris Wilson
2019-08-21 23:32 ` Summers, Stuart
2019-08-20 23:05 ` [PATCH 10/11] drm/i915: Add new function to copy subslices for a slice Stuart Summers
2019-08-21 22:41 ` Chris Wilson
2019-08-22 16:36 ` Summers, Stuart
2019-08-20 23:05 ` [PATCH 11/11] drm/i915: Expand subslice mask Stuart Summers
2019-08-21 22:49 ` Chris Wilson
2019-08-22 0:01 ` Summers, Stuart
2019-08-20 23:59 ` ✗ Fi.CI.CHECKPATCH: warning for Refactor to expand subslice mask (rev 2) Patchwork
2019-08-21 0:02 ` ✗ Fi.CI.SPARSE: " Patchwork
2019-08-21 0:20 ` ✓ Fi.CI.BAT: success " Patchwork
2019-08-21 15:15 ` ✓ Fi.CI.IGT: " Patchwork
-- strict thread matches above, loose matches on Subject: below --
2019-08-23 16:02 [PATCH 00/11] " Stuart Summers
2019-08-24 18:47 ` ✓ Fi.CI.IGT: success for " Patchwork
2019-08-19 21:49 [PATCH 0/9] " Stuart Summers
2019-08-20 10:44 ` ✓ Fi.CI.IGT: success for " Patchwork
2019-08-20 11:10 ` Patchwork
2019-08-19 21:18 [PATCH 0/9] " Stuart Summers
2019-08-20 11:16 ` ✓ Fi.CI.IGT: success for " Patchwork
2019-08-02 20:51 [PATCH 00/10] " Stuart Summers
2019-08-04 13:45 ` ✓ Fi.CI.IGT: success for " Patchwork
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