* [PATCH 01/15] drm/edid: Add drm_hdmi_avi_infoframe_bars()
2019-09-04 16:26 [PATCH 00/15] drm/i915: Expose margin connector properties for underscan Ville Syrjala
@ 2019-09-04 16:26 ` Ville Syrjala
2019-09-04 16:26 ` Ville Syrjala
` (20 subsequent siblings)
21 siblings, 0 replies; 27+ messages in thread
From: Ville Syrjala @ 2019-09-04 16:26 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Add a function to fill the AVI infoframe bar information from
the standard tv margin properties.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/drm_edid.c | 17 +++++++++++++++++
include/drm/drm_edid.h | 4 ++++
2 files changed, 21 insertions(+)
diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index 82a4ceed3fcf..1e16ee20cd31 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -5282,6 +5282,23 @@ drm_hdmi_avi_infoframe_quant_range(struct hdmi_avi_infoframe *frame,
}
EXPORT_SYMBOL(drm_hdmi_avi_infoframe_quant_range);
+/**
+ * drm_hdmi_avi_infoframe_bars() - fill the HDMI AVI infoframe
+ * bar information
+ * @frame: HDMI AVI infoframe
+ * @conn_state: connector state
+ */
+void
+drm_hdmi_avi_infoframe_bars(struct hdmi_avi_infoframe *frame,
+ const struct drm_connector_state *conn_state)
+{
+ frame->right_bar = conn_state->tv.margins.right;
+ frame->left_bar = conn_state->tv.margins.left;
+ frame->top_bar = conn_state->tv.margins.top;
+ frame->bottom_bar = conn_state->tv.margins.bottom;
+}
+EXPORT_SYMBOL(drm_hdmi_avi_infoframe_bars);
+
static enum hdmi_3d_structure
s3d_structure_from_display_mode(const struct drm_display_mode *mode)
{
diff --git a/include/drm/drm_edid.h b/include/drm/drm_edid.h
index b9719418c3d2..e0701b3d3194 100644
--- a/include/drm/drm_edid.h
+++ b/include/drm/drm_edid.h
@@ -367,6 +367,10 @@ void
drm_hdmi_avi_infoframe_colorspace(struct hdmi_avi_infoframe *frame,
const struct drm_connector_state *conn_state);
+void
+drm_hdmi_avi_infoframe_bars(struct hdmi_avi_infoframe *frame,
+ const struct drm_connector_state *conn_state);
+
void
drm_hdmi_avi_infoframe_quant_range(struct hdmi_avi_infoframe *frame,
struct drm_connector *connector,
--
2.21.0
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^ permalink raw reply related [flat|nested] 27+ messages in thread* [PATCH 01/15] drm/edid: Add drm_hdmi_avi_infoframe_bars()
2019-09-04 16:26 [PATCH 00/15] drm/i915: Expose margin connector properties for underscan Ville Syrjala
2019-09-04 16:26 ` [PATCH 01/15] drm/edid: Add drm_hdmi_avi_infoframe_bars() Ville Syrjala
@ 2019-09-04 16:26 ` Ville Syrjala
2019-09-04 16:26 ` [PATCH 02/15] drm/i915: Parametrize PFIT_PIPE Ville Syrjala
` (19 subsequent siblings)
21 siblings, 0 replies; 27+ messages in thread
From: Ville Syrjala @ 2019-09-04 16:26 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Add a function to fill the AVI infoframe bar information from
the standard tv margin properties.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/drm_edid.c | 17 +++++++++++++++++
include/drm/drm_edid.h | 4 ++++
2 files changed, 21 insertions(+)
diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index 82a4ceed3fcf..1e16ee20cd31 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -5282,6 +5282,23 @@ drm_hdmi_avi_infoframe_quant_range(struct hdmi_avi_infoframe *frame,
}
EXPORT_SYMBOL(drm_hdmi_avi_infoframe_quant_range);
+/**
+ * drm_hdmi_avi_infoframe_bars() - fill the HDMI AVI infoframe
+ * bar information
+ * @frame: HDMI AVI infoframe
+ * @conn_state: connector state
+ */
+void
+drm_hdmi_avi_infoframe_bars(struct hdmi_avi_infoframe *frame,
+ const struct drm_connector_state *conn_state)
+{
+ frame->right_bar = conn_state->tv.margins.right;
+ frame->left_bar = conn_state->tv.margins.left;
+ frame->top_bar = conn_state->tv.margins.top;
+ frame->bottom_bar = conn_state->tv.margins.bottom;
+}
+EXPORT_SYMBOL(drm_hdmi_avi_infoframe_bars);
+
static enum hdmi_3d_structure
s3d_structure_from_display_mode(const struct drm_display_mode *mode)
{
diff --git a/include/drm/drm_edid.h b/include/drm/drm_edid.h
index b9719418c3d2..e0701b3d3194 100644
--- a/include/drm/drm_edid.h
+++ b/include/drm/drm_edid.h
@@ -367,6 +367,10 @@ void
drm_hdmi_avi_infoframe_colorspace(struct hdmi_avi_infoframe *frame,
const struct drm_connector_state *conn_state);
+void
+drm_hdmi_avi_infoframe_bars(struct hdmi_avi_infoframe *frame,
+ const struct drm_connector_state *conn_state);
+
void
drm_hdmi_avi_infoframe_quant_range(struct hdmi_avi_infoframe *frame,
struct drm_connector *connector,
--
2.21.0
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^ permalink raw reply related [flat|nested] 27+ messages in thread* [PATCH 02/15] drm/i915: Parametrize PFIT_PIPE
2019-09-04 16:26 [PATCH 00/15] drm/i915: Expose margin connector properties for underscan Ville Syrjala
2019-09-04 16:26 ` [PATCH 01/15] drm/edid: Add drm_hdmi_avi_infoframe_bars() Ville Syrjala
2019-09-04 16:26 ` Ville Syrjala
@ 2019-09-04 16:26 ` Ville Syrjala
2019-09-04 16:26 ` [PATCH 03/15] drm/i915: Replace some accidental I915_READ_FW()s with the normal version Ville Syrjala
` (18 subsequent siblings)
21 siblings, 0 replies; 27+ messages in thread
From: Ville Syrjala @ 2019-09-04 16:26 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Make the PFIT_PIPE stuff less ugly via parametriziation.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_panel.c | 3 +--
drivers/gpu/drm/i915/i915_reg.h | 1 +
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_panel.c b/drivers/gpu/drm/i915/display/intel_panel.c
index bc14e9c0285a..4601416c603e 100644
--- a/drivers/gpu/drm/i915/display/intel_panel.c
+++ b/drivers/gpu/drm/i915/display/intel_panel.c
@@ -430,8 +430,7 @@ void intel_gmch_panel_fitting(struct intel_crtc *intel_crtc,
/* 965+ wants fuzzy fitting */
/* FIXME: handle multiple panels by failing gracefully */
if (INTEL_GEN(dev_priv) >= 4)
- pfit_control |= ((intel_crtc->pipe << PFIT_PIPE_SHIFT) |
- PFIT_FILTER_FUZZY);
+ pfit_control |= PFIT_PIPE(intel_crtc->pipe) | PFIT_FILTER_FUZZY;
out:
if ((pfit_control & PFIT_ENABLE) == 0) {
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 45ed96d7c599..22130ada891d 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4787,6 +4787,7 @@ enum {
#define PFIT_ENABLE (1 << 31)
#define PFIT_PIPE_MASK (3 << 29)
#define PFIT_PIPE_SHIFT 29
+#define PFIT_PIPE(pipe) ((pipe) << 29)
#define VERT_INTERP_DISABLE (0 << 10)
#define VERT_INTERP_BILINEAR (1 << 10)
#define VERT_INTERP_MASK (3 << 10)
--
2.21.0
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^ permalink raw reply related [flat|nested] 27+ messages in thread* [PATCH 03/15] drm/i915: Replace some accidental I915_READ_FW()s with the normal version
2019-09-04 16:26 [PATCH 00/15] drm/i915: Expose margin connector properties for underscan Ville Syrjala
` (2 preceding siblings ...)
2019-09-04 16:26 ` [PATCH 02/15] drm/i915: Parametrize PFIT_PIPE Ville Syrjala
@ 2019-09-04 16:26 ` Ville Syrjala
2019-09-04 16:26 ` [PATCH 04/15] drm/i915: Fix skl+ non-scaled pfit modes Ville Syrjala
` (17 subsequent siblings)
21 siblings, 0 replies; 27+ messages in thread
From: Ville Syrjala @ 2019-09-04 16:26 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Some I915_READ_FW()s have snuck in where we don't hold the uncore lock.
Replace with the normal thing for now.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 06cf2171474d..84d8a4e2ec24 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -5622,10 +5622,10 @@ static void skylake_pfit_enable(const struct intel_crtc_state *crtc_state)
id = scaler_state->scaler_id;
I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
- I915_WRITE_FW(SKL_PS_VPHASE(pipe, id),
- PS_Y_PHASE(0) | PS_UV_RGB_PHASE(uv_rgb_vphase));
- I915_WRITE_FW(SKL_PS_HPHASE(pipe, id),
- PS_Y_PHASE(0) | PS_UV_RGB_PHASE(uv_rgb_hphase));
+ I915_WRITE(SKL_PS_VPHASE(pipe, id),
+ PS_Y_PHASE(0) | PS_UV_RGB_PHASE(uv_rgb_vphase));
+ I915_WRITE(SKL_PS_HPHASE(pipe, id),
+ PS_Y_PHASE(0) | PS_UV_RGB_PHASE(uv_rgb_hphase));
I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc_state->pch_pfit.pos);
I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc_state->pch_pfit.size);
}
--
2.21.0
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^ permalink raw reply related [flat|nested] 27+ messages in thread* [PATCH 04/15] drm/i915: Fix skl+ non-scaled pfit modes
2019-09-04 16:26 [PATCH 00/15] drm/i915: Expose margin connector properties for underscan Ville Syrjala
` (3 preceding siblings ...)
2019-09-04 16:26 ` [PATCH 03/15] drm/i915: Replace some accidental I915_READ_FW()s with the normal version Ville Syrjala
@ 2019-09-04 16:26 ` Ville Syrjala
2019-09-04 16:26 ` [PATCH 05/15] drm/i915: Flatten a bunch of the pfit functions Ville Syrjala
` (16 subsequent siblings)
21 siblings, 0 replies; 27+ messages in thread
From: Ville Syrjala @ 2019-09-04 16:26 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Fix skl_update_scaler_crtc() to deal with different scaling
modes correctly. The current implementation assumes
DRM_MODE_SCALE_FULLSCREEN. Fortunately we don't expose any
border properties currently so the code does actually end
up doing the right thing (assigning a scaler for pfit).
The code does need to be fixed before any borders are
exposed.
Also we have redundant calls to skl_update_scaler_crtc() in
dp/hdmi .compute_config() which can be nuked. They were anyway
called before we had even computed the pfit state so were
basically nonsense. The real call we need to keep is in
intel_crtc_atomic_check().
v2: Deal witrh skl_update_scaler_crtc() in intel_dp_ycbcr420_config()
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 38 ++++++++++----------
drivers/gpu/drm/i915/display/intel_display.h | 1 -
drivers/gpu/drm/i915/display/intel_dp.c | 15 --------
drivers/gpu/drm/i915/display/intel_hdmi.c | 6 ----
4 files changed, 19 insertions(+), 41 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 84d8a4e2ec24..1403e9aad057 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -5479,28 +5479,28 @@ skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
return 0;
}
-/**
- * skl_update_scaler_crtc - Stages update to scaler state for a given crtc.
- *
- * @state: crtc's scaler state
- *
- * Return
- * 0 - scaler_usage updated successfully
- * error - requested scaling cannot be supported or other error condition
- */
-int skl_update_scaler_crtc(struct intel_crtc_state *state)
+static int skl_update_scaler_crtc(struct intel_crtc_state *crtc_state)
{
- const struct drm_display_mode *adjusted_mode = &state->base.adjusted_mode;
- bool need_scaler = false;
+ const struct drm_display_mode *adjusted_mode =
+ &crtc_state->base.adjusted_mode;
+ int width, height;
- if (state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
- need_scaler = true;
+ if (crtc_state->pch_pfit.enabled) {
+ u32 pfit_size = crtc_state->pch_pfit.size;
+
+ width = pfit_size >> 16;
+ height = pfit_size & 0xffff;
+ } else {
+ width = adjusted_mode->crtc_hdisplay;
+ height = adjusted_mode->crtc_vdisplay;
+ }
- return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX,
- &state->scaler_state.scaler_id,
- state->pipe_src_w, state->pipe_src_h,
- adjusted_mode->crtc_hdisplay,
- adjusted_mode->crtc_vdisplay, NULL, need_scaler);
+ return skl_update_scaler(crtc_state, !crtc_state->base.active,
+ SKL_CRTC_INDEX,
+ &crtc_state->scaler_state.scaler_id,
+ crtc_state->pipe_src_w, crtc_state->pipe_src_h,
+ width, height, NULL,
+ crtc_state->pch_pfit.enabled);
}
/**
diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
index 33fd523c4622..ecebe567c647 100644
--- a/drivers/gpu/drm/i915/display/intel_display.h
+++ b/drivers/gpu/drm/i915/display/intel_display.h
@@ -546,7 +546,6 @@ void intel_crtc_arm_fifo_underrun(struct intel_crtc *crtc,
struct intel_crtc_state *crtc_state);
u16 skl_scaler_calc_phase(int sub, int scale, bool chroma_center);
-int skl_update_scaler_crtc(struct intel_crtc_state *crtc_state);
int skl_max_scale(const struct intel_crtc_state *crtc_state,
u32 pixel_format);
u32 glk_plane_color_ctl(const struct intel_crtc_state *crtc_state,
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 5673ed75e428..d333f87d5b39 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -2121,7 +2121,6 @@ intel_dp_ycbcr420_config(struct intel_dp *intel_dp,
const struct drm_display_mode *adjusted_mode =
&crtc_state->base.adjusted_mode;
struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
- int ret;
if (!drm_mode_is_420_only(info, adjusted_mode) ||
!intel_dp_get_colorimetry_status(intel_dp) ||
@@ -2130,13 +2129,6 @@ intel_dp_ycbcr420_config(struct intel_dp *intel_dp,
crtc_state->output_format = INTEL_OUTPUT_FORMAT_YCBCR420;
- /* YCBCR 420 output conversion needs a scaler */
- ret = skl_update_scaler_crtc(crtc_state);
- if (ret) {
- DRM_DEBUG_KMS("Scaler allocation for output failed\n");
- return ret;
- }
-
intel_pch_panel_fitting(crtc, crtc_state, DRM_MODE_SCALE_FULLSCREEN);
return 0;
@@ -2192,7 +2184,6 @@ intel_dp_compute_config(struct intel_encoder *encoder,
else
ret = intel_dp_ycbcr420_config(intel_dp, &intel_connector->base,
pipe_config);
-
if (ret)
return ret;
@@ -2208,12 +2199,6 @@ intel_dp_compute_config(struct intel_encoder *encoder,
intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
adjusted_mode);
- if (INTEL_GEN(dev_priv) >= 9) {
- ret = skl_update_scaler_crtc(pipe_config);
- if (ret)
- return ret;
- }
-
if (HAS_GMCH(dev_priv))
intel_gmch_panel_fitting(intel_crtc, pipe_config,
conn_state->scaling_mode);
diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c
index c500fc9154c8..4039c2216ae0 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
@@ -2276,12 +2276,6 @@ intel_hdmi_ycbcr420_config(struct drm_connector *connector,
config->output_format = INTEL_OUTPUT_FORMAT_YCBCR420;
- /* YCBCR 420 output conversion needs a scaler */
- if (skl_update_scaler_crtc(config)) {
- DRM_DEBUG_KMS("Scaler allocation for output failed\n");
- return false;
- }
-
intel_pch_panel_fitting(intel_crtc, config,
DRM_MODE_SCALE_FULLSCREEN);
--
2.21.0
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^ permalink raw reply related [flat|nested] 27+ messages in thread* [PATCH 05/15] drm/i915: Flatten a bunch of the pfit functions
2019-09-04 16:26 [PATCH 00/15] drm/i915: Expose margin connector properties for underscan Ville Syrjala
` (4 preceding siblings ...)
2019-09-04 16:26 ` [PATCH 04/15] drm/i915: Fix skl+ non-scaled pfit modes Ville Syrjala
@ 2019-09-04 16:26 ` Ville Syrjala
2019-09-04 16:26 ` [PATCH 06/15] drm/i915: Use drm_rect to store the pfit window pos/size Ville Syrjala
` (15 subsequent siblings)
21 siblings, 0 replies; 27+ messages in thread
From: Ville Syrjala @ 2019-09-04 16:26 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Most of the pfit functions are of the form:
func()
{
if (pfit_enabled) {
...
}
}
Flip the pfit_enabled check around to flatten the functions.
And while we're touching all this let's do the usual
s/pipe_config/crtc_state/ replacement.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 207 +++++++++----------
drivers/gpu/drm/i915/intel_pm.c | 38 ++--
2 files changed, 119 insertions(+), 126 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 1403e9aad057..7efb3781109a 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -5601,34 +5601,34 @@ static void skylake_pfit_enable(const struct intel_crtc_state *crtc_state)
enum pipe pipe = crtc->pipe;
const struct intel_crtc_scaler_state *scaler_state =
&crtc_state->scaler_state;
+ u16 uv_rgb_hphase, uv_rgb_vphase;
+ int pfit_w, pfit_h, hscale, vscale;
+ int id;
- if (crtc_state->pch_pfit.enabled) {
- u16 uv_rgb_hphase, uv_rgb_vphase;
- int pfit_w, pfit_h, hscale, vscale;
- int id;
+ if (!crtc_state->pch_pfit.enabled)
+ return;
- if (WARN_ON(crtc_state->scaler_state.scaler_id < 0))
- return;
+ if (WARN_ON(crtc_state->scaler_state.scaler_id < 0))
+ return;
- pfit_w = (crtc_state->pch_pfit.size >> 16) & 0xFFFF;
- pfit_h = crtc_state->pch_pfit.size & 0xFFFF;
+ pfit_w = (crtc_state->pch_pfit.size >> 16) & 0xFFFF;
+ pfit_h = crtc_state->pch_pfit.size & 0xFFFF;
- hscale = (crtc_state->pipe_src_w << 16) / pfit_w;
- vscale = (crtc_state->pipe_src_h << 16) / pfit_h;
+ hscale = (crtc_state->pipe_src_w << 16) / pfit_w;
+ vscale = (crtc_state->pipe_src_h << 16) / pfit_h;
- uv_rgb_hphase = skl_scaler_calc_phase(1, hscale, false);
- uv_rgb_vphase = skl_scaler_calc_phase(1, vscale, false);
+ uv_rgb_hphase = skl_scaler_calc_phase(1, hscale, false);
+ uv_rgb_vphase = skl_scaler_calc_phase(1, vscale, false);
- id = scaler_state->scaler_id;
- I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
- PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
- I915_WRITE(SKL_PS_VPHASE(pipe, id),
- PS_Y_PHASE(0) | PS_UV_RGB_PHASE(uv_rgb_vphase));
- I915_WRITE(SKL_PS_HPHASE(pipe, id),
- PS_Y_PHASE(0) | PS_UV_RGB_PHASE(uv_rgb_hphase));
- I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc_state->pch_pfit.pos);
- I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc_state->pch_pfit.size);
- }
+ id = scaler_state->scaler_id;
+ I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
+ PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
+ I915_WRITE(SKL_PS_VPHASE(pipe, id),
+ PS_Y_PHASE(0) | PS_UV_RGB_PHASE(uv_rgb_vphase));
+ I915_WRITE(SKL_PS_HPHASE(pipe, id),
+ PS_Y_PHASE(0) | PS_UV_RGB_PHASE(uv_rgb_hphase));
+ I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc_state->pch_pfit.pos);
+ I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc_state->pch_pfit.size);
}
static void ironlake_pfit_enable(const struct intel_crtc_state *crtc_state)
@@ -5637,19 +5637,20 @@ static void ironlake_pfit_enable(const struct intel_crtc_state *crtc_state)
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
enum pipe pipe = crtc->pipe;
- if (crtc_state->pch_pfit.enabled) {
- /* Force use of hard-coded filter coefficients
- * as some pre-programmed values are broken,
- * e.g. x201.
- */
- if (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv))
- I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
- PF_PIPE_SEL_IVB(pipe));
- else
- I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
- I915_WRITE(PF_WIN_POS(pipe), crtc_state->pch_pfit.pos);
- I915_WRITE(PF_WIN_SZ(pipe), crtc_state->pch_pfit.size);
- }
+ if (!crtc_state->pch_pfit.enabled)
+ return;
+
+ /* Force use of hard-coded filter coefficients
+ * as some pre-programmed values are broken,
+ * e.g. x201.
+ */
+ if (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv))
+ I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
+ PF_PIPE_SEL_IVB(pipe));
+ else
+ I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
+ I915_WRITE(PF_WIN_POS(pipe), crtc_state->pch_pfit.pos);
+ I915_WRITE(PF_WIN_SZ(pipe), crtc_state->pch_pfit.size);
}
void hsw_enable_ips(const struct intel_crtc_state *crtc_state)
@@ -6540,11 +6541,12 @@ static void ironlake_pfit_disable(const struct intel_crtc_state *old_crtc_state)
/* To avoid upsetting the power well on haswell only disable the pfit if
* it's in use. The hw state code will make sure we get this right. */
- if (old_crtc_state->pch_pfit.enabled) {
- I915_WRITE(PF_CTL(pipe), 0);
- I915_WRITE(PF_WIN_POS(pipe), 0);
- I915_WRITE(PF_WIN_SZ(pipe), 0);
- }
+ if (!old_crtc_state->pch_pfit.enabled)
+ return;
+
+ I915_WRITE(PF_CTL(pipe), 0);
+ I915_WRITE(PF_WIN_POS(pipe), 0);
+ I915_WRITE(PF_WIN_SZ(pipe), 0);
}
static void ironlake_crtc_disable(struct intel_crtc_state *old_crtc_state,
@@ -7354,39 +7356,35 @@ static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc)
(crtc->pipe == PIPE_A || IS_I915G(dev_priv));
}
-static u32 ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config)
+static u32 ilk_pipe_pixel_rate(const struct intel_crtc_state *crtc_state)
{
- u32 pixel_rate;
-
- pixel_rate = pipe_config->base.adjusted_mode.crtc_clock;
+ u32 pixel_rate = crtc_state->base.adjusted_mode.crtc_clock;
+ u32 pfit_size = crtc_state->pch_pfit.size;
+ u64 pipe_w, pipe_h, pfit_w, pfit_h;
/*
* We only use IF-ID interlacing. If we ever use
* PF-ID we'll need to adjust the pixel_rate here.
*/
- if (pipe_config->pch_pfit.enabled) {
- u64 pipe_w, pipe_h, pfit_w, pfit_h;
- u32 pfit_size = pipe_config->pch_pfit.size;
+ if (!crtc_state->pch_pfit.enabled)
+ return pixel_rate;
- pipe_w = pipe_config->pipe_src_w;
- pipe_h = pipe_config->pipe_src_h;
+ pipe_w = crtc_state->pipe_src_w;
+ pipe_h = crtc_state->pipe_src_h;
- pfit_w = (pfit_size >> 16) & 0xFFFF;
- pfit_h = pfit_size & 0xFFFF;
- if (pipe_w < pfit_w)
- pipe_w = pfit_w;
- if (pipe_h < pfit_h)
- pipe_h = pfit_h;
+ pfit_w = (pfit_size >> 16) & 0xFFFF;
+ pfit_h = pfit_size & 0xFFFF;
+ if (pipe_w < pfit_w)
+ pipe_w = pfit_w;
+ if (pipe_h < pfit_h)
+ pipe_h = pfit_h;
- if (WARN_ON(!pfit_w || !pfit_h))
- return pixel_rate;
+ if (WARN_ON(!pfit_w || !pfit_h))
+ return pixel_rate;
- pixel_rate = div_u64(mul_u32_u32(pixel_rate, pipe_w * pipe_h),
- pfit_w * pfit_h);
- }
-
- return pixel_rate;
+ return div_u64(mul_u32_u32(pixel_rate, pipe_w * pipe_h),
+ pfit_w * pfit_h);
}
static void intel_crtc_compute_pixel_rate(struct intel_crtc_state *crtc_state)
@@ -8514,9 +8512,9 @@ static bool i9xx_has_pfit(struct drm_i915_private *dev_priv)
IS_PINEVIEW(dev_priv) || IS_MOBILE(dev_priv);
}
-static void i9xx_get_pfit_config(struct intel_crtc *crtc,
- struct intel_crtc_state *pipe_config)
+static void i9xx_get_pfit_config(struct intel_crtc_state *crtc_state)
{
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
u32 tmp;
@@ -8536,8 +8534,8 @@ static void i9xx_get_pfit_config(struct intel_crtc *crtc,
return;
}
- pipe_config->gmch_pfit.control = tmp;
- pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
+ crtc_state->gmch_pfit.control = tmp;
+ crtc_state->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
}
static void vlv_crtc_clock_get(struct intel_crtc *crtc,
@@ -8805,7 +8803,7 @@ static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
intel_get_pipe_timings(crtc, pipe_config);
intel_get_pipe_src_size(crtc, pipe_config);
- i9xx_get_pfit_config(crtc, pipe_config);
+ i9xx_get_pfit_config(pipe_config);
if (INTEL_GEN(dev_priv) >= 4) {
/* No way to read it out on pipes B and C */
@@ -9738,35 +9736,35 @@ static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
&pipe_config->fdi_m_n, NULL);
}
-static void skylake_get_pfit_config(struct intel_crtc *crtc,
- struct intel_crtc_state *pipe_config)
+static void skylake_get_pfit_config(struct intel_crtc_state *crtc_state)
{
- struct drm_device *dev = crtc->base.dev;
- struct drm_i915_private *dev_priv = to_i915(dev);
- struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
- u32 ps_ctrl = 0;
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state;
int id = -1;
int i;
/* find scaler attached to this pipe */
for (i = 0; i < crtc->num_scalers; i++) {
- ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
- if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
- id = i;
- pipe_config->pch_pfit.enabled = true;
- pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
- pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
- scaler_state->scalers[i].in_use = true;
- break;
- }
+ u32 tmp;
+
+ tmp = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
+ if ((tmp & (PS_SCALER_EN | PS_PLANE_SEL_MASK)) != PS_SCALER_EN)
+ continue;
+
+ id = i;
+ crtc_state->pch_pfit.enabled = true;
+ crtc_state->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
+ crtc_state->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
+ scaler_state->scalers[i].in_use = true;
+ break;
}
scaler_state->scaler_id = id;
- if (id >= 0) {
+ if (id >= 0)
scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
- } else {
+ else
scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
- }
}
static void
@@ -9896,28 +9894,27 @@ skylake_get_initial_plane_config(struct intel_crtc *crtc,
kfree(intel_fb);
}
-static void ironlake_get_pfit_config(struct intel_crtc *crtc,
- struct intel_crtc_state *pipe_config)
+static void ironlake_get_pfit_config(struct intel_crtc_state *crtc_state)
{
- struct drm_device *dev = crtc->base.dev;
- struct drm_i915_private *dev_priv = to_i915(dev);
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
u32 tmp;
tmp = I915_READ(PF_CTL(crtc->pipe));
+ if ((tmp & PF_ENABLE) == 0)
+ return;
- if (tmp & PF_ENABLE) {
- pipe_config->pch_pfit.enabled = true;
- pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
- pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
-
- /* We currently do not free assignements of panel fitters on
- * ivb/hsw (since we don't use the higher upscaling modes which
- * differentiates them) so just WARN about this case for now. */
- if (IS_GEN(dev_priv, 7)) {
- WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
- PF_PIPE_SEL_IVB(crtc->pipe));
- }
- }
+ /*
+ * We currently do not free assignements of panel fitters on
+ * ivb/hsw (since we don't use the higher upscaling modes which
+ * differentiates them) so just WARN about this case for now.
+ */
+ WARN_ON(IS_GEN(dev_priv, 7) &&
+ (tmp & PF_PIPE_SEL_MASK_IVB) != PF_PIPE_SEL_IVB(crtc->pipe));
+
+ crtc_state->pch_pfit.enabled = true;
+ crtc_state->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
+ crtc_state->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
}
static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
@@ -10018,7 +10015,7 @@ static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
intel_get_pipe_timings(crtc, pipe_config);
intel_get_pipe_src_size(crtc, pipe_config);
- ironlake_get_pfit_config(crtc, pipe_config);
+ ironlake_get_pfit_config(pipe_config);
ret = true;
@@ -10448,9 +10445,9 @@ static bool haswell_get_pipe_config(struct intel_crtc *crtc,
power_domain_mask |= BIT_ULL(power_domain);
if (INTEL_GEN(dev_priv) >= 9)
- skylake_get_pfit_config(crtc, pipe_config);
+ skylake_get_pfit_config(pipe_config);
else
- ironlake_get_pfit_config(crtc, pipe_config);
+ ironlake_get_pfit_config(pipe_config);
}
if (hsw_crtc_supports_ips(crtc)) {
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 4fa9bc83c8b4..9f3184e0d2f1 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4105,33 +4105,29 @@ static uint_fixed_16_16_t
skl_pipe_downscale_amount(const struct intel_crtc_state *crtc_state)
{
uint_fixed_16_16_t pipe_downscale = u32_to_fixed16(1);
+ u32 src_w, src_h, dst_w, dst_h;
+ u32 pfit_size = crtc_state->pch_pfit.size;
+ uint_fixed_16_16_t fp_w_ratio, fp_h_ratio;
+ uint_fixed_16_16_t downscale_h, downscale_w;
- if (!crtc_state->base.enable)
+ if (!crtc_state->base.enable ||
+ !crtc_state->pch_pfit.enabled)
return pipe_downscale;
- if (crtc_state->pch_pfit.enabled) {
- u32 src_w, src_h, dst_w, dst_h;
- u32 pfit_size = crtc_state->pch_pfit.size;
- uint_fixed_16_16_t fp_w_ratio, fp_h_ratio;
- uint_fixed_16_16_t downscale_h, downscale_w;
+ src_w = crtc_state->pipe_src_w;
+ src_h = crtc_state->pipe_src_h;
+ dst_w = pfit_size >> 16;
+ dst_h = pfit_size & 0xffff;
- src_w = crtc_state->pipe_src_w;
- src_h = crtc_state->pipe_src_h;
- dst_w = pfit_size >> 16;
- dst_h = pfit_size & 0xffff;
-
- if (!dst_w || !dst_h)
- return pipe_downscale;
-
- fp_w_ratio = div_fixed16(src_w, dst_w);
- fp_h_ratio = div_fixed16(src_h, dst_h);
- downscale_w = max_fixed16(fp_w_ratio, u32_to_fixed16(1));
- downscale_h = max_fixed16(fp_h_ratio, u32_to_fixed16(1));
+ if (!dst_w || !dst_h)
+ return pipe_downscale;
- pipe_downscale = mul_fixed16(downscale_w, downscale_h);
- }
+ fp_w_ratio = div_fixed16(src_w, dst_w);
+ fp_h_ratio = div_fixed16(src_h, dst_h);
+ downscale_w = max_fixed16(fp_w_ratio, u32_to_fixed16(1));
+ downscale_h = max_fixed16(fp_h_ratio, u32_to_fixed16(1));
- return pipe_downscale;
+ return mul_fixed16(downscale_w, downscale_h);
}
int skl_check_pipe_max_pixel_rate(struct intel_crtc *intel_crtc,
--
2.21.0
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^ permalink raw reply related [flat|nested] 27+ messages in thread* [PATCH 06/15] drm/i915: Use drm_rect to store the pfit window pos/size
2019-09-04 16:26 [PATCH 00/15] drm/i915: Expose margin connector properties for underscan Ville Syrjala
` (5 preceding siblings ...)
2019-09-04 16:26 ` [PATCH 05/15] drm/i915: Flatten a bunch of the pfit functions Ville Syrjala
@ 2019-09-04 16:26 ` Ville Syrjala
2019-09-04 16:26 ` [PATCH 07/15] drm/i915: Check pipe source size against pfit limits Ville Syrjala
` (14 subsequent siblings)
21 siblings, 0 replies; 27+ messages in thread
From: Ville Syrjala @ 2019-09-04 16:26 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Make things a bit more abstract by replacing the pch_pfit.pos/size
raw register values with a drm_rect. Makes it slighly more convenient
to eg. compute the scaling factors.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 83 ++++++++++++-------
.../drm/i915/display/intel_display_types.h | 3 +-
drivers/gpu/drm/i915/display/intel_panel.c | 15 ++--
drivers/gpu/drm/i915/intel_pm.c | 5 +-
4 files changed, 66 insertions(+), 40 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 7efb3781109a..348071db8b4c 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -5486,10 +5486,8 @@ static int skl_update_scaler_crtc(struct intel_crtc_state *crtc_state)
int width, height;
if (crtc_state->pch_pfit.enabled) {
- u32 pfit_size = crtc_state->pch_pfit.size;
-
- width = pfit_size >> 16;
- height = pfit_size & 0xffff;
+ width = drm_rect_width(&crtc_state->pch_pfit.dst);
+ height = drm_rect_height(&crtc_state->pch_pfit.dst);
} else {
width = adjusted_mode->crtc_hdisplay;
height = adjusted_mode->crtc_vdisplay;
@@ -5598,11 +5596,20 @@ static void skylake_pfit_enable(const struct intel_crtc_state *crtc_state)
{
struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
- enum pipe pipe = crtc->pipe;
const struct intel_crtc_scaler_state *scaler_state =
&crtc_state->scaler_state;
+ struct drm_rect src = {
+ .x2 = crtc_state->pipe_src_w << 16,
+ .y2 = crtc_state->pipe_src_h << 16,
+ };
+ const struct drm_rect *dst = &crtc_state->pch_pfit.dst;
u16 uv_rgb_hphase, uv_rgb_vphase;
- int pfit_w, pfit_h, hscale, vscale;
+ enum pipe pipe = crtc->pipe;
+ int width = drm_rect_width(dst);
+ int height = drm_rect_height(dst);
+ int x = dst->x1;
+ int y = dst->y1;
+ int hscale, vscale;
int id;
if (!crtc_state->pch_pfit.enabled)
@@ -5611,11 +5618,8 @@ static void skylake_pfit_enable(const struct intel_crtc_state *crtc_state)
if (WARN_ON(crtc_state->scaler_state.scaler_id < 0))
return;
- pfit_w = (crtc_state->pch_pfit.size >> 16) & 0xFFFF;
- pfit_h = crtc_state->pch_pfit.size & 0xFFFF;
-
- hscale = (crtc_state->pipe_src_w << 16) / pfit_w;
- vscale = (crtc_state->pipe_src_h << 16) / pfit_h;
+ hscale = drm_rect_calc_hscale(&src, dst, 0, INT_MAX);
+ vscale = drm_rect_calc_vscale(&src, dst, 0, INT_MAX);
uv_rgb_hphase = skl_scaler_calc_phase(1, hscale, false);
uv_rgb_vphase = skl_scaler_calc_phase(1, vscale, false);
@@ -5627,15 +5631,20 @@ static void skylake_pfit_enable(const struct intel_crtc_state *crtc_state)
PS_Y_PHASE(0) | PS_UV_RGB_PHASE(uv_rgb_vphase));
I915_WRITE(SKL_PS_HPHASE(pipe, id),
PS_Y_PHASE(0) | PS_UV_RGB_PHASE(uv_rgb_hphase));
- I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc_state->pch_pfit.pos);
- I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc_state->pch_pfit.size);
+ I915_WRITE(SKL_PS_WIN_POS(pipe, id), x << 16 | y);
+ I915_WRITE(SKL_PS_WIN_SZ(pipe, id), width << 16 | height);
}
static void ironlake_pfit_enable(const struct intel_crtc_state *crtc_state)
{
struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ const struct drm_rect *dst = &crtc_state->pch_pfit.dst;
enum pipe pipe = crtc->pipe;
+ int width = drm_rect_width(dst);
+ int height = drm_rect_height(dst);
+ int x = dst->x1;
+ int y = dst->y1;
if (!crtc_state->pch_pfit.enabled)
return;
@@ -5649,8 +5658,8 @@ static void ironlake_pfit_enable(const struct intel_crtc_state *crtc_state)
PF_PIPE_SEL_IVB(pipe));
else
I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
- I915_WRITE(PF_WIN_POS(pipe), crtc_state->pch_pfit.pos);
- I915_WRITE(PF_WIN_SZ(pipe), crtc_state->pch_pfit.size);
+ I915_WRITE(PF_WIN_POS(pipe), x << 16 | y);
+ I915_WRITE(PF_WIN_SZ(pipe), width << 16 | height);
}
void hsw_enable_ips(const struct intel_crtc_state *crtc_state)
@@ -7359,8 +7368,7 @@ static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc)
static u32 ilk_pipe_pixel_rate(const struct intel_crtc_state *crtc_state)
{
u32 pixel_rate = crtc_state->base.adjusted_mode.crtc_clock;
- u32 pfit_size = crtc_state->pch_pfit.size;
- u64 pipe_w, pipe_h, pfit_w, pfit_h;
+ unsigned int pipe_w, pipe_h, pfit_w, pfit_h;
/*
* We only use IF-ID interlacing. If we ever use
@@ -7373,8 +7381,9 @@ static u32 ilk_pipe_pixel_rate(const struct intel_crtc_state *crtc_state)
pipe_w = crtc_state->pipe_src_w;
pipe_h = crtc_state->pipe_src_h;
- pfit_w = (pfit_size >> 16) & 0xFFFF;
- pfit_h = pfit_size & 0xFFFF;
+ pfit_w = drm_rect_width(&crtc_state->pch_pfit.dst);
+ pfit_h = drm_rect_height(&crtc_state->pch_pfit.dst);
+
if (pipe_w < pfit_w)
pipe_w = pfit_w;
if (pipe_h < pfit_h)
@@ -9736,6 +9745,18 @@ static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
&pipe_config->fdi_m_n, NULL);
}
+static void ilk_get_pfit_pos_size(struct intel_crtc_state *crtc_state,
+ u32 pos, u32 size)
+{
+ crtc_state->pch_pfit.dst.x1 = pos >> 16;
+ crtc_state->pch_pfit.dst.y1 = pos & 0xffff;
+
+ crtc_state->pch_pfit.dst.x2 = (size >> 16) +
+ crtc_state->pch_pfit.dst.x1;
+ crtc_state->pch_pfit.dst.y2 = (size & 0xffff) +
+ crtc_state->pch_pfit.dst.y1;
+}
+
static void skylake_get_pfit_config(struct intel_crtc_state *crtc_state)
{
struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
@@ -9754,8 +9775,11 @@ static void skylake_get_pfit_config(struct intel_crtc_state *crtc_state)
id = i;
crtc_state->pch_pfit.enabled = true;
- crtc_state->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
- crtc_state->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
+
+ ilk_get_pfit_pos_size(crtc_state,
+ I915_READ(SKL_PS_WIN_POS(crtc->pipe, i)),
+ I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i)));
+
scaler_state->scalers[i].in_use = true;
break;
}
@@ -9913,8 +9937,10 @@ static void ironlake_get_pfit_config(struct intel_crtc_state *crtc_state)
(tmp & PF_PIPE_SEL_MASK_IVB) != PF_PIPE_SEL_IVB(crtc->pipe));
crtc_state->pch_pfit.enabled = true;
- crtc_state->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
- crtc_state->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
+
+ ilk_get_pfit_pos_size(crtc_state,
+ I915_READ(PF_WIN_POS(crtc->pipe)),
+ I915_READ(PF_WIN_SZ(crtc->pipe)));
}
static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
@@ -12126,9 +12152,8 @@ static void intel_dump_pipe_config(const struct intel_crtc_state *pipe_config,
pipe_config->gmch_pfit.pgm_ratios,
pipe_config->gmch_pfit.lvds_border_bits);
else
- DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s, force thru: %s\n",
- pipe_config->pch_pfit.pos,
- pipe_config->pch_pfit.size,
+ DRM_DEBUG_KMS("pch pfit: " DRM_RECT_FMT ", %s, force thru: %s\n",
+ DRM_RECT_ARG(&pipe_config->pch_pfit.dst),
enableddisabled(pipe_config->pch_pfit.enabled),
yesno(pipe_config->pch_pfit.force_thru));
@@ -12779,8 +12804,10 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
PIPE_CONF_CHECK_BOOL(pch_pfit.enabled);
if (current_config->pch_pfit.enabled) {
- PIPE_CONF_CHECK_X(pch_pfit.pos);
- PIPE_CONF_CHECK_X(pch_pfit.size);
+ PIPE_CONF_CHECK_I(pch_pfit.dst.x1);
+ PIPE_CONF_CHECK_I(pch_pfit.dst.y1);
+ PIPE_CONF_CHECK_I(pch_pfit.dst.x2);
+ PIPE_CONF_CHECK_I(pch_pfit.dst.y2);
}
PIPE_CONF_CHECK_I(scaler_state.scaler_id);
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 61277a87dbe7..87ed7650ee27 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -902,8 +902,7 @@ struct intel_crtc_state {
/* Panel fitter placement and size for Ironlake+ */
struct {
- u32 pos;
- u32 size;
+ struct drm_rect dst;
bool enabled;
bool force_thru;
} pch_pfit;
diff --git a/drivers/gpu/drm/i915/display/intel_panel.c b/drivers/gpu/drm/i915/display/intel_panel.c
index 4601416c603e..8f2e7750e8f4 100644
--- a/drivers/gpu/drm/i915/display/intel_panel.c
+++ b/drivers/gpu/drm/i915/display/intel_panel.c
@@ -179,13 +179,13 @@ intel_pch_panel_fitting(struct intel_crtc *intel_crtc,
int fitting_mode)
{
const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
- int x = 0, y = 0, width = 0, height = 0;
+ int x, y, width, height;
/* Native modes don't need fitting */
if (adjusted_mode->crtc_hdisplay == pipe_config->pipe_src_w &&
adjusted_mode->crtc_vdisplay == pipe_config->pipe_src_h &&
pipe_config->output_format != INTEL_OUTPUT_FORMAT_YCBCR420)
- goto done;
+ return;
switch (fitting_mode) {
case DRM_MODE_SCALE_CENTER:
@@ -231,14 +231,15 @@ intel_pch_panel_fitting(struct intel_crtc *intel_crtc,
break;
default:
- WARN(1, "bad panel fit mode: %d\n", fitting_mode);
+ MISSING_CASE(fitting_mode);
return;
}
-done:
- pipe_config->pch_pfit.pos = (x << 16) | y;
- pipe_config->pch_pfit.size = (width << 16) | height;
- pipe_config->pch_pfit.enabled = pipe_config->pch_pfit.size != 0;
+ pipe_config->pch_pfit.dst.x1 = x;
+ pipe_config->pch_pfit.dst.y1 = y;
+ pipe_config->pch_pfit.dst.x2 = x + width;
+ pipe_config->pch_pfit.dst.y2 = y + height;
+ pipe_config->pch_pfit.enabled = true;
}
static void
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 9f3184e0d2f1..2687f7a047f3 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4106,7 +4106,6 @@ skl_pipe_downscale_amount(const struct intel_crtc_state *crtc_state)
{
uint_fixed_16_16_t pipe_downscale = u32_to_fixed16(1);
u32 src_w, src_h, dst_w, dst_h;
- u32 pfit_size = crtc_state->pch_pfit.size;
uint_fixed_16_16_t fp_w_ratio, fp_h_ratio;
uint_fixed_16_16_t downscale_h, downscale_w;
@@ -4116,8 +4115,8 @@ skl_pipe_downscale_amount(const struct intel_crtc_state *crtc_state)
src_w = crtc_state->pipe_src_w;
src_h = crtc_state->pipe_src_h;
- dst_w = pfit_size >> 16;
- dst_h = pfit_size & 0xffff;
+ dst_w = drm_rect_width(&crtc_state->pch_pfit.dst);
+ dst_h = drm_rect_height(&crtc_state->pch_pfit.dst);
if (!dst_w || !dst_h)
return pipe_downscale;
--
2.21.0
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 27+ messages in thread* [PATCH 07/15] drm/i915: Check pipe source size against pfit limits
2019-09-04 16:26 [PATCH 00/15] drm/i915: Expose margin connector properties for underscan Ville Syrjala
` (6 preceding siblings ...)
2019-09-04 16:26 ` [PATCH 06/15] drm/i915: Use drm_rect to store the pfit window pos/size Ville Syrjala
@ 2019-09-04 16:26 ` Ville Syrjala
2019-09-05 10:37 ` [PATCH v2 " Ville Syrjala
2019-09-04 16:26 ` [PATCH 08/15] drm/i915: Check pfit scaling factors Ville Syrjala
` (13 subsequent siblings)
21 siblings, 1 reply; 27+ messages in thread
From: Ville Syrjala @ 2019-09-04 16:26 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
The panel fitter imposes extra limits on the maximum pipe source
size we can use. Check for that.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 56 ++++++++++++++++++++
1 file changed, 56 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 348071db8b4c..09bb8d9254cb 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -11768,6 +11768,56 @@ static bool c8_planes_changed(const struct intel_crtc_state *new_crtc_state)
return !old_crtc_state->c8_planes != !new_crtc_state->c8_planes;
}
+static int intel_pch_pfit_check_src_size(const struct intel_crtc_state *crtc_state)
+{
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ int max_src_w, max_src_h;
+
+ if (INTEL_GEN(dev_priv) >= 11) {
+ max_src_w = 5120;
+ max_src_h = 4320;
+ } else if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) {
+ max_src_w = crtc->pipe == PIPE_A ? 5120 : 4096;
+ max_src_h = 4096;
+ } else if (INTEL_GEN(dev_priv) >= 8) {
+ max_src_w = 4096;
+ max_src_h = 4096;
+ } else if (INTEL_GEN(dev_priv) >= 7) {
+ /*
+ * PF0 7x5 capable
+ * PF1 3x3 capable (could be switched to 7x5
+ * mode on HSW when PF2 unused)
+ * PF2 3x3 capable
+ *
+ * This assumes we use a 1:1 mapping between pipe and PF.
+ */
+ max_src_w = crtc->pipe == PIPE_A ? 4096 : 2048;
+ max_src_h = 4096;
+ } else {
+ max_src_w = 4096;
+ max_src_h = 4096;
+ }
+
+ if (crtc_state->pipe_src_w > max_src_w ||
+ crtc_state->pipe_src_h > max_src_h) {
+ DRM_DEBUG_KMS("pipe %c source size (%dx%d) exceeds pfit max (%dx%d)\n",
+ pipe_name(crtc->pipe), crtc_state->pipe_src_w,
+ crtc_state->pipe_src_h, max_src_w, max_src_h);
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static int intel_pch_pfit_check(const struct intel_crtc_state *crtc_state)
+{
+ if (!crtc_state->pch_pfit.enabled)
+ return 0;
+
+ return intel_pch_pfit_check_src_size(crtc_state);
+}
+
static int intel_crtc_atomic_check(struct drm_crtc *crtc,
struct drm_crtc_state *crtc_state)
{
@@ -11791,6 +11841,12 @@ static int intel_crtc_atomic_check(struct drm_crtc *crtc,
return ret;
}
+ if (!HAS_GMCH(dev_priv)) {
+ ret = intel_pch_pfit_check(pipe_config);
+ if (ret)
+ return ret;
+ }
+
/*
* May need to update pipe gamma enable bits
* when C8 planes are getting enabled/disabled.
--
2.21.0
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 27+ messages in thread* [PATCH v2 07/15] drm/i915: Check pipe source size against pfit limits
2019-09-04 16:26 ` [PATCH 07/15] drm/i915: Check pipe source size against pfit limits Ville Syrjala
@ 2019-09-05 10:37 ` Ville Syrjala
2019-09-05 12:30 ` Ville Syrjälä
0 siblings, 1 reply; 27+ messages in thread
From: Ville Syrjala @ 2019-09-05 10:37 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
The panel fitter imposes extra limits on the maximum pipe source
size we can use. Check for that.
v2: Skip the checks if the crtc is disabled
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 57 ++++++++++++++++++++
1 file changed, 57 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 348071db8b4c..ccec2b54677d 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -11768,6 +11768,57 @@ static bool c8_planes_changed(const struct intel_crtc_state *new_crtc_state)
return !old_crtc_state->c8_planes != !new_crtc_state->c8_planes;
}
+static int intel_pch_pfit_check_src_size(const struct intel_crtc_state *crtc_state)
+{
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ int max_src_w, max_src_h;
+
+ if (INTEL_GEN(dev_priv) >= 11) {
+ max_src_w = 5120;
+ max_src_h = 4320;
+ } else if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) {
+ max_src_w = crtc->pipe == PIPE_A ? 5120 : 4096;
+ max_src_h = 4096;
+ } else if (INTEL_GEN(dev_priv) >= 8) {
+ max_src_w = 4096;
+ max_src_h = 4096;
+ } else if (INTEL_GEN(dev_priv) >= 7) {
+ /*
+ * PF0 7x5 capable
+ * PF1 3x3 capable (could be switched to 7x5
+ * mode on HSW when PF2 unused)
+ * PF2 3x3 capable
+ *
+ * This assumes we use a 1:1 mapping between pipe and PF.
+ */
+ max_src_w = crtc->pipe == PIPE_A ? 4096 : 2048;
+ max_src_h = 4096;
+ } else {
+ max_src_w = 4096;
+ max_src_h = 4096;
+ }
+
+ if (crtc_state->pipe_src_w > max_src_w ||
+ crtc_state->pipe_src_h > max_src_h) {
+ DRM_DEBUG_KMS("pipe %c source size (%dx%d) exceeds pfit max (%dx%d)\n",
+ pipe_name(crtc->pipe), crtc_state->pipe_src_w,
+ crtc_state->pipe_src_h, max_src_w, max_src_h);
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static int intel_pch_pfit_check(const struct intel_crtc_state *crtc_state)
+{
+ if (!crtc_state->base.enable ||
+ !crtc_state->pch_pfit.enabled)
+ return 0;
+
+ return intel_pch_pfit_check_src_size(crtc_state);
+}
+
static int intel_crtc_atomic_check(struct drm_crtc *crtc,
struct drm_crtc_state *crtc_state)
{
@@ -11791,6 +11842,12 @@ static int intel_crtc_atomic_check(struct drm_crtc *crtc,
return ret;
}
+ if (!HAS_GMCH(dev_priv)) {
+ ret = intel_pch_pfit_check(pipe_config);
+ if (ret)
+ return ret;
+ }
+
/*
* May need to update pipe gamma enable bits
* when C8 planes are getting enabled/disabled.
--
2.21.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 27+ messages in thread* Re: [PATCH v2 07/15] drm/i915: Check pipe source size against pfit limits
2019-09-05 10:37 ` [PATCH v2 " Ville Syrjala
@ 2019-09-05 12:30 ` Ville Syrjälä
0 siblings, 0 replies; 27+ messages in thread
From: Ville Syrjälä @ 2019-09-05 12:30 UTC (permalink / raw)
To: intel-gfx
On Thu, Sep 05, 2019 at 01:37:06PM +0300, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> The panel fitter imposes extra limits on the maximum pipe source
> size we can use. Check for that.
>
> v2: Skip the checks if the crtc is disabled
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 57 ++++++++++++++++++++
> 1 file changed, 57 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 348071db8b4c..ccec2b54677d 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -11768,6 +11768,57 @@ static bool c8_planes_changed(const struct intel_crtc_state *new_crtc_state)
> return !old_crtc_state->c8_planes != !new_crtc_state->c8_planes;
> }
>
> +static int intel_pch_pfit_check_src_size(const struct intel_crtc_state *crtc_state)
> +{
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> + int max_src_w, max_src_h;
> +
> + if (INTEL_GEN(dev_priv) >= 11) {
> + max_src_w = 5120;
> + max_src_h = 4320;
> + } else if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) {
> + max_src_w = crtc->pipe == PIPE_A ? 5120 : 4096;
> + max_src_h = 4096;
> + } else if (INTEL_GEN(dev_priv) >= 8) {
> + max_src_w = 4096;
> + max_src_h = 4096;
> + } else if (INTEL_GEN(dev_priv) >= 7) {
> + /*
> + * PF0 7x5 capable
> + * PF1 3x3 capable (could be switched to 7x5
> + * mode on HSW when PF2 unused)
> + * PF2 3x3 capable
> + *
> + * This assumes we use a 1:1 mapping between pipe and PF.
> + */
> + max_src_w = crtc->pipe == PIPE_A ? 4096 : 2048;
> + max_src_h = 4096;
> + } else {
> + max_src_w = 4096;
> + max_src_h = 4096;
> + }
> +
> + if (crtc_state->pipe_src_w > max_src_w ||
> + crtc_state->pipe_src_h > max_src_h) {
> + DRM_DEBUG_KMS("pipe %c source size (%dx%d) exceeds pfit max (%dx%d)\n",
> + pipe_name(crtc->pipe), crtc_state->pipe_src_w,
> + crtc_state->pipe_src_h, max_src_w, max_src_h);
> + return -EINVAL;
> + }
> +
> + return 0;
> +}
> +
> +static int intel_pch_pfit_check(const struct intel_crtc_state *crtc_state)
> +{
> + if (!crtc_state->base.enable ||
We might actually consider clearing most of the crtc state for disabled
pipes. Would avoid having to sprinkle these checks all over the place.
But I haven't really thought through the implications of doing that.
> + !crtc_state->pch_pfit.enabled)
> + return 0;
> +
> + return intel_pch_pfit_check_src_size(crtc_state);
> +}
> +
> static int intel_crtc_atomic_check(struct drm_crtc *crtc,
> struct drm_crtc_state *crtc_state)
> {
> @@ -11791,6 +11842,12 @@ static int intel_crtc_atomic_check(struct drm_crtc *crtc,
> return ret;
> }
>
> + if (!HAS_GMCH(dev_priv)) {
> + ret = intel_pch_pfit_check(pipe_config);
> + if (ret)
> + return ret;
> + }
> +
> /*
> * May need to update pipe gamma enable bits
> * when C8 planes are getting enabled/disabled.
> --
> 2.21.0
--
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 27+ messages in thread
* [PATCH 08/15] drm/i915: Check pfit scaling factors
2019-09-04 16:26 [PATCH 00/15] drm/i915: Expose margin connector properties for underscan Ville Syrjala
` (7 preceding siblings ...)
2019-09-04 16:26 ` [PATCH 07/15] drm/i915: Check pipe source size against pfit limits Ville Syrjala
@ 2019-09-04 16:26 ` Ville Syrjala
2019-09-05 10:37 ` [PATCH v2 " Ville Syrjala
2019-09-04 16:26 ` [PATCH 09/15] drm/i915: Check pfit minimum timings Ville Syrjala
` (12 subsequent siblings)
21 siblings, 1 reply; 27+ messages in thread
From: Ville Syrjala @ 2019-09-04 16:26 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Make sure we're not exceeding the max scaling factors for the panel
fitter.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 46 +++++++++++++++++++-
1 file changed, 45 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 09bb8d9254cb..65fdabcb201a 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -11810,12 +11810,56 @@ static int intel_pch_pfit_check_src_size(const struct intel_crtc_state *crtc_sta
return 0;
}
+static int intel_pch_pfit_check_scaling(const struct intel_crtc_state *crtc_state)
+{
+ struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
+ struct drm_rect src = {
+ .x2 = crtc_state->pipe_src_w << 16,
+ .y2 = crtc_state->pipe_src_h << 16,
+ };
+ const struct drm_rect *dst = &crtc_state->pch_pfit.dst;
+ int ret, max_scale;
+
+ if (INTEL_GEN(dev_priv) >= 9) {
+ if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
+ max_scale = 0x18000 - 1; /* < 1.5 */
+ else
+ max_scale = 0x30000 - 1; /* < 3.0 */
+ } else {
+ max_scale = 0x12000; /* 1.125 */
+ }
+
+ ret = drm_rect_calc_hscale(&src, dst, 0, max_scale);
+ if (ret < 0) {
+ DRM_DEBUG_KMS("pfit horizontal downscale (%d->%d) exceeds max (0x%x)\n",
+ crtc_state->pipe_src_w,
+ drm_rect_width(dst), max_scale);
+ return ret;
+ }
+
+ ret = drm_rect_calc_vscale(&src, dst, 0, max_scale);
+ if (ret < 0) {
+ DRM_DEBUG_KMS("pfit vertical downscale (%d->%d) exceeds max (0x%x)\n",
+ crtc_state->pipe_src_h,
+ drm_rect_height(dst), max_scale);
+ return ret;
+ }
+
+ return 0;
+}
+
static int intel_pch_pfit_check(const struct intel_crtc_state *crtc_state)
{
+ int ret;
+
if (!crtc_state->pch_pfit.enabled)
return 0;
- return intel_pch_pfit_check_src_size(crtc_state);
+ ret = intel_pch_pfit_check_src_size(crtc_state);
+ if (ret)
+ return ret;
+
+ return intel_pch_pfit_check_scaling(crtc_state);
}
static int intel_crtc_atomic_check(struct drm_crtc *crtc,
--
2.21.0
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 27+ messages in thread* [PATCH v2 08/15] drm/i915: Check pfit scaling factors
2019-09-04 16:26 ` [PATCH 08/15] drm/i915: Check pfit scaling factors Ville Syrjala
@ 2019-09-05 10:37 ` Ville Syrjala
0 siblings, 0 replies; 27+ messages in thread
From: Ville Syrjala @ 2019-09-05 10:37 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Make sure we're not exceeding the max scaling factors for the panel
fitter.
v2: Rebase due to crtc enable check
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 46 +++++++++++++++++++-
1 file changed, 45 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index ccec2b54677d..f7f93af55ec5 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -11810,13 +11810,57 @@ static int intel_pch_pfit_check_src_size(const struct intel_crtc_state *crtc_sta
return 0;
}
+static int intel_pch_pfit_check_scaling(const struct intel_crtc_state *crtc_state)
+{
+ struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
+ struct drm_rect src = {
+ .x2 = crtc_state->pipe_src_w << 16,
+ .y2 = crtc_state->pipe_src_h << 16,
+ };
+ const struct drm_rect *dst = &crtc_state->pch_pfit.dst;
+ int ret, max_scale;
+
+ if (INTEL_GEN(dev_priv) >= 9) {
+ if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
+ max_scale = 0x18000 - 1; /* < 1.5 */
+ else
+ max_scale = 0x30000 - 1; /* < 3.0 */
+ } else {
+ max_scale = 0x12000; /* 1.125 */
+ }
+
+ ret = drm_rect_calc_hscale(&src, dst, 0, max_scale);
+ if (ret < 0) {
+ DRM_DEBUG_KMS("pfit horizontal downscale (%d->%d) exceeds max (0x%x)\n",
+ crtc_state->pipe_src_w,
+ drm_rect_width(dst), max_scale);
+ return ret;
+ }
+
+ ret = drm_rect_calc_vscale(&src, dst, 0, max_scale);
+ if (ret < 0) {
+ DRM_DEBUG_KMS("pfit vertical downscale (%d->%d) exceeds max (0x%x)\n",
+ crtc_state->pipe_src_h,
+ drm_rect_height(dst), max_scale);
+ return ret;
+ }
+
+ return 0;
+}
+
static int intel_pch_pfit_check(const struct intel_crtc_state *crtc_state)
{
+ int ret;
+
if (!crtc_state->base.enable ||
!crtc_state->pch_pfit.enabled)
return 0;
- return intel_pch_pfit_check_src_size(crtc_state);
+ ret = intel_pch_pfit_check_src_size(crtc_state);
+ if (ret)
+ return ret;
+
+ return intel_pch_pfit_check_scaling(crtc_state);
}
static int intel_crtc_atomic_check(struct drm_crtc *crtc,
--
2.21.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 27+ messages in thread
* [PATCH 09/15] drm/i915: Check pfit minimum timings
2019-09-04 16:26 [PATCH 00/15] drm/i915: Expose margin connector properties for underscan Ville Syrjala
` (8 preceding siblings ...)
2019-09-04 16:26 ` [PATCH 08/15] drm/i915: Check pfit scaling factors Ville Syrjala
@ 2019-09-04 16:26 ` Ville Syrjala
2019-09-05 10:38 ` [PATCH v2 " Ville Syrjala
2019-09-04 16:26 ` [PATCH 10/15] drm/i915: s/pipe_config/crtc_state/ in pfit functions Ville Syrjala
` (11 subsequent siblings)
21 siblings, 1 reply; 27+ messages in thread
From: Ville Syrjala @ 2019-09-04 16:26 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Transcoder hdisplay/vdisplay have documented minimum limits
when using the panel fitter. Enforce those limits.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 51 ++++++++++++++++++--
1 file changed, 47 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 65fdabcb201a..c2bd64b3ed54 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -11768,6 +11768,17 @@ static bool c8_planes_changed(const struct intel_crtc_state *new_crtc_state)
return !old_crtc_state->c8_planes != !new_crtc_state->c8_planes;
}
+static int intel_pch_pfit_check_timings(const struct intel_crtc_state *crtc_state)
+{
+ const struct drm_display_mode *adjusted_mode =
+ &crtc_state->base.adjusted_mode;
+
+ if (adjusted_mode->crtc_vdisplay < 7)
+ return -EINVAL;
+
+ return 0;
+}
+
static int intel_pch_pfit_check_src_size(const struct intel_crtc_state *crtc_state)
{
struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
@@ -11855,6 +11866,10 @@ static int intel_pch_pfit_check(const struct intel_crtc_state *crtc_state)
if (!crtc_state->pch_pfit.enabled)
return 0;
+ ret = intel_pch_pfit_check_timings(crtc_state);
+ if (ret)
+ return ret;
+
ret = intel_pch_pfit_check_src_size(crtc_state);
if (ret)
return ret;
@@ -11862,6 +11877,33 @@ static int intel_pch_pfit_check(const struct intel_crtc_state *crtc_state)
return intel_pch_pfit_check_scaling(crtc_state);
}
+static int intel_gmch_pfit_check_timings(const struct intel_crtc_state *crtc_state)
+{
+ struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
+ const struct drm_display_mode *adjusted_mode =
+ &crtc_state->base.adjusted_mode;
+ int min;
+
+ if (INTEL_GEN(dev_priv) >= 4)
+ min = 3;
+ else
+ min = 2;
+
+ if (adjusted_mode->crtc_hdisplay < min ||
+ adjusted_mode->crtc_vdisplay < min)
+ return -EINVAL;
+
+ return 0;
+}
+
+static int intel_gmch_pfit_check(const struct intel_crtc_state *crtc_state)
+{
+ if ((crtc_state->gmch_pfit.control & PFIT_ENABLE) == 0)
+ return 0;
+
+ return intel_gmch_pfit_check_timings(crtc_state);
+}
+
static int intel_crtc_atomic_check(struct drm_crtc *crtc,
struct drm_crtc_state *crtc_state)
{
@@ -11885,11 +11927,12 @@ static int intel_crtc_atomic_check(struct drm_crtc *crtc,
return ret;
}
- if (!HAS_GMCH(dev_priv)) {
+ if (HAS_GMCH(dev_priv))
+ ret = intel_gmch_pfit_check(pipe_config);
+ else
ret = intel_pch_pfit_check(pipe_config);
- if (ret)
- return ret;
- }
+ if (ret)
+ return ret;
/*
* May need to update pipe gamma enable bits
--
2.21.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 27+ messages in thread* [PATCH v2 09/15] drm/i915: Check pfit minimum timings
2019-09-04 16:26 ` [PATCH 09/15] drm/i915: Check pfit minimum timings Ville Syrjala
@ 2019-09-05 10:38 ` Ville Syrjala
0 siblings, 0 replies; 27+ messages in thread
From: Ville Syrjala @ 2019-09-05 10:38 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Transcoder hdisplay/vdisplay have documented minimum limits
when using the panel fitter. Enforce those limits.
v2: Skip the checks if the crtc is disabled
Add debugs for the failures
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 63 ++++++++++++++++++--
1 file changed, 59 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index f7f93af55ec5..2c523f500cb4 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -11768,6 +11768,20 @@ static bool c8_planes_changed(const struct intel_crtc_state *new_crtc_state)
return !old_crtc_state->c8_planes != !new_crtc_state->c8_planes;
}
+static int intel_pch_pfit_check_timings(const struct intel_crtc_state *crtc_state)
+{
+ const struct drm_display_mode *adjusted_mode =
+ &crtc_state->base.adjusted_mode;
+
+ if (adjusted_mode->crtc_vdisplay < 7) {
+ DRM_DEBUG_KMS("Vertical active (%d) below minimum (%d) for pfit\n",
+ adjusted_mode->crtc_vdisplay, 7);
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
static int intel_pch_pfit_check_src_size(const struct intel_crtc_state *crtc_state)
{
struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
@@ -11856,6 +11870,10 @@ static int intel_pch_pfit_check(const struct intel_crtc_state *crtc_state)
!crtc_state->pch_pfit.enabled)
return 0;
+ ret = intel_pch_pfit_check_timings(crtc_state);
+ if (ret)
+ return ret;
+
ret = intel_pch_pfit_check_src_size(crtc_state);
if (ret)
return ret;
@@ -11863,6 +11881,42 @@ static int intel_pch_pfit_check(const struct intel_crtc_state *crtc_state)
return intel_pch_pfit_check_scaling(crtc_state);
}
+static int intel_gmch_pfit_check_timings(const struct intel_crtc_state *crtc_state)
+{
+ struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
+ const struct drm_display_mode *adjusted_mode =
+ &crtc_state->base.adjusted_mode;
+ int min;
+
+ if (INTEL_GEN(dev_priv) >= 4)
+ min = 3;
+ else
+ min = 2;
+
+ if (adjusted_mode->crtc_hdisplay < min) {
+ DRM_DEBUG_KMS("Horizontal active (%d) below minimum (%d) for pfit\n",
+ adjusted_mode->crtc_hdisplay, min);
+ return -EINVAL;
+ }
+
+ if (adjusted_mode->crtc_vdisplay < min) {
+ DRM_DEBUG_KMS("Vertical active (%d) below minimum (%d) for pfit\n",
+ adjusted_mode->crtc_vdisplay, min);
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static int intel_gmch_pfit_check(const struct intel_crtc_state *crtc_state)
+{
+ if (!crtc_state->base.enable ||
+ (crtc_state->gmch_pfit.control & PFIT_ENABLE) == 0)
+ return 0;
+
+ return intel_gmch_pfit_check_timings(crtc_state);
+}
+
static int intel_crtc_atomic_check(struct drm_crtc *crtc,
struct drm_crtc_state *crtc_state)
{
@@ -11886,11 +11940,12 @@ static int intel_crtc_atomic_check(struct drm_crtc *crtc,
return ret;
}
- if (!HAS_GMCH(dev_priv)) {
+ if (HAS_GMCH(dev_priv))
+ ret = intel_gmch_pfit_check(pipe_config);
+ else
ret = intel_pch_pfit_check(pipe_config);
- if (ret)
- return ret;
- }
+ if (ret)
+ return ret;
/*
* May need to update pipe gamma enable bits
--
2.21.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 27+ messages in thread
* [PATCH 10/15] drm/i915: s/pipe_config/crtc_state/ in pfit functions
2019-09-04 16:26 [PATCH 00/15] drm/i915: Expose margin connector properties for underscan Ville Syrjala
` (9 preceding siblings ...)
2019-09-04 16:26 ` [PATCH 09/15] drm/i915: Check pfit minimum timings Ville Syrjala
@ 2019-09-04 16:26 ` Ville Syrjala
2019-09-04 16:26 ` [PATCH 11/15] drm/i915: Pass connector state to pfit calculations Ville Syrjala
` (10 subsequent siblings)
21 siblings, 0 replies; 27+ messages in thread
From: Ville Syrjala @ 2019-09-04 16:26 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Follow the new naming convention and call the crtc state
"crtc_state", and while at it drop the redundant crtc argument.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/icl_dsi.c | 3 +-
drivers/gpu/drm/i915/display/intel_dp.c | 7 +-
drivers/gpu/drm/i915/display/intel_hdmi.c | 5 +-
drivers/gpu/drm/i915/display/intel_lvds.c | 4 +-
drivers/gpu/drm/i915/display/intel_panel.c | 98 +++++++++++-----------
drivers/gpu/drm/i915/display/intel_panel.h | 6 +-
drivers/gpu/drm/i915/display/vlv_dsi.c | 5 +-
7 files changed, 60 insertions(+), 68 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
index 6e398c33a524..627cbd880224 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -1265,7 +1265,6 @@ static int gen11_dsi_compute_config(struct intel_encoder *encoder,
struct intel_dsi *intel_dsi = container_of(encoder, struct intel_dsi,
base);
struct intel_connector *intel_connector = intel_dsi->attached_connector;
- struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
const struct drm_display_mode *fixed_mode =
intel_connector->panel.fixed_mode;
struct drm_display_mode *adjusted_mode =
@@ -1273,7 +1272,7 @@ static int gen11_dsi_compute_config(struct intel_encoder *encoder,
pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
intel_fixed_panel_mode(fixed_mode, adjusted_mode);
- intel_pch_panel_fitting(crtc, pipe_config, conn_state->scaling_mode);
+ intel_pch_panel_fitting(pipe_config, conn_state->scaling_mode);
adjusted_mode->flags = 0;
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index d333f87d5b39..f6ef3c25c0ed 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -2120,7 +2120,6 @@ intel_dp_ycbcr420_config(struct intel_dp *intel_dp,
const struct drm_display_info *info = &connector->display_info;
const struct drm_display_mode *adjusted_mode =
&crtc_state->base.adjusted_mode;
- struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
if (!drm_mode_is_420_only(info, adjusted_mode) ||
!intel_dp_get_colorimetry_status(intel_dp) ||
@@ -2129,7 +2128,7 @@ intel_dp_ycbcr420_config(struct intel_dp *intel_dp,
crtc_state->output_format = INTEL_OUTPUT_FORMAT_YCBCR420;
- intel_pch_panel_fitting(crtc, crtc_state, DRM_MODE_SCALE_FULLSCREEN);
+ intel_pch_panel_fitting(crtc_state, DRM_MODE_SCALE_FULLSCREEN);
return 0;
}
@@ -2200,10 +2199,10 @@ intel_dp_compute_config(struct intel_encoder *encoder,
adjusted_mode);
if (HAS_GMCH(dev_priv))
- intel_gmch_panel_fitting(intel_crtc, pipe_config,
+ intel_gmch_panel_fitting(pipe_config,
conn_state->scaling_mode);
else
- intel_pch_panel_fitting(intel_crtc, pipe_config,
+ intel_pch_panel_fitting(pipe_config,
conn_state->scaling_mode);
}
diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c
index 4039c2216ae0..c749b04ba477 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
@@ -2267,8 +2267,6 @@ static bool
intel_hdmi_ycbcr420_config(struct drm_connector *connector,
struct intel_crtc_state *config)
{
- struct intel_crtc *intel_crtc = to_intel_crtc(config->base.crtc);
-
if (!connector->ycbcr_420_allowed) {
DRM_ERROR("Platform doesn't support YCBCR420 output\n");
return false;
@@ -2276,8 +2274,7 @@ intel_hdmi_ycbcr420_config(struct drm_connector *connector,
config->output_format = INTEL_OUTPUT_FORMAT_YCBCR420;
- intel_pch_panel_fitting(intel_crtc, config,
- DRM_MODE_SCALE_FULLSCREEN);
+ intel_pch_panel_fitting(config, DRM_MODE_SCALE_FULLSCREEN);
return true;
}
diff --git a/drivers/gpu/drm/i915/display/intel_lvds.c b/drivers/gpu/drm/i915/display/intel_lvds.c
index c786abdc3336..e983035aca63 100644
--- a/drivers/gpu/drm/i915/display/intel_lvds.c
+++ b/drivers/gpu/drm/i915/display/intel_lvds.c
@@ -430,10 +430,10 @@ static int intel_lvds_compute_config(struct intel_encoder *intel_encoder,
if (HAS_PCH_SPLIT(dev_priv)) {
pipe_config->has_pch_encoder = true;
- intel_pch_panel_fitting(intel_crtc, pipe_config,
+ intel_pch_panel_fitting(pipe_config,
conn_state->scaling_mode);
} else {
- intel_gmch_panel_fitting(intel_crtc, pipe_config,
+ intel_gmch_panel_fitting(pipe_config,
conn_state->scaling_mode);
}
diff --git a/drivers/gpu/drm/i915/display/intel_panel.c b/drivers/gpu/drm/i915/display/intel_panel.c
index 8f2e7750e8f4..6f4270ecdebd 100644
--- a/drivers/gpu/drm/i915/display/intel_panel.c
+++ b/drivers/gpu/drm/i915/display/intel_panel.c
@@ -174,23 +174,23 @@ intel_panel_vbt_fixed_mode(struct intel_connector *connector)
/* adjusted_mode has been preset to be the panel's fixed mode */
void
-intel_pch_panel_fitting(struct intel_crtc *intel_crtc,
- struct intel_crtc_state *pipe_config,
+intel_pch_panel_fitting(struct intel_crtc_state *crtc_state,
int fitting_mode)
{
- const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
+ const struct drm_display_mode *adjusted_mode =
+ &crtc_state->base.adjusted_mode;
int x, y, width, height;
/* Native modes don't need fitting */
- if (adjusted_mode->crtc_hdisplay == pipe_config->pipe_src_w &&
- adjusted_mode->crtc_vdisplay == pipe_config->pipe_src_h &&
- pipe_config->output_format != INTEL_OUTPUT_FORMAT_YCBCR420)
+ if (adjusted_mode->crtc_hdisplay == crtc_state->pipe_src_w &&
+ adjusted_mode->crtc_vdisplay == crtc_state->pipe_src_h &&
+ crtc_state->output_format != INTEL_OUTPUT_FORMAT_YCBCR420)
return;
switch (fitting_mode) {
case DRM_MODE_SCALE_CENTER:
- width = pipe_config->pipe_src_w;
- height = pipe_config->pipe_src_h;
+ width = crtc_state->pipe_src_w;
+ height = crtc_state->pipe_src_h;
x = (adjusted_mode->crtc_hdisplay - width + 1)/2;
y = (adjusted_mode->crtc_vdisplay - height + 1)/2;
break;
@@ -199,18 +199,18 @@ intel_pch_panel_fitting(struct intel_crtc *intel_crtc,
/* Scale but preserve the aspect ratio */
{
u32 scaled_width = adjusted_mode->crtc_hdisplay
- * pipe_config->pipe_src_h;
- u32 scaled_height = pipe_config->pipe_src_w
+ * crtc_state->pipe_src_h;
+ u32 scaled_height = crtc_state->pipe_src_w
* adjusted_mode->crtc_vdisplay;
if (scaled_width > scaled_height) { /* pillar */
- width = scaled_height / pipe_config->pipe_src_h;
+ width = scaled_height / crtc_state->pipe_src_h;
if (width & 1)
width++;
x = (adjusted_mode->crtc_hdisplay - width + 1) / 2;
y = 0;
height = adjusted_mode->crtc_vdisplay;
} else if (scaled_width < scaled_height) { /* letter */
- height = scaled_width / pipe_config->pipe_src_w;
+ height = scaled_width / crtc_state->pipe_src_w;
if (height & 1)
height++;
y = (adjusted_mode->crtc_vdisplay - height + 1) / 2;
@@ -235,11 +235,11 @@ intel_pch_panel_fitting(struct intel_crtc *intel_crtc,
return;
}
- pipe_config->pch_pfit.dst.x1 = x;
- pipe_config->pch_pfit.dst.y1 = y;
- pipe_config->pch_pfit.dst.x2 = x + width;
- pipe_config->pch_pfit.dst.y2 = y + height;
- pipe_config->pch_pfit.enabled = true;
+ crtc_state->pch_pfit.dst.x1 = x;
+ crtc_state->pch_pfit.dst.y1 = y;
+ crtc_state->pch_pfit.dst.x2 = x + width;
+ crtc_state->pch_pfit.dst.y2 = y + height;
+ crtc_state->pch_pfit.enabled = true;
}
static void
@@ -298,13 +298,13 @@ static inline u32 panel_fitter_scaling(u32 source, u32 target)
return (FACTOR * ratio + FACTOR/2) / FACTOR;
}
-static void i965_scale_aspect(struct intel_crtc_state *pipe_config,
+static void i965_scale_aspect(struct intel_crtc_state *crtc_state,
u32 *pfit_control)
{
- const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
+ const struct drm_display_mode *adjusted_mode = &crtc_state->base.adjusted_mode;
u32 scaled_width = adjusted_mode->crtc_hdisplay *
- pipe_config->pipe_src_h;
- u32 scaled_height = pipe_config->pipe_src_w *
+ crtc_state->pipe_src_h;
+ u32 scaled_height = crtc_state->pipe_src_w *
adjusted_mode->crtc_vdisplay;
/* 965+ is easy, it does everything in hw */
@@ -314,18 +314,18 @@ static void i965_scale_aspect(struct intel_crtc_state *pipe_config,
else if (scaled_width < scaled_height)
*pfit_control |= PFIT_ENABLE |
PFIT_SCALING_LETTER;
- else if (adjusted_mode->crtc_hdisplay != pipe_config->pipe_src_w)
+ else if (adjusted_mode->crtc_hdisplay != crtc_state->pipe_src_w)
*pfit_control |= PFIT_ENABLE | PFIT_SCALING_AUTO;
}
-static void i9xx_scale_aspect(struct intel_crtc_state *pipe_config,
+static void i9xx_scale_aspect(struct intel_crtc_state *crtc_state,
u32 *pfit_control, u32 *pfit_pgm_ratios,
u32 *border)
{
- struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
+ struct drm_display_mode *adjusted_mode = &crtc_state->base.adjusted_mode;
u32 scaled_width = adjusted_mode->crtc_hdisplay *
- pipe_config->pipe_src_h;
- u32 scaled_height = pipe_config->pipe_src_w *
+ crtc_state->pipe_src_h;
+ u32 scaled_height = crtc_state->pipe_src_w *
adjusted_mode->crtc_vdisplay;
u32 bits;
@@ -337,11 +337,11 @@ static void i9xx_scale_aspect(struct intel_crtc_state *pipe_config,
if (scaled_width > scaled_height) { /* pillar */
centre_horizontally(adjusted_mode,
scaled_height /
- pipe_config->pipe_src_h);
+ crtc_state->pipe_src_h);
*border = LVDS_BORDER_ENABLE;
- if (pipe_config->pipe_src_h != adjusted_mode->crtc_vdisplay) {
- bits = panel_fitter_scaling(pipe_config->pipe_src_h,
+ if (crtc_state->pipe_src_h != adjusted_mode->crtc_vdisplay) {
+ bits = panel_fitter_scaling(crtc_state->pipe_src_h,
adjusted_mode->crtc_vdisplay);
*pfit_pgm_ratios |= (bits << PFIT_HORIZ_SCALE_SHIFT |
@@ -353,11 +353,11 @@ static void i9xx_scale_aspect(struct intel_crtc_state *pipe_config,
} else if (scaled_width < scaled_height) { /* letter */
centre_vertically(adjusted_mode,
scaled_width /
- pipe_config->pipe_src_w);
+ crtc_state->pipe_src_w);
*border = LVDS_BORDER_ENABLE;
- if (pipe_config->pipe_src_w != adjusted_mode->crtc_hdisplay) {
- bits = panel_fitter_scaling(pipe_config->pipe_src_w,
+ if (crtc_state->pipe_src_w != adjusted_mode->crtc_hdisplay) {
+ bits = panel_fitter_scaling(crtc_state->pipe_src_w,
adjusted_mode->crtc_hdisplay);
*pfit_pgm_ratios |= (bits << PFIT_HORIZ_SCALE_SHIFT |
@@ -375,17 +375,17 @@ static void i9xx_scale_aspect(struct intel_crtc_state *pipe_config,
}
}
-void intel_gmch_panel_fitting(struct intel_crtc *intel_crtc,
- struct intel_crtc_state *pipe_config,
+void intel_gmch_panel_fitting(struct intel_crtc_state *crtc_state,
int fitting_mode)
{
- struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
u32 pfit_control = 0, pfit_pgm_ratios = 0, border = 0;
- struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
+ struct drm_display_mode *adjusted_mode = &crtc_state->base.adjusted_mode;
/* Native modes don't need fitting */
- if (adjusted_mode->crtc_hdisplay == pipe_config->pipe_src_w &&
- adjusted_mode->crtc_vdisplay == pipe_config->pipe_src_h)
+ if (adjusted_mode->crtc_hdisplay == crtc_state->pipe_src_w &&
+ adjusted_mode->crtc_vdisplay == crtc_state->pipe_src_h)
goto out;
switch (fitting_mode) {
@@ -394,16 +394,16 @@ void intel_gmch_panel_fitting(struct intel_crtc *intel_crtc,
* For centered modes, we have to calculate border widths &
* heights and modify the values programmed into the CRTC.
*/
- centre_horizontally(adjusted_mode, pipe_config->pipe_src_w);
- centre_vertically(adjusted_mode, pipe_config->pipe_src_h);
+ centre_horizontally(adjusted_mode, crtc_state->pipe_src_w);
+ centre_vertically(adjusted_mode, crtc_state->pipe_src_h);
border = LVDS_BORDER_ENABLE;
break;
case DRM_MODE_SCALE_ASPECT:
/* Scale but preserve the aspect ratio */
if (INTEL_GEN(dev_priv) >= 4)
- i965_scale_aspect(pipe_config, &pfit_control);
+ i965_scale_aspect(crtc_state, &pfit_control);
else
- i9xx_scale_aspect(pipe_config, &pfit_control,
+ i9xx_scale_aspect(crtc_state, &pfit_control,
&pfit_pgm_ratios, &border);
break;
case DRM_MODE_SCALE_FULLSCREEN:
@@ -411,8 +411,8 @@ void intel_gmch_panel_fitting(struct intel_crtc *intel_crtc,
* Full scaling, even if it changes the aspect ratio.
* Fortunately this is all done for us in hw.
*/
- if (pipe_config->pipe_src_h != adjusted_mode->crtc_vdisplay ||
- pipe_config->pipe_src_w != adjusted_mode->crtc_hdisplay) {
+ if (crtc_state->pipe_src_h != adjusted_mode->crtc_vdisplay ||
+ crtc_state->pipe_src_w != adjusted_mode->crtc_hdisplay) {
pfit_control |= PFIT_ENABLE;
if (INTEL_GEN(dev_priv) >= 4)
pfit_control |= PFIT_SCALING_AUTO;
@@ -431,7 +431,7 @@ void intel_gmch_panel_fitting(struct intel_crtc *intel_crtc,
/* 965+ wants fuzzy fitting */
/* FIXME: handle multiple panels by failing gracefully */
if (INTEL_GEN(dev_priv) >= 4)
- pfit_control |= PFIT_PIPE(intel_crtc->pipe) | PFIT_FILTER_FUZZY;
+ pfit_control |= PFIT_PIPE(crtc->pipe) | PFIT_FILTER_FUZZY;
out:
if ((pfit_control & PFIT_ENABLE) == 0) {
@@ -440,12 +440,12 @@ void intel_gmch_panel_fitting(struct intel_crtc *intel_crtc,
}
/* Make sure pre-965 set dither correctly for 18bpp panels. */
- if (INTEL_GEN(dev_priv) < 4 && pipe_config->pipe_bpp == 18)
+ if (INTEL_GEN(dev_priv) < 4 && crtc_state->pipe_bpp == 18)
pfit_control |= PANEL_8TO6_DITHER_ENABLE;
- pipe_config->gmch_pfit.control = pfit_control;
- pipe_config->gmch_pfit.pgm_ratios = pfit_pgm_ratios;
- pipe_config->gmch_pfit.lvds_border_bits = border;
+ crtc_state->gmch_pfit.control = pfit_control;
+ crtc_state->gmch_pfit.pgm_ratios = pfit_pgm_ratios;
+ crtc_state->gmch_pfit.lvds_border_bits = border;
}
/**
diff --git a/drivers/gpu/drm/i915/display/intel_panel.h b/drivers/gpu/drm/i915/display/intel_panel.h
index cedeea443336..e1804e6e8325 100644
--- a/drivers/gpu/drm/i915/display/intel_panel.h
+++ b/drivers/gpu/drm/i915/display/intel_panel.h
@@ -25,11 +25,9 @@ int intel_panel_init(struct intel_panel *panel,
void intel_panel_fini(struct intel_panel *panel);
void intel_fixed_panel_mode(const struct drm_display_mode *fixed_mode,
struct drm_display_mode *adjusted_mode);
-void intel_pch_panel_fitting(struct intel_crtc *crtc,
- struct intel_crtc_state *pipe_config,
+void intel_pch_panel_fitting(struct intel_crtc_state *crtc_state,
int fitting_mode);
-void intel_gmch_panel_fitting(struct intel_crtc *crtc,
- struct intel_crtc_state *pipe_config,
+void intel_gmch_panel_fitting(struct intel_crtc_state *crtc_state,
int fitting_mode);
void intel_panel_set_backlight_acpi(const struct drm_connector_state *conn_state,
u32 level, u32 max);
diff --git a/drivers/gpu/drm/i915/display/vlv_dsi.c b/drivers/gpu/drm/i915/display/vlv_dsi.c
index 50064cde0724..6a20c4169a53 100644
--- a/drivers/gpu/drm/i915/display/vlv_dsi.c
+++ b/drivers/gpu/drm/i915/display/vlv_dsi.c
@@ -261,7 +261,6 @@ static int intel_dsi_compute_config(struct intel_encoder *encoder,
struct intel_dsi *intel_dsi = container_of(encoder, struct intel_dsi,
base);
struct intel_connector *intel_connector = intel_dsi->attached_connector;
- struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
const struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
int ret;
@@ -273,10 +272,10 @@ static int intel_dsi_compute_config(struct intel_encoder *encoder,
intel_fixed_panel_mode(fixed_mode, adjusted_mode);
if (HAS_GMCH(dev_priv))
- intel_gmch_panel_fitting(crtc, pipe_config,
+ intel_gmch_panel_fitting(pipe_config,
conn_state->scaling_mode);
else
- intel_pch_panel_fitting(crtc, pipe_config,
+ intel_pch_panel_fitting(pipe_config,
conn_state->scaling_mode);
}
--
2.21.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 27+ messages in thread* [PATCH 11/15] drm/i915: Pass connector state to pfit calculations
2019-09-04 16:26 [PATCH 00/15] drm/i915: Expose margin connector properties for underscan Ville Syrjala
` (10 preceding siblings ...)
2019-09-04 16:26 ` [PATCH 10/15] drm/i915: s/pipe_config/crtc_state/ in pfit functions Ville Syrjala
@ 2019-09-04 16:26 ` Ville Syrjala
2019-09-04 16:26 ` [PATCH 12/15] drm/i915: Have pfit calculations return an error code Ville Syrjala
` (9 subsequent siblings)
21 siblings, 0 replies; 27+ messages in thread
From: Ville Syrjala @ 2019-09-04 16:26 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Pass the entire connector state to intel_{gmch,pch}_panel_fitting().
For now we just need to get at .scaling_mode but in the future we'll
want access to the margin properties as well.
v2: Deal with intel_dp_ycbcr420_config()
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/icl_dsi.c | 2 +-
drivers/gpu/drm/i915/display/intel_dp.c | 18 ++++++++----------
drivers/gpu/drm/i915/display/intel_hdmi.c | 12 +++++++-----
drivers/gpu/drm/i915/display/intel_lvds.c | 7 ++-----
drivers/gpu/drm/i915/display/intel_panel.c | 18 ++++++++++++------
drivers/gpu/drm/i915/display/intel_panel.h | 4 ++--
drivers/gpu/drm/i915/display/vlv_dsi.c | 6 ++----
7 files changed, 34 insertions(+), 33 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
index 627cbd880224..d252f68e5d09 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -1272,7 +1272,7 @@ static int gen11_dsi_compute_config(struct intel_encoder *encoder,
pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
intel_fixed_panel_mode(fixed_mode, adjusted_mode);
- intel_pch_panel_fitting(pipe_config, conn_state->scaling_mode);
+ intel_pch_panel_fitting(pipe_config, conn_state);
adjusted_mode->flags = 0;
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index f6ef3c25c0ed..c8af11f03b55 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -2114,9 +2114,10 @@ intel_dp_compute_link_config(struct intel_encoder *encoder,
static int
intel_dp_ycbcr420_config(struct intel_dp *intel_dp,
- struct drm_connector *connector,
- struct intel_crtc_state *crtc_state)
+ struct intel_crtc_state *crtc_state,
+ const struct drm_connector_state *conn_state)
{
+ struct drm_connector *connector = conn_state->connector;
const struct drm_display_info *info = &connector->display_info;
const struct drm_display_mode *adjusted_mode =
&crtc_state->base.adjusted_mode;
@@ -2128,7 +2129,7 @@ intel_dp_ycbcr420_config(struct intel_dp *intel_dp,
crtc_state->output_format = INTEL_OUTPUT_FORMAT_YCBCR420;
- intel_pch_panel_fitting(crtc_state, DRM_MODE_SCALE_FULLSCREEN);
+ intel_pch_panel_fitting(crtc_state, conn_state);
return 0;
}
@@ -2166,7 +2167,6 @@ intel_dp_compute_config(struct intel_encoder *encoder,
struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
struct intel_lspcon *lspcon = enc_to_intel_lspcon(&encoder->base);
enum port port = encoder->port;
- struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc);
struct intel_connector *intel_connector = intel_dp->attached_connector;
struct intel_digital_connector_state *intel_conn_state =
to_intel_digital_connector_state(conn_state);
@@ -2181,8 +2181,8 @@ intel_dp_compute_config(struct intel_encoder *encoder,
if (lspcon->active)
lspcon_ycbcr420_config(&intel_connector->base, pipe_config);
else
- ret = intel_dp_ycbcr420_config(intel_dp, &intel_connector->base,
- pipe_config);
+ ret = intel_dp_ycbcr420_config(intel_dp, pipe_config,
+ conn_state);
if (ret)
return ret;
@@ -2199,11 +2199,9 @@ intel_dp_compute_config(struct intel_encoder *encoder,
adjusted_mode);
if (HAS_GMCH(dev_priv))
- intel_gmch_panel_fitting(pipe_config,
- conn_state->scaling_mode);
+ intel_gmch_panel_fitting(pipe_config, conn_state);
else
- intel_pch_panel_fitting(pipe_config,
- conn_state->scaling_mode);
+ intel_pch_panel_fitting(pipe_config, conn_state);
}
if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c
index c749b04ba477..1fa4f073b274 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
@@ -2264,17 +2264,19 @@ static bool hdmi_deep_color_possible(const struct intel_crtc_state *crtc_state,
}
static bool
-intel_hdmi_ycbcr420_config(struct drm_connector *connector,
- struct intel_crtc_state *config)
+intel_hdmi_ycbcr420_config(struct intel_crtc_state *crtc_state,
+ const struct drm_connector_state *conn_state)
{
+ struct drm_connector *connector = conn_state->connector;
+
if (!connector->ycbcr_420_allowed) {
DRM_ERROR("Platform doesn't support YCBCR420 output\n");
return false;
}
- config->output_format = INTEL_OUTPUT_FORMAT_YCBCR420;
+ crtc_state->output_format = INTEL_OUTPUT_FORMAT_YCBCR420;
- intel_pch_panel_fitting(config, DRM_MODE_SCALE_FULLSCREEN);
+ intel_pch_panel_fitting(crtc_state, conn_state);
return true;
}
@@ -2387,7 +2389,7 @@ int intel_hdmi_compute_config(struct intel_encoder *encoder,
pipe_config->pixel_multiplier = 2;
if (drm_mode_is_420_only(&connector->display_info, adjusted_mode)) {
- if (!intel_hdmi_ycbcr420_config(connector, pipe_config)) {
+ if (!intel_hdmi_ycbcr420_config(pipe_config, conn_state)) {
DRM_ERROR("Can't support YCBCR420 output\n");
return -EINVAL;
}
diff --git a/drivers/gpu/drm/i915/display/intel_lvds.c b/drivers/gpu/drm/i915/display/intel_lvds.c
index e983035aca63..adc959f8f95a 100644
--- a/drivers/gpu/drm/i915/display/intel_lvds.c
+++ b/drivers/gpu/drm/i915/display/intel_lvds.c
@@ -430,12 +430,9 @@ static int intel_lvds_compute_config(struct intel_encoder *intel_encoder,
if (HAS_PCH_SPLIT(dev_priv)) {
pipe_config->has_pch_encoder = true;
- intel_pch_panel_fitting(pipe_config,
- conn_state->scaling_mode);
+ intel_pch_panel_fitting(pipe_config, conn_state);
} else {
- intel_gmch_panel_fitting(pipe_config,
- conn_state->scaling_mode);
-
+ intel_gmch_panel_fitting(pipe_config, conn_state);
}
/*
diff --git a/drivers/gpu/drm/i915/display/intel_panel.c b/drivers/gpu/drm/i915/display/intel_panel.c
index 6f4270ecdebd..1a0b69ec1778 100644
--- a/drivers/gpu/drm/i915/display/intel_panel.c
+++ b/drivers/gpu/drm/i915/display/intel_panel.c
@@ -175,10 +175,11 @@ intel_panel_vbt_fixed_mode(struct intel_connector *connector)
/* adjusted_mode has been preset to be the panel's fixed mode */
void
intel_pch_panel_fitting(struct intel_crtc_state *crtc_state,
- int fitting_mode)
+ const struct drm_connector_state *conn_state)
{
const struct drm_display_mode *adjusted_mode =
&crtc_state->base.adjusted_mode;
+ int scaling_mode = conn_state->scaling_mode;
int x, y, width, height;
/* Native modes don't need fitting */
@@ -187,7 +188,7 @@ intel_pch_panel_fitting(struct intel_crtc_state *crtc_state,
crtc_state->output_format != INTEL_OUTPUT_FORMAT_YCBCR420)
return;
- switch (fitting_mode) {
+ switch (scaling_mode) {
case DRM_MODE_SCALE_CENTER:
width = crtc_state->pipe_src_w;
height = crtc_state->pipe_src_h;
@@ -224,6 +225,10 @@ intel_pch_panel_fitting(struct intel_crtc_state *crtc_state,
}
break;
+ case DRM_MODE_SCALE_NONE:
+ WARN_ON(adjusted_mode->crtc_hdisplay != crtc_state->pipe_src_w);
+ WARN_ON(adjusted_mode->crtc_vdisplay != crtc_state->pipe_src_h);
+ /* fall through */
case DRM_MODE_SCALE_FULLSCREEN:
x = y = 0;
width = adjusted_mode->crtc_hdisplay;
@@ -231,7 +236,7 @@ intel_pch_panel_fitting(struct intel_crtc_state *crtc_state,
break;
default:
- MISSING_CASE(fitting_mode);
+ MISSING_CASE(scaling_mode);
return;
}
@@ -376,19 +381,20 @@ static void i9xx_scale_aspect(struct intel_crtc_state *crtc_state,
}
void intel_gmch_panel_fitting(struct intel_crtc_state *crtc_state,
- int fitting_mode)
+ const struct drm_connector_state *conn_state)
{
struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
u32 pfit_control = 0, pfit_pgm_ratios = 0, border = 0;
struct drm_display_mode *adjusted_mode = &crtc_state->base.adjusted_mode;
+ int scaling_mode = conn_state->scaling_mode;
/* Native modes don't need fitting */
if (adjusted_mode->crtc_hdisplay == crtc_state->pipe_src_w &&
adjusted_mode->crtc_vdisplay == crtc_state->pipe_src_h)
goto out;
- switch (fitting_mode) {
+ switch (scaling_mode) {
case DRM_MODE_SCALE_CENTER:
/*
* For centered modes, we have to calculate border widths &
@@ -424,7 +430,7 @@ void intel_gmch_panel_fitting(struct intel_crtc_state *crtc_state,
}
break;
default:
- WARN(1, "bad panel fit mode: %d\n", fitting_mode);
+ MISSING_CASE(scaling_mode);
return;
}
diff --git a/drivers/gpu/drm/i915/display/intel_panel.h b/drivers/gpu/drm/i915/display/intel_panel.h
index e1804e6e8325..e2fa1543a61f 100644
--- a/drivers/gpu/drm/i915/display/intel_panel.h
+++ b/drivers/gpu/drm/i915/display/intel_panel.h
@@ -26,9 +26,9 @@ void intel_panel_fini(struct intel_panel *panel);
void intel_fixed_panel_mode(const struct drm_display_mode *fixed_mode,
struct drm_display_mode *adjusted_mode);
void intel_pch_panel_fitting(struct intel_crtc_state *crtc_state,
- int fitting_mode);
+ const struct drm_connector_state *conn_state);
void intel_gmch_panel_fitting(struct intel_crtc_state *crtc_state,
- int fitting_mode);
+ const struct drm_connector_state *conn_state);
void intel_panel_set_backlight_acpi(const struct drm_connector_state *conn_state,
u32 level, u32 max);
int intel_panel_setup_backlight(struct drm_connector *connector,
diff --git a/drivers/gpu/drm/i915/display/vlv_dsi.c b/drivers/gpu/drm/i915/display/vlv_dsi.c
index 6a20c4169a53..9f4f7c670cc8 100644
--- a/drivers/gpu/drm/i915/display/vlv_dsi.c
+++ b/drivers/gpu/drm/i915/display/vlv_dsi.c
@@ -272,11 +272,9 @@ static int intel_dsi_compute_config(struct intel_encoder *encoder,
intel_fixed_panel_mode(fixed_mode, adjusted_mode);
if (HAS_GMCH(dev_priv))
- intel_gmch_panel_fitting(pipe_config,
- conn_state->scaling_mode);
+ intel_gmch_panel_fitting(pipe_config, conn_state);
else
- intel_pch_panel_fitting(pipe_config,
- conn_state->scaling_mode);
+ intel_pch_panel_fitting(pipe_config, conn_state);
}
if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
--
2.21.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 27+ messages in thread* [PATCH 12/15] drm/i915: Have pfit calculations return an error code
2019-09-04 16:26 [PATCH 00/15] drm/i915: Expose margin connector properties for underscan Ville Syrjala
` (11 preceding siblings ...)
2019-09-04 16:26 ` [PATCH 11/15] drm/i915: Pass connector state to pfit calculations Ville Syrjala
@ 2019-09-04 16:26 ` Ville Syrjala
2019-09-04 16:26 ` [PATCH 13/15] drm/i915: Expose margin properties on ilk+ HDMI Ville Syrjala
` (8 subsequent siblings)
21 siblings, 0 replies; 27+ messages in thread
From: Ville Syrjala @ 2019-09-04 16:26 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Change intel_{gmch,pch}_panel_fitting() to return a normal
error vs. success int. We'll need this later to validate that
the margin properties aren't misconfigured.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/icl_dsi.c | 10 +++++++---
drivers/gpu/drm/i915/display/intel_dp.c | 10 +++++-----
drivers/gpu/drm/i915/display/intel_hdmi.c | 22 +++++++++++-----------
drivers/gpu/drm/i915/display/intel_lvds.c | 13 ++++++++-----
drivers/gpu/drm/i915/display/intel_panel.c | 19 +++++++++++--------
drivers/gpu/drm/i915/display/intel_panel.h | 6 +++---
drivers/gpu/drm/i915/display/vlv_dsi.c | 6 ++++--
7 files changed, 49 insertions(+), 37 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
index d252f68e5d09..2010ad991876 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -1266,13 +1266,17 @@ static int gen11_dsi_compute_config(struct intel_encoder *encoder,
base);
struct intel_connector *intel_connector = intel_dsi->attached_connector;
const struct drm_display_mode *fixed_mode =
- intel_connector->panel.fixed_mode;
+ intel_connector->panel.fixed_mode;
struct drm_display_mode *adjusted_mode =
- &pipe_config->base.adjusted_mode;
+ &pipe_config->base.adjusted_mode;
+ int ret;
pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
intel_fixed_panel_mode(fixed_mode, adjusted_mode);
- intel_pch_panel_fitting(pipe_config, conn_state);
+
+ ret = intel_pch_panel_fitting(pipe_config, conn_state);
+ if (ret)
+ return ret;
adjusted_mode->flags = 0;
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index c8af11f03b55..058c34013f58 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -2129,9 +2129,7 @@ intel_dp_ycbcr420_config(struct intel_dp *intel_dp,
crtc_state->output_format = INTEL_OUTPUT_FORMAT_YCBCR420;
- intel_pch_panel_fitting(crtc_state, conn_state);
-
- return 0;
+ return intel_pch_panel_fitting(crtc_state, conn_state);
}
bool intel_dp_limited_color_range(const struct intel_crtc_state *crtc_state,
@@ -2199,9 +2197,11 @@ intel_dp_compute_config(struct intel_encoder *encoder,
adjusted_mode);
if (HAS_GMCH(dev_priv))
- intel_gmch_panel_fitting(pipe_config, conn_state);
+ ret = intel_gmch_panel_fitting(pipe_config, conn_state);
else
- intel_pch_panel_fitting(pipe_config, conn_state);
+ ret = intel_pch_panel_fitting(pipe_config, conn_state);
+ if (ret)
+ return ret;
}
if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c
index 1fa4f073b274..7bacd9b135eb 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
@@ -2263,22 +2263,25 @@ static bool hdmi_deep_color_possible(const struct intel_crtc_state *crtc_state,
return true;
}
-static bool
+static int
intel_hdmi_ycbcr420_config(struct intel_crtc_state *crtc_state,
const struct drm_connector_state *conn_state)
{
struct drm_connector *connector = conn_state->connector;
+ const struct drm_display_mode *adjusted_mode =
+ &crtc_state->base.adjusted_mode;
+
+ if (!drm_mode_is_420_only(&connector->display_info, adjusted_mode))
+ return 0;
if (!connector->ycbcr_420_allowed) {
DRM_ERROR("Platform doesn't support YCBCR420 output\n");
- return false;
+ return -EINVAL;
}
crtc_state->output_format = INTEL_OUTPUT_FORMAT_YCBCR420;
- intel_pch_panel_fitting(crtc_state, conn_state);
-
- return true;
+ return intel_pch_panel_fitting(crtc_state, conn_state);
}
static int intel_hdmi_port_clock(int clock, int bpc)
@@ -2388,12 +2391,9 @@ int intel_hdmi_compute_config(struct intel_encoder *encoder,
if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
pipe_config->pixel_multiplier = 2;
- if (drm_mode_is_420_only(&connector->display_info, adjusted_mode)) {
- if (!intel_hdmi_ycbcr420_config(pipe_config, conn_state)) {
- DRM_ERROR("Can't support YCBCR420 output\n");
- return -EINVAL;
- }
- }
+ ret = intel_hdmi_ycbcr420_config(pipe_config, conn_state);
+ if (ret)
+ return ret;
if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv))
pipe_config->has_pch_encoder = true;
diff --git a/drivers/gpu/drm/i915/display/intel_lvds.c b/drivers/gpu/drm/i915/display/intel_lvds.c
index adc959f8f95a..5e77d98d20f7 100644
--- a/drivers/gpu/drm/i915/display/intel_lvds.c
+++ b/drivers/gpu/drm/i915/display/intel_lvds.c
@@ -395,6 +395,7 @@ static int intel_lvds_compute_config(struct intel_encoder *intel_encoder,
struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc);
unsigned int lvds_bpp;
+ int ret;
/* Should never happen!! */
if (INTEL_GEN(dev_priv) < 4 && intel_crtc->pipe == 0) {
@@ -427,13 +428,15 @@ static int intel_lvds_compute_config(struct intel_encoder *intel_encoder,
if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
return -EINVAL;
- if (HAS_PCH_SPLIT(dev_priv)) {
+ if (HAS_PCH_SPLIT(dev_priv))
pipe_config->has_pch_encoder = true;
- intel_pch_panel_fitting(pipe_config, conn_state);
- } else {
- intel_gmch_panel_fitting(pipe_config, conn_state);
- }
+ if (HAS_GMCH(dev_priv))
+ ret = intel_gmch_panel_fitting(pipe_config, conn_state);
+ else
+ ret = intel_pch_panel_fitting(pipe_config, conn_state);
+ if (ret)
+ return ret;
/*
* XXX: It would be nice to support lower refresh rates on the
diff --git a/drivers/gpu/drm/i915/display/intel_panel.c b/drivers/gpu/drm/i915/display/intel_panel.c
index 1a0b69ec1778..f64fa73587ef 100644
--- a/drivers/gpu/drm/i915/display/intel_panel.c
+++ b/drivers/gpu/drm/i915/display/intel_panel.c
@@ -173,9 +173,8 @@ intel_panel_vbt_fixed_mode(struct intel_connector *connector)
}
/* adjusted_mode has been preset to be the panel's fixed mode */
-void
-intel_pch_panel_fitting(struct intel_crtc_state *crtc_state,
- const struct drm_connector_state *conn_state)
+int intel_pch_panel_fitting(struct intel_crtc_state *crtc_state,
+ const struct drm_connector_state *conn_state)
{
const struct drm_display_mode *adjusted_mode =
&crtc_state->base.adjusted_mode;
@@ -186,7 +185,7 @@ intel_pch_panel_fitting(struct intel_crtc_state *crtc_state,
if (adjusted_mode->crtc_hdisplay == crtc_state->pipe_src_w &&
adjusted_mode->crtc_vdisplay == crtc_state->pipe_src_h &&
crtc_state->output_format != INTEL_OUTPUT_FORMAT_YCBCR420)
- return;
+ return 0;
switch (scaling_mode) {
case DRM_MODE_SCALE_CENTER:
@@ -237,7 +236,7 @@ intel_pch_panel_fitting(struct intel_crtc_state *crtc_state,
default:
MISSING_CASE(scaling_mode);
- return;
+ return -EINVAL;
}
crtc_state->pch_pfit.dst.x1 = x;
@@ -245,6 +244,8 @@ intel_pch_panel_fitting(struct intel_crtc_state *crtc_state,
crtc_state->pch_pfit.dst.x2 = x + width;
crtc_state->pch_pfit.dst.y2 = y + height;
crtc_state->pch_pfit.enabled = true;
+
+ return 0;
}
static void
@@ -380,8 +381,8 @@ static void i9xx_scale_aspect(struct intel_crtc_state *crtc_state,
}
}
-void intel_gmch_panel_fitting(struct intel_crtc_state *crtc_state,
- const struct drm_connector_state *conn_state)
+int intel_gmch_panel_fitting(struct intel_crtc_state *crtc_state,
+ const struct drm_connector_state *conn_state)
{
struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
@@ -431,7 +432,7 @@ void intel_gmch_panel_fitting(struct intel_crtc_state *crtc_state,
break;
default:
MISSING_CASE(scaling_mode);
- return;
+ return -EINVAL;
}
/* 965+ wants fuzzy fitting */
@@ -452,6 +453,8 @@ void intel_gmch_panel_fitting(struct intel_crtc_state *crtc_state,
crtc_state->gmch_pfit.control = pfit_control;
crtc_state->gmch_pfit.pgm_ratios = pfit_pgm_ratios;
crtc_state->gmch_pfit.lvds_border_bits = border;
+
+ return 0;
}
/**
diff --git a/drivers/gpu/drm/i915/display/intel_panel.h b/drivers/gpu/drm/i915/display/intel_panel.h
index e2fa1543a61f..a5c93232eb6f 100644
--- a/drivers/gpu/drm/i915/display/intel_panel.h
+++ b/drivers/gpu/drm/i915/display/intel_panel.h
@@ -25,10 +25,10 @@ int intel_panel_init(struct intel_panel *panel,
void intel_panel_fini(struct intel_panel *panel);
void intel_fixed_panel_mode(const struct drm_display_mode *fixed_mode,
struct drm_display_mode *adjusted_mode);
-void intel_pch_panel_fitting(struct intel_crtc_state *crtc_state,
+int intel_pch_panel_fitting(struct intel_crtc_state *crtc_state,
+ const struct drm_connector_state *conn_state);
+int intel_gmch_panel_fitting(struct intel_crtc_state *crtc_state,
const struct drm_connector_state *conn_state);
-void intel_gmch_panel_fitting(struct intel_crtc_state *crtc_state,
- const struct drm_connector_state *conn_state);
void intel_panel_set_backlight_acpi(const struct drm_connector_state *conn_state,
u32 level, u32 max);
int intel_panel_setup_backlight(struct drm_connector *connector,
diff --git a/drivers/gpu/drm/i915/display/vlv_dsi.c b/drivers/gpu/drm/i915/display/vlv_dsi.c
index 9f4f7c670cc8..7b0007faa579 100644
--- a/drivers/gpu/drm/i915/display/vlv_dsi.c
+++ b/drivers/gpu/drm/i915/display/vlv_dsi.c
@@ -272,9 +272,11 @@ static int intel_dsi_compute_config(struct intel_encoder *encoder,
intel_fixed_panel_mode(fixed_mode, adjusted_mode);
if (HAS_GMCH(dev_priv))
- intel_gmch_panel_fitting(pipe_config, conn_state);
+ ret = intel_gmch_panel_fitting(pipe_config, conn_state);
else
- intel_pch_panel_fitting(pipe_config, conn_state);
+ ret = intel_pch_panel_fitting(pipe_config, conn_state);
+ if (ret)
+ return ret;
}
if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
--
2.21.0
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^ permalink raw reply related [flat|nested] 27+ messages in thread* [PATCH 13/15] drm/i915: Expose margin properties on ilk+ HDMI
2019-09-04 16:26 [PATCH 00/15] drm/i915: Expose margin connector properties for underscan Ville Syrjala
` (12 preceding siblings ...)
2019-09-04 16:26 ` [PATCH 12/15] drm/i915: Have pfit calculations return an error code Ville Syrjala
@ 2019-09-04 16:26 ` Ville Syrjala
2019-09-04 16:26 ` [PATCH 14/15] drm/i915: Expose margin properties on ilk+ DP SST Ville Syrjala
` (7 subsequent siblings)
21 siblings, 0 replies; 27+ messages in thread
From: Ville Syrjala @ 2019-09-04 16:26 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Add support for underscan by exposing the margin properties on
ilk+ HDMI ports. This can be useful with silly TVs that won't
let you disable overscanning.
We limit this to ilk+ only because the gmch style panel fitter
doesn't really have the flexibility we need.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=29723
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_atomic.c | 4 +++
drivers/gpu/drm/i915/display/intel_hdmi.c | 17 +++++++++---
drivers/gpu/drm/i915/display/intel_panel.c | 29 ++++++++++++++++-----
3 files changed, 41 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_atomic.c b/drivers/gpu/drm/i915/display/intel_atomic.c
index d3fb75bb9eb1..6764e32a4b53 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic.c
@@ -145,6 +145,10 @@ int intel_digital_connector_atomic_check(struct drm_connector *conn,
new_conn_state->base.picture_aspect_ratio != old_conn_state->base.picture_aspect_ratio ||
new_conn_state->base.content_type != old_conn_state->base.content_type ||
new_conn_state->base.scaling_mode != old_conn_state->base.scaling_mode ||
+ new_conn_state->base.tv.margins.left != old_conn_state->base.tv.margins.left ||
+ new_conn_state->base.tv.margins.right != old_conn_state->base.tv.margins.right ||
+ new_conn_state->base.tv.margins.top != old_conn_state->base.tv.margins.top ||
+ new_conn_state->base.tv.margins.bottom != old_conn_state->base.tv.margins.bottom ||
!blob_equal(new_conn_state->base.hdr_output_metadata,
old_conn_state->base.hdr_output_metadata))
crtc_state->mode_changed = true;
diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c
index 7bacd9b135eb..287d370f8111 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
@@ -732,6 +732,8 @@ intel_hdmi_compute_avi_infoframe(struct intel_encoder *encoder,
drm_hdmi_avi_infoframe_content_type(frame, conn_state);
+ drm_hdmi_avi_infoframe_bars(frame, conn_state);
+
/* TODO: handle pixel repetition for YCBCR420 outputs */
ret = hdmi_avi_infoframe_check(frame);
@@ -2275,13 +2277,13 @@ intel_hdmi_ycbcr420_config(struct intel_crtc_state *crtc_state,
return 0;
if (!connector->ycbcr_420_allowed) {
- DRM_ERROR("Platform doesn't support YCBCR420 output\n");
+ DRM_DEBUG_KMS("Platform doesn't support YCBCR420 output\n");
return -EINVAL;
}
crtc_state->output_format = INTEL_OUTPUT_FORMAT_YCBCR420;
- return intel_pch_panel_fitting(crtc_state, conn_state);
+ return 0;
}
static int intel_hdmi_port_clock(int clock, int bpc)
@@ -2395,6 +2397,12 @@ int intel_hdmi_compute_config(struct intel_encoder *encoder,
if (ret)
return ret;
+ if (!HAS_GMCH(dev_priv)) {
+ ret = intel_pch_panel_fitting(pipe_config, conn_state);
+ if (ret)
+ return ret;
+ }
+
if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv))
pipe_config->has_pch_encoder = true;
@@ -2834,8 +2842,11 @@ intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *c
drm_object_attach_property(&connector->base,
connector->dev->mode_config.hdr_output_metadata_property, 0);
- if (!HAS_GMCH(dev_priv))
+ if (!HAS_GMCH(dev_priv)) {
drm_connector_attach_max_bpc_property(connector, 8, 12);
+ drm_mode_create_tv_margin_properties(&dev_priv->drm);
+ drm_connector_attach_tv_margin_properties(connector);
+ }
}
/*
diff --git a/drivers/gpu/drm/i915/display/intel_panel.c b/drivers/gpu/drm/i915/display/intel_panel.c
index f64fa73587ef..57f9bc808f93 100644
--- a/drivers/gpu/drm/i915/display/intel_panel.c
+++ b/drivers/gpu/drm/i915/display/intel_panel.c
@@ -181,12 +181,30 @@ int intel_pch_panel_fitting(struct intel_crtc_state *crtc_state,
int scaling_mode = conn_state->scaling_mode;
int x, y, width, height;
+ x = conn_state->tv.margins.left;
+ y = conn_state->tv.margins.top;
+
+ width = adjusted_mode->crtc_hdisplay -
+ conn_state->tv.margins.left -
+ conn_state->tv.margins.right;
+ height = adjusted_mode->crtc_vdisplay -
+ conn_state->tv.margins.top -
+ conn_state->tv.margins.bottom;
+
+ if (width <= 0 || height <= 0)
+ return -EINVAL;
+
/* Native modes don't need fitting */
- if (adjusted_mode->crtc_hdisplay == crtc_state->pipe_src_w &&
- adjusted_mode->crtc_vdisplay == crtc_state->pipe_src_h &&
+ if (x == 0 && y == 0 &&
+ width == crtc_state->pipe_src_w &&
+ height == crtc_state->pipe_src_h &&
crtc_state->output_format != INTEL_OUTPUT_FORMAT_YCBCR420)
return 0;
+ /*
+ * FIXME: margins and scaling_mode are implemented
+ * in a mutually exclusive way for the time being.
+ */
switch (scaling_mode) {
case DRM_MODE_SCALE_CENTER:
width = crtc_state->pipe_src_w;
@@ -224,16 +242,15 @@ int intel_pch_panel_fitting(struct intel_crtc_state *crtc_state,
}
break;
- case DRM_MODE_SCALE_NONE:
- WARN_ON(adjusted_mode->crtc_hdisplay != crtc_state->pipe_src_w);
- WARN_ON(adjusted_mode->crtc_vdisplay != crtc_state->pipe_src_h);
- /* fall through */
case DRM_MODE_SCALE_FULLSCREEN:
x = y = 0;
width = adjusted_mode->crtc_hdisplay;
height = adjusted_mode->crtc_vdisplay;
break;
+ case DRM_MODE_SCALE_NONE:
+ break;
+
default:
MISSING_CASE(scaling_mode);
return -EINVAL;
--
2.21.0
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 27+ messages in thread* [PATCH 14/15] drm/i915: Expose margin properties on ilk+ DP SST
2019-09-04 16:26 [PATCH 00/15] drm/i915: Expose margin connector properties for underscan Ville Syrjala
` (13 preceding siblings ...)
2019-09-04 16:26 ` [PATCH 13/15] drm/i915: Expose margin properties on ilk+ HDMI Ville Syrjala
@ 2019-09-04 16:26 ` Ville Syrjala
2019-09-04 16:26 ` [PATCH 15/15] drm/i915: Expose margin properties on DP MST Ville Syrjala
` (6 subsequent siblings)
21 siblings, 0 replies; 27+ messages in thread
From: Ville Syrjala @ 2019-09-04 16:26 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
As with HDMI let's can expose the margin properties for DP/LSPCON
on ilk+. I don't think DP has anything resembling the AVI infoframe
bar information so we don't have to worry about that part except
with LSPCON.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=29723
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_dp.c | 27 ++++++++++++---------
drivers/gpu/drm/i915/display/intel_lspcon.c | 2 ++
2 files changed, 18 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 058c34013f58..a00b10f070e0 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -2129,7 +2129,7 @@ intel_dp_ycbcr420_config(struct intel_dp *intel_dp,
crtc_state->output_format = INTEL_OUTPUT_FORMAT_YCBCR420;
- return intel_pch_panel_fitting(crtc_state, conn_state);
+ return 0;
}
bool intel_dp_limited_color_range(const struct intel_crtc_state *crtc_state,
@@ -2192,18 +2192,10 @@ intel_dp_compute_config(struct intel_encoder *encoder,
else
pipe_config->has_audio = intel_conn_state->force_audio == HDMI_AUDIO_ON;
- if (intel_dp_is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
+ if (intel_dp_is_edp(intel_dp) && intel_connector->panel.fixed_mode)
intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
adjusted_mode);
- if (HAS_GMCH(dev_priv))
- ret = intel_gmch_panel_fitting(pipe_config, conn_state);
- else
- ret = intel_pch_panel_fitting(pipe_config, conn_state);
- if (ret)
- return ret;
- }
-
if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
return -EINVAL;
@@ -2214,6 +2206,13 @@ intel_dp_compute_config(struct intel_encoder *encoder,
if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
return -EINVAL;
+ if (HAS_GMCH(dev_priv) && intel_dp_is_edp(intel_dp))
+ ret = intel_gmch_panel_fitting(pipe_config, conn_state);
+ else if (!HAS_GMCH(dev_priv))
+ ret = intel_pch_panel_fitting(pipe_config, conn_state);
+ if (ret)
+ return ret;
+
ret = intel_dp_compute_link_config(encoder, pipe_config, conn_state);
if (ret < 0)
return ret;
@@ -6356,6 +6355,10 @@ intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connect
else if (INTEL_GEN(dev_priv) >= 5)
drm_connector_attach_max_bpc_property(connector, 6, 12);
+ /*
+ * FIXME: margins and scaling_mode are implemented
+ * in a mutually exclusive way for the time being.
+ */
if (intel_dp_is_edp(intel_dp)) {
u32 allowed_scalers;
@@ -6366,7 +6369,9 @@ intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connect
drm_connector_attach_scaling_mode_property(connector, allowed_scalers);
connector->state->scaling_mode = DRM_MODE_SCALE_ASPECT;
-
+ } else if (!HAS_GMCH(dev_priv)) {
+ drm_mode_create_tv_margin_properties(&dev_priv->drm);
+ drm_connector_attach_tv_margin_properties(connector);
}
}
diff --git a/drivers/gpu/drm/i915/display/intel_lspcon.c b/drivers/gpu/drm/i915/display/intel_lspcon.c
index f8f1308643a9..664977157081 100644
--- a/drivers/gpu/drm/i915/display/intel_lspcon.c
+++ b/drivers/gpu/drm/i915/display/intel_lspcon.c
@@ -508,6 +508,8 @@ void lspcon_set_infoframes(struct intel_encoder *encoder,
HDMI_QUANTIZATION_RANGE_LIMITED :
HDMI_QUANTIZATION_RANGE_FULL);
+ drm_hdmi_avi_infoframe_bars(&frame.avi, conn_state);
+
ret = hdmi_infoframe_pack(&frame, buf, sizeof(buf));
if (ret < 0) {
DRM_ERROR("Failed to pack AVI IF\n");
--
2.21.0
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 27+ messages in thread* [PATCH 15/15] drm/i915: Expose margin properties on DP MST
2019-09-04 16:26 [PATCH 00/15] drm/i915: Expose margin connector properties for underscan Ville Syrjala
` (14 preceding siblings ...)
2019-09-04 16:26 ` [PATCH 14/15] drm/i915: Expose margin properties on ilk+ DP SST Ville Syrjala
@ 2019-09-04 16:26 ` Ville Syrjala
2019-09-04 16:47 ` ✗ Fi.CI.SPARSE: warning for drm/i915: Expose margin connector properties for underscan Patchwork
` (5 subsequent siblings)
21 siblings, 0 replies; 27+ messages in thread
From: Ville Syrjala @ 2019-09-04 16:26 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Expose the margin properties for DP MST as well. Only HSW+ to
worry about here, so nothing really to do but set up the
pfit appropriately.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=29723
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_dp_mst.c | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index 37366f81255b..76719a822ea5 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -36,6 +36,7 @@
#include "intel_dp.h"
#include "intel_dp_mst.h"
#include "intel_dpio_phy.h"
+#include "intel_panel.h"
static int intel_dp_mst_compute_link_config(struct intel_encoder *encoder,
struct intel_crtc_state *crtc_state,
@@ -117,6 +118,10 @@ static int intel_dp_mst_compute_config(struct intel_encoder *encoder,
pipe_config->has_audio =
intel_conn_state->force_audio == HDMI_AUDIO_ON;
+ ret = intel_pch_panel_fitting(pipe_config, conn_state);
+ if (ret)
+ return ret;
+
/*
* for MST we always configure max link bw - the spec doesn't
* seem to suggest we should do otherwise.
@@ -554,6 +559,8 @@ static struct drm_connector *intel_dp_add_mst_connector(struct drm_dp_mst_topolo
if (connector->max_bpc_property)
drm_connector_attach_max_bpc_property(connector, 6, 12);
+ drm_connector_attach_tv_margin_properties(connector);
+
return connector;
err:
--
2.21.0
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^ permalink raw reply related [flat|nested] 27+ messages in thread* ✗ Fi.CI.SPARSE: warning for drm/i915: Expose margin connector properties for underscan
2019-09-04 16:26 [PATCH 00/15] drm/i915: Expose margin connector properties for underscan Ville Syrjala
` (15 preceding siblings ...)
2019-09-04 16:26 ` [PATCH 15/15] drm/i915: Expose margin properties on DP MST Ville Syrjala
@ 2019-09-04 16:47 ` Patchwork
2019-09-04 17:18 ` ✓ Fi.CI.BAT: success " Patchwork
` (4 subsequent siblings)
21 siblings, 0 replies; 27+ messages in thread
From: Patchwork @ 2019-09-04 16:47 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Expose margin connector properties for underscan
URL : https://patchwork.freedesktop.org/series/66225/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.6.0
Commit: drm/edid: Add drm_hdmi_avi_infoframe_bars()
Okay!
Commit: drm/i915: Parametrize PFIT_PIPE
Okay!
Commit: drm/i915: Replace some accidental I915_READ_FW()s with the normal version
Okay!
Commit: drm/i915: Fix skl+ non-scaled pfit modes
Okay!
Commit: drm/i915: Flatten a bunch of the pfit functions
Okay!
Commit: drm/i915: Use drm_rect to store the pfit window pos/size
Okay!
Commit: drm/i915: Check pipe source size against pfit limits
Okay!
Commit: drm/i915: Check pfit scaling factors
Okay!
Commit: drm/i915: Check pfit minimum timings
Okay!
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^ permalink raw reply [flat|nested] 27+ messages in thread* ✓ Fi.CI.BAT: success for drm/i915: Expose margin connector properties for underscan
2019-09-04 16:26 [PATCH 00/15] drm/i915: Expose margin connector properties for underscan Ville Syrjala
` (16 preceding siblings ...)
2019-09-04 16:47 ` ✗ Fi.CI.SPARSE: warning for drm/i915: Expose margin connector properties for underscan Patchwork
@ 2019-09-04 17:18 ` Patchwork
2019-09-04 20:08 ` ✗ Fi.CI.IGT: failure " Patchwork
` (3 subsequent siblings)
21 siblings, 0 replies; 27+ messages in thread
From: Patchwork @ 2019-09-04 17:18 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Expose margin connector properties for underscan
URL : https://patchwork.freedesktop.org/series/66225/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6835 -> Patchwork_14276
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14276/
Known issues
------------
Here are the changes found in Patchwork_14276 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_exec_basic@basic-all:
- fi-icl-u3: [PASS][1] -> [DMESG-WARN][2] ([fdo#107724])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6835/fi-icl-u3/igt@gem_exec_basic@basic-all.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14276/fi-icl-u3/igt@gem_exec_basic@basic-all.html
* igt@i915_module_load@reload:
- fi-icl-u3: [PASS][3] -> [DMESG-WARN][4] ([fdo#107724] / [fdo#111214])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6835/fi-icl-u3/igt@i915_module_load@reload.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14276/fi-icl-u3/igt@i915_module_load@reload.html
* igt@kms_chamelium@hdmi-crc-fast:
- fi-kbl-7500u: [PASS][5] -> [FAIL][6] ([fdo#109635 ])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6835/fi-kbl-7500u/igt@kms_chamelium@hdmi-crc-fast.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14276/fi-kbl-7500u/igt@kms_chamelium@hdmi-crc-fast.html
* igt@kms_flip@basic-flip-vs-wf_vblank:
- fi-bsw-n3050: [PASS][7] -> [FAIL][8] ([fdo#100368])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6835/fi-bsw-n3050/igt@kms_flip@basic-flip-vs-wf_vblank.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14276/fi-bsw-n3050/igt@kms_flip@basic-flip-vs-wf_vblank.html
* igt@kms_frontbuffer_tracking@basic:
- fi-hsw-peppy: [PASS][9] -> [DMESG-WARN][10] ([fdo#102614])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6835/fi-hsw-peppy/igt@kms_frontbuffer_tracking@basic.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14276/fi-hsw-peppy/igt@kms_frontbuffer_tracking@basic.html
#### Possible fixes ####
* igt@gem_exec_suspend@basic-s3:
- fi-blb-e6850: [INCOMPLETE][11] ([fdo#107718]) -> [PASS][12]
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6835/fi-blb-e6850/igt@gem_exec_suspend@basic-s3.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14276/fi-blb-e6850/igt@gem_exec_suspend@basic-s3.html
* igt@prime_busy@basic-before-default:
- fi-icl-u3: [DMESG-WARN][13] ([fdo#107724]) -> [PASS][14] +1 similar issue
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6835/fi-icl-u3/igt@prime_busy@basic-before-default.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14276/fi-icl-u3/igt@prime_busy@basic-before-default.html
#### Warnings ####
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: [FAIL][15] ([fdo#111096]) -> [FAIL][16] ([fdo#111407])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6835/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14276/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#100368]: https://bugs.freedesktop.org/show_bug.cgi?id=100368
[fdo#102614]: https://bugs.freedesktop.org/show_bug.cgi?id=102614
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#109635 ]: https://bugs.freedesktop.org/show_bug.cgi?id=109635
[fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096
[fdo#111214]: https://bugs.freedesktop.org/show_bug.cgi?id=111214
[fdo#111407]: https://bugs.freedesktop.org/show_bug.cgi?id=111407
Participating hosts (52 -> 46)
------------------------------
Missing (6): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-icl-y fi-byt-clapper fi-bdw-samus
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_6835 -> Patchwork_14276
CI-20190529: 20190529
CI_DRM_6835: cde3db21383e3c077c278ba783e4ec8d006f2e32 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5171: 1911564805fe454919e8a5846534a0c1ef376a33 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_14276: 11794db5ae4124dff1f0fb0252e1b143edcbd48b @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
11794db5ae41 drm/i915: Expose margin properties on DP MST
69964922d0f3 drm/i915: Expose margin properties on ilk+ DP SST
0e237855dc45 drm/i915: Expose margin properties on ilk+ HDMI
016210607774 drm/i915: Have pfit calculations return an error code
4830953d95a8 drm/i915: Pass connector state to pfit calculations
38c82b8cca0d drm/i915: s/pipe_config/crtc_state/ in pfit functions
f220f020280b drm/i915: Check pfit minimum timings
c2855b2d9388 drm/i915: Check pfit scaling factors
012dfad5da53 drm/i915: Check pipe source size against pfit limits
831198682816 drm/i915: Use drm_rect to store the pfit window pos/size
392fdae7ab4b drm/i915: Flatten a bunch of the pfit functions
716bb8fedae2 drm/i915: Fix skl+ non-scaled pfit modes
026eea183816 drm/i915: Replace some accidental I915_READ_FW()s with the normal version
cf4fb8a63061 drm/i915: Parametrize PFIT_PIPE
e0ce54ecf10b drm/edid: Add drm_hdmi_avi_infoframe_bars()
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14276/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 27+ messages in thread* ✗ Fi.CI.IGT: failure for drm/i915: Expose margin connector properties for underscan
2019-09-04 16:26 [PATCH 00/15] drm/i915: Expose margin connector properties for underscan Ville Syrjala
` (17 preceding siblings ...)
2019-09-04 17:18 ` ✓ Fi.CI.BAT: success " Patchwork
@ 2019-09-04 20:08 ` Patchwork
2019-09-05 11:06 ` ✗ Fi.CI.SPARSE: warning for drm/i915: Expose margin connector properties for underscan (rev4) Patchwork
` (2 subsequent siblings)
21 siblings, 0 replies; 27+ messages in thread
From: Patchwork @ 2019-09-04 20:08 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Expose margin connector properties for underscan
URL : https://patchwork.freedesktop.org/series/66225/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_6835_full -> Patchwork_14276_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_14276_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_14276_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_14276_full:
### IGT changes ###
#### Possible regressions ####
* igt@kms_panel_fitting@legacy:
- shard-iclb: [PASS][1] -> [FAIL][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6835/shard-iclb1/igt@kms_panel_fitting@legacy.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14276/shard-iclb7/igt@kms_panel_fitting@legacy.html
Known issues
------------
Here are the changes found in Patchwork_14276_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_ctx_shared@exec-single-timeline-bsd:
- shard-iclb: [PASS][3] -> [SKIP][4] ([fdo#110841])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6835/shard-iclb7/igt@gem_ctx_shared@exec-single-timeline-bsd.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14276/shard-iclb1/igt@gem_ctx_shared@exec-single-timeline-bsd.html
* igt@gem_ctx_switch@legacy-render-heavy-queue:
- shard-glk: [PASS][5] -> [INCOMPLETE][6] ([fdo#103359] / [k.org#198133]) +1 similar issue
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6835/shard-glk5/igt@gem_ctx_switch@legacy-render-heavy-queue.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14276/shard-glk3/igt@gem_ctx_switch@legacy-render-heavy-queue.html
* igt@gem_exec_schedule@preemptive-hang-bsd:
- shard-iclb: [PASS][7] -> [SKIP][8] ([fdo#111325]) +3 similar issues
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6835/shard-iclb8/igt@gem_exec_schedule@preemptive-hang-bsd.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14276/shard-iclb2/igt@gem_exec_schedule@preemptive-hang-bsd.html
* igt@gem_pwrite@small-cpu-forwards:
- shard-kbl: [PASS][9] -> [INCOMPLETE][10] ([fdo#103665])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6835/shard-kbl6/igt@gem_pwrite@small-cpu-forwards.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14276/shard-kbl7/igt@gem_pwrite@small-cpu-forwards.html
* igt@i915_pm_rpm@fences:
- shard-iclb: [PASS][11] -> [INCOMPLETE][12] ([fdo#107713] / [fdo#108840])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6835/shard-iclb8/igt@i915_pm_rpm@fences.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14276/shard-iclb2/igt@i915_pm_rpm@fences.html
* igt@i915_pm_rpm@modeset-non-lpsp-stress:
- shard-hsw: [PASS][13] -> [FAIL][14] ([fdo#111548]) +4 similar issues
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6835/shard-hsw6/igt@i915_pm_rpm@modeset-non-lpsp-stress.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14276/shard-hsw8/igt@i915_pm_rpm@modeset-non-lpsp-stress.html
* igt@kms_cursor_crc@pipe-c-cursor-256x85-offscreen:
- shard-apl: [PASS][15] -> [INCOMPLETE][16] ([fdo#103927]) +3 similar issues
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6835/shard-apl8/igt@kms_cursor_crc@pipe-c-cursor-256x85-offscreen.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14276/shard-apl3/igt@kms_cursor_crc@pipe-c-cursor-256x85-offscreen.html
* igt@kms_flip@dpms-vs-vblank-race:
- shard-kbl: [PASS][17] -> [FAIL][18] ([fdo#103060])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6835/shard-kbl6/igt@kms_flip@dpms-vs-vblank-race.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14276/shard-kbl4/igt@kms_flip@dpms-vs-vblank-race.html
* igt@kms_flip@flip-vs-expired-vblank:
- shard-iclb: [PASS][19] -> [FAIL][20] ([fdo#105363])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6835/shard-iclb1/igt@kms_flip@flip-vs-expired-vblank.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14276/shard-iclb3/igt@kms_flip@flip-vs-expired-vblank.html
* igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-blt:
- shard-iclb: [PASS][21] -> [FAIL][22] ([fdo#103167]) +3 similar issues
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6835/shard-iclb3/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-blt.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14276/shard-iclb7/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-blt.html
* igt@kms_panel_fitting@atomic-fastset:
- shard-skl: [PASS][23] -> [FAIL][24] ([fdo#109052])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6835/shard-skl4/igt@kms_panel_fitting@atomic-fastset.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14276/shard-skl7/igt@kms_panel_fitting@atomic-fastset.html
- shard-iclb: [PASS][25] -> [FAIL][26] ([fdo#109052])
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6835/shard-iclb4/igt@kms_panel_fitting@atomic-fastset.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14276/shard-iclb2/igt@kms_panel_fitting@atomic-fastset.html
* igt@kms_panel_fitting@legacy:
- shard-skl: [PASS][27] -> [FAIL][28] ([fdo#105456])
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6835/shard-skl3/igt@kms_panel_fitting@legacy.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14276/shard-skl5/igt@kms_panel_fitting@legacy.html
* igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min:
- shard-skl: [PASS][29] -> [FAIL][30] ([fdo#108145])
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6835/shard-skl7/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14276/shard-skl10/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min.html
* igt@kms_psr@psr2_sprite_mmap_gtt:
- shard-iclb: [PASS][31] -> [SKIP][32] ([fdo#109441]) +1 similar issue
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6835/shard-iclb2/igt@kms_psr@psr2_sprite_mmap_gtt.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14276/shard-iclb3/igt@kms_psr@psr2_sprite_mmap_gtt.html
* igt@kms_vblank@pipe-a-ts-continuation-suspend:
- shard-hsw: [PASS][33] -> [FAIL][34] ([fdo#103375])
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6835/shard-hsw8/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14276/shard-hsw8/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
* igt@kms_vblank@pipe-b-ts-continuation-suspend:
- shard-apl: [PASS][35] -> [DMESG-WARN][36] ([fdo#108566])
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6835/shard-apl8/igt@kms_vblank@pipe-b-ts-continuation-suspend.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14276/shard-apl4/igt@kms_vblank@pipe-b-ts-continuation-suspend.html
* igt@prime_vgem@fence-wait-bsd2:
- shard-iclb: [PASS][37] -> [SKIP][38] ([fdo#109276]) +15 similar issues
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6835/shard-iclb4/igt@prime_vgem@fence-wait-bsd2.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14276/shard-iclb6/igt@prime_vgem@fence-wait-bsd2.html
#### Possible fixes ####
* igt@gem_exec_schedule@pi-ringfull-bsd:
- shard-iclb: [SKIP][39] ([fdo#111325]) -> [PASS][40] +4 similar issues
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6835/shard-iclb2/igt@gem_exec_schedule@pi-ringfull-bsd.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14276/shard-iclb3/igt@gem_exec_schedule@pi-ringfull-bsd.html
* igt@gem_exec_schedule@preempt-queue-bsd1:
- shard-iclb: [SKIP][41] ([fdo#109276]) -> [PASS][42] +18 similar issues
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6835/shard-iclb8/igt@gem_exec_schedule@preempt-queue-bsd1.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14276/shard-iclb2/igt@gem_exec_schedule@preempt-queue-bsd1.html
* igt@gem_mocs_settings@mocs-rc6-blt:
- shard-apl: [SKIP][43] ([fdo#109271]) -> [PASS][44]
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6835/shard-apl5/igt@gem_mocs_settings@mocs-rc6-blt.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14276/shard-apl7/igt@gem_mocs_settings@mocs-rc6-blt.html
* igt@gem_tiled_swapping@non-threaded:
- shard-kbl: [DMESG-WARN][45] ([fdo#108686]) -> [PASS][46]
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6835/shard-kbl6/igt@gem_tiled_swapping@non-threaded.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14276/shard-kbl7/igt@gem_tiled_swapping@non-threaded.html
* igt@gem_workarounds@suspend-resume-context:
- shard-apl: [DMESG-WARN][47] ([fdo#108566]) -> [PASS][48] +4 similar issues
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6835/shard-apl7/igt@gem_workarounds@suspend-resume-context.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14276/shard-apl5/igt@gem_workarounds@suspend-resume-context.html
- shard-kbl: [INCOMPLETE][49] ([fdo#103665]) -> [PASS][50]
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6835/shard-kbl2/igt@gem_workarounds@suspend-resume-context.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14276/shard-kbl6/igt@gem_workarounds@suspend-resume-context.html
* igt@i915_suspend@fence-restore-tiled2untiled:
- shard-skl: [INCOMPLETE][51] ([fdo#104108]) -> [PASS][52]
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6835/shard-skl3/igt@i915_suspend@fence-restore-tiled2untiled.html
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14276/shard-skl3/igt@i915_suspend@fence-restore-tiled2untiled.html
* igt@kms_flip@2x-plain-flip-fb-recreate:
- shard-glk: [FAIL][53] ([fdo#100368]) -> [PASS][54]
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6835/shard-glk3/igt@kms_flip@2x-plain-flip-fb-recreate.html
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14276/shard-glk7/igt@kms_flip@2x-plain-flip-fb-recreate.html
* igt@kms_flip@flip-vs-expired-vblank:
- shard-skl: [FAIL][55] ([fdo#105363]) -> [PASS][56] +1 similar issue
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6835/shard-skl8/igt@kms_flip@flip-vs-expired-vblank.html
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14276/shard-skl7/igt@kms_flip@flip-vs-expired-vblank.html
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-shrfb-msflip-blt:
- shard-iclb: [FAIL][57] ([fdo#103167]) -> [PASS][58] +2 similar issues
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6835/shard-iclb6/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-shrfb-msflip-blt.html
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14276/shard-iclb8/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-shrfb-msflip-blt.html
* igt@kms_frontbuffer_tracking@fbc-suspend:
- shard-apl: [FAIL][59] ([fdo#103375]) -> [PASS][60]
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6835/shard-apl5/igt@kms_frontbuffer_tracking@fbc-suspend.html
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14276/shard-apl6/igt@kms_frontbuffer_tracking@fbc-suspend.html
* igt@kms_psr2_su@page_flip:
- shard-iclb: [SKIP][61] ([fdo#109642] / [fdo#111068]) -> [PASS][62]
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6835/shard-iclb8/igt@kms_psr2_su@page_flip.html
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14276/shard-iclb2/igt@kms_psr2_su@page_flip.html
* igt@kms_psr@no_drrs:
- shard-iclb: [FAIL][63] ([fdo#108341]) -> [PASS][64]
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6835/shard-iclb1/igt@kms_psr@no_drrs.html
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14276/shard-iclb6/igt@kms_psr@no_drrs.html
* igt@kms_psr@psr2_sprite_blt:
- shard-iclb: [SKIP][65] ([fdo#109441]) -> [PASS][66] +1 similar issue
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6835/shard-iclb4/igt@kms_psr@psr2_sprite_blt.html
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14276/shard-iclb2/igt@kms_psr@psr2_sprite_blt.html
* igt@perf_pmu@busy-double-start-vcs0:
- shard-apl: [FAIL][67] ([fdo#111545]) -> [PASS][68] +4 similar issues
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6835/shard-apl5/igt@perf_pmu@busy-double-start-vcs0.html
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14276/shard-apl6/igt@perf_pmu@busy-double-start-vcs0.html
#### Warnings ####
* igt@gem_mocs_settings@mocs-settings-bsd2:
- shard-iclb: [FAIL][69] ([fdo#111330]) -> [SKIP][70] ([fdo#109276]) +2 similar issues
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6835/shard-iclb1/igt@gem_mocs_settings@mocs-settings-bsd2.html
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14276/shard-iclb6/igt@gem_mocs_settings@mocs-settings-bsd2.html
* igt@gem_softpin@noreloc-s3:
- shard-apl: [FAIL][71] ([fdo#103375]) -> [DMESG-WARN][72] ([fdo#108566]) +2 similar issues
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6835/shard-apl5/igt@gem_softpin@noreloc-s3.html
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14276/shard-apl7/igt@gem_softpin@noreloc-s3.html
* igt@i915_pm_rpm@dpms-lpsp:
- shard-hsw: [SKIP][73] ([fdo#109271]) -> [FAIL][74] ([fdo#111548])
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6835/shard-hsw6/igt@i915_pm_rpm@dpms-lpsp.html
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14276/shard-hsw8/igt@i915_pm_rpm@dpms-lpsp.html
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-mmap-gtt:
- shard-skl: [FAIL][75] ([fdo#103167]) -> [FAIL][76] ([fdo#108040])
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6835/shard-skl3/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-mmap-gtt.html
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14276/shard-skl5/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-mmap-gtt.html
* igt@perf_pmu@cpu-hotplug:
- shard-hsw: [INCOMPLETE][77] ([fdo#103540]) -> [TIMEOUT][78] ([fdo#111546])
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6835/shard-hsw4/igt@perf_pmu@cpu-hotplug.html
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14276/shard-hsw8/igt@perf_pmu@cpu-hotplug.html
[fdo#100368]: https://bugs.freedesktop.org/show_bug.cgi?id=100368
[fdo#103060]: https://bugs.freedesktop.org/show_bug.cgi?id=103060
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#103359]: https://bugs.freedesktop.org/show_bug.cgi?id=103359
[fdo#103375]: https://bugs.freedesktop.org/show_bug.cgi?id=103375
[fdo#103540]: https://bugs.freedesktop.org/show_bug.cgi?id=103540
[fdo#103665]: https://bugs.freedesktop.org/show_bug.cgi?id=103665
[fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
[fdo#104108]: https://bugs.freedesktop.org/show_bug.cgi?id=104108
[fdo#105363]: https://bugs.freedesktop.org/show_bug.cgi?id=105363
[fdo#105456]: https://bugs.freedesktop.org/show_bug.cgi?id=105456
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#108040]: https://bugs.freedesktop.org/show_bug.cgi?id=108040
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#108341]: https://bugs.freedesktop.org/show_bug.cgi?id=108341
[fdo#108566]: https://bugs.freedesktop.org/show_bug.cgi?id=108566
[fdo#108686]: https://bugs.freedesktop.org/show_bug.cgi?id=108686
[fdo#108840]: https://bugs.freedesktop.org/show_bug.cgi?id=108840
[fdo#109052]: https://bugs.freedesktop.org/show_bug.cgi?id=109052
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642
[fdo#110841]: https://bugs.freedesktop.org/show_bug.cgi?id=110841
[fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
[fdo#111325]: https://bugs.freedesktop.org/show_bug.cgi?id=111325
[fdo#111330]: https://bugs.freedesktop.org/show_bug.cgi?id=111330
[fdo#111545]: https://bugs.freedesktop.org/show_bug.cgi?id=111545
[fdo#111546]: https://bugs.freedesktop.org/show_bug.cgi?id=111546
[fdo#111548]: https://bugs.freedesktop.org/show_bug.cgi?id=111548
[k.org#198133]: https://bugzilla.kernel.org/show_bug.cgi?id=198133
Participating hosts (10 -> 9)
------------------------------
Missing (1): pig-hsw-4770r
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_6835 -> Patchwork_14276
CI-20190529: 20190529
CI_DRM_6835: cde3db21383e3c077c278ba783e4ec8d006f2e32 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5171: 1911564805fe454919e8a5846534a0c1ef376a33 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_14276: 11794db5ae4124dff1f0fb0252e1b143edcbd48b @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14276/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 27+ messages in thread* ✗ Fi.CI.SPARSE: warning for drm/i915: Expose margin connector properties for underscan (rev4)
2019-09-04 16:26 [PATCH 00/15] drm/i915: Expose margin connector properties for underscan Ville Syrjala
` (18 preceding siblings ...)
2019-09-04 20:08 ` ✗ Fi.CI.IGT: failure " Patchwork
@ 2019-09-05 11:06 ` Patchwork
2019-09-05 11:29 ` ✓ Fi.CI.BAT: success " Patchwork
2019-09-05 12:52 ` ✓ Fi.CI.IGT: " Patchwork
21 siblings, 0 replies; 27+ messages in thread
From: Patchwork @ 2019-09-05 11:06 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Expose margin connector properties for underscan (rev4)
URL : https://patchwork.freedesktop.org/series/66225/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.6.0
Commit: drm/edid: Add drm_hdmi_avi_infoframe_bars()
Okay!
Commit: drm/i915: Parametrize PFIT_PIPE
Okay!
Commit: drm/i915: Replace some accidental I915_READ_FW()s with the normal version
Okay!
Commit: drm/i915: Fix skl+ non-scaled pfit modes
Okay!
Commit: drm/i915: Flatten a bunch of the pfit functions
Okay!
Commit: drm/i915: Use drm_rect to store the pfit window pos/size
Okay!
Commit: drm/i915: Check pipe source size against pfit limits
Okay!
Commit: drm/i915: Check pfit scaling factors
Okay!
Commit: drm/i915: Check pfit minimum timings
Okay!
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 27+ messages in thread* ✓ Fi.CI.BAT: success for drm/i915: Expose margin connector properties for underscan (rev4)
2019-09-04 16:26 [PATCH 00/15] drm/i915: Expose margin connector properties for underscan Ville Syrjala
` (19 preceding siblings ...)
2019-09-05 11:06 ` ✗ Fi.CI.SPARSE: warning for drm/i915: Expose margin connector properties for underscan (rev4) Patchwork
@ 2019-09-05 11:29 ` Patchwork
2019-09-05 12:52 ` ✓ Fi.CI.IGT: " Patchwork
21 siblings, 0 replies; 27+ messages in thread
From: Patchwork @ 2019-09-05 11:29 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Expose margin connector properties for underscan (rev4)
URL : https://patchwork.freedesktop.org/series/66225/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6838 -> Patchwork_14282
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14282/
Known issues
------------
Here are the changes found in Patchwork_14282 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_exec_suspend@basic-s4-devices:
- fi-blb-e6850: [PASS][1] -> [INCOMPLETE][2] ([fdo#107718])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6838/fi-blb-e6850/igt@gem_exec_suspend@basic-s4-devices.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14282/fi-blb-e6850/igt@gem_exec_suspend@basic-s4-devices.html
* igt@kms_chamelium@dp-hpd-fast:
- fi-icl-u2: [PASS][3] -> [DMESG-WARN][4] ([fdo#110595])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6838/fi-icl-u2/igt@kms_chamelium@dp-hpd-fast.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14282/fi-icl-u2/igt@kms_chamelium@dp-hpd-fast.html
* igt@prime_self_import@basic-with_one_bo:
- fi-icl-u3: [PASS][5] -> [DMESG-WARN][6] ([fdo#107724])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6838/fi-icl-u3/igt@prime_self_import@basic-with_one_bo.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14282/fi-icl-u3/igt@prime_self_import@basic-with_one_bo.html
#### Possible fixes ####
* igt@gem_mmap_gtt@basic:
- fi-glk-dsi: [INCOMPLETE][7] ([fdo#103359] / [k.org#198133]) -> [PASS][8]
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6838/fi-glk-dsi/igt@gem_mmap_gtt@basic.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14282/fi-glk-dsi/igt@gem_mmap_gtt@basic.html
* igt@kms_busy@basic-flip-c:
- fi-skl-6770hq: [SKIP][9] ([fdo#109271] / [fdo#109278]) -> [PASS][10] +2 similar issues
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6838/fi-skl-6770hq/igt@kms_busy@basic-flip-c.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14282/fi-skl-6770hq/igt@kms_busy@basic-flip-c.html
* igt@kms_chamelium@dp-edid-read:
- fi-kbl-7500u: [WARN][11] ([fdo#109483]) -> [PASS][12]
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6838/fi-kbl-7500u/igt@kms_chamelium@dp-edid-read.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14282/fi-kbl-7500u/igt@kms_chamelium@dp-edid-read.html
* igt@kms_flip@basic-flip-vs-dpms:
- fi-skl-6770hq: [SKIP][13] ([fdo#109271]) -> [PASS][14] +23 similar issues
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6838/fi-skl-6770hq/igt@kms_flip@basic-flip-vs-dpms.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14282/fi-skl-6770hq/igt@kms_flip@basic-flip-vs-dpms.html
* igt@kms_frontbuffer_tracking@basic:
- fi-hsw-peppy: [DMESG-WARN][15] ([fdo#102614]) -> [PASS][16]
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6838/fi-hsw-peppy/igt@kms_frontbuffer_tracking@basic.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14282/fi-hsw-peppy/igt@kms_frontbuffer_tracking@basic.html
- fi-icl-u2: [FAIL][17] ([fdo#103167]) -> [PASS][18]
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6838/fi-icl-u2/igt@kms_frontbuffer_tracking@basic.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14282/fi-icl-u2/igt@kms_frontbuffer_tracking@basic.html
* igt@vgem_basic@debugfs:
- fi-icl-u3: [DMESG-WARN][19] ([fdo#107724]) -> [PASS][20]
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6838/fi-icl-u3/igt@vgem_basic@debugfs.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14282/fi-icl-u3/igt@vgem_basic@debugfs.html
[fdo#102614]: https://bugs.freedesktop.org/show_bug.cgi?id=102614
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#103359]: https://bugs.freedesktop.org/show_bug.cgi?id=103359
[fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
[fdo#109483]: https://bugs.freedesktop.org/show_bug.cgi?id=109483
[fdo#110595]: https://bugs.freedesktop.org/show_bug.cgi?id=110595
[k.org#198133]: https://bugzilla.kernel.org/show_bug.cgi?id=198133
Participating hosts (53 -> 45)
------------------------------
Additional (1): fi-pnv-d510
Missing (9): fi-kbl-soraka fi-ilk-m540 fi-tgl-u fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-icl-y fi-byt-clapper fi-bdw-samus
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_6838 -> Patchwork_14282
CI-20190529: 20190529
CI_DRM_6838: 8e907b7591b620dba402c7ada493a31ca0320c99 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5171: 1911564805fe454919e8a5846534a0c1ef376a33 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_14282: 665f407f9346de4c06d766ea641a1643e3470174 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
665f407f9346 drm/i915: Expose margin properties on DP MST
981d7717f519 drm/i915: Expose margin properties on ilk+ DP SST
7348b8e4b3a8 drm/i915: Expose margin properties on ilk+ HDMI
75f3f222894e drm/i915: Have pfit calculations return an error code
ea19a851798c drm/i915: Pass connector state to pfit calculations
1bbd58e4cf0d drm/i915: s/pipe_config/crtc_state/ in pfit functions
01937b30ea10 drm/i915: Check pfit minimum timings
fbf5ca58370d drm/i915: Check pfit scaling factors
b1d29067e05c drm/i915: Check pipe source size against pfit limits
fab3def7bd73 drm/i915: Use drm_rect to store the pfit window pos/size
f4255b96e6af drm/i915: Flatten a bunch of the pfit functions
4cb5e7ca4b13 drm/i915: Fix skl+ non-scaled pfit modes
d9910ff31981 drm/i915: Replace some accidental I915_READ_FW()s with the normal version
b33bb98c81cf drm/i915: Parametrize PFIT_PIPE
6b63f4b51393 drm/edid: Add drm_hdmi_avi_infoframe_bars()
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14282/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 27+ messages in thread* ✓ Fi.CI.IGT: success for drm/i915: Expose margin connector properties for underscan (rev4)
2019-09-04 16:26 [PATCH 00/15] drm/i915: Expose margin connector properties for underscan Ville Syrjala
` (20 preceding siblings ...)
2019-09-05 11:29 ` ✓ Fi.CI.BAT: success " Patchwork
@ 2019-09-05 12:52 ` Patchwork
21 siblings, 0 replies; 27+ messages in thread
From: Patchwork @ 2019-09-05 12:52 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Expose margin connector properties for underscan (rev4)
URL : https://patchwork.freedesktop.org/series/66225/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6838_full -> Patchwork_14282_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Known issues
------------
Here are the changes found in Patchwork_14282_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_exec_balancer@indices:
- shard-apl: [PASS][1] -> [SKIP][2] ([fdo#109271])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6838/shard-apl1/igt@gem_exec_balancer@indices.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14282/shard-apl8/igt@gem_exec_balancer@indices.html
* igt@gem_exec_schedule@pi-ringfull-bsd:
- shard-apl: [PASS][3] -> [FAIL][4] ([fdo#111547])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6838/shard-apl1/igt@gem_exec_schedule@pi-ringfull-bsd.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14282/shard-apl8/igt@gem_exec_schedule@pi-ringfull-bsd.html
* igt@gem_exec_schedule@preempt-queue-contexts-render:
- shard-kbl: [PASS][5] -> [INCOMPLETE][6] ([fdo#103665]) +1 similar issue
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6838/shard-kbl4/igt@gem_exec_schedule@preempt-queue-contexts-render.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14282/shard-kbl1/igt@gem_exec_schedule@preempt-queue-contexts-render.html
* igt@gem_exec_schedule@preemptive-hang-bsd:
- shard-iclb: [PASS][7] -> [SKIP][8] ([fdo#111325]) +7 similar issues
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6838/shard-iclb6/igt@gem_exec_schedule@preemptive-hang-bsd.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14282/shard-iclb4/igt@gem_exec_schedule@preemptive-hang-bsd.html
* igt@gem_exec_schedule@promotion-bsd1:
- shard-iclb: [PASS][9] -> [SKIP][10] ([fdo#109276]) +18 similar issues
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6838/shard-iclb4/igt@gem_exec_schedule@promotion-bsd1.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14282/shard-iclb7/igt@gem_exec_schedule@promotion-bsd1.html
* igt@gem_exec_suspend@basic-s3-devices:
- shard-hsw: [PASS][11] -> [FAIL][12] ([fdo#111550])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6838/shard-hsw8/igt@gem_exec_suspend@basic-s3-devices.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14282/shard-hsw2/igt@gem_exec_suspend@basic-s3-devices.html
* igt@gem_tiled_swapping@non-threaded:
- shard-apl: [PASS][13] -> [DMESG-WARN][14] ([fdo#108686])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6838/shard-apl5/igt@gem_tiled_swapping@non-threaded.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14282/shard-apl2/igt@gem_tiled_swapping@non-threaded.html
* igt@gem_workarounds@suspend-resume-context:
- shard-apl: [PASS][15] -> [DMESG-WARN][16] ([fdo#108566]) +2 similar issues
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6838/shard-apl6/igt@gem_workarounds@suspend-resume-context.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14282/shard-apl6/igt@gem_workarounds@suspend-resume-context.html
* igt@i915_pm_rpm@debugfs-forcewake-user:
- shard-hsw: [PASS][17] -> [FAIL][18] ([fdo#111548]) +1 similar issue
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6838/shard-hsw8/igt@i915_pm_rpm@debugfs-forcewake-user.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14282/shard-hsw2/igt@i915_pm_rpm@debugfs-forcewake-user.html
* igt@i915_suspend@forcewake:
- shard-snb: [PASS][19] -> [FAIL][20] ([fdo#103375]) +3 similar issues
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6838/shard-snb2/igt@i915_suspend@forcewake.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14282/shard-snb4/igt@i915_suspend@forcewake.html
- shard-hsw: [PASS][21] -> [FAIL][22] ([fdo#103375]) +3 similar issues
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6838/shard-hsw8/igt@i915_suspend@forcewake.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14282/shard-hsw2/igt@i915_suspend@forcewake.html
* igt@kms_flip@dpms-vs-vblank-race:
- shard-kbl: [PASS][23] -> [FAIL][24] ([fdo#103060])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6838/shard-kbl6/igt@kms_flip@dpms-vs-vblank-race.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14282/shard-kbl2/igt@kms_flip@dpms-vs-vblank-race.html
* igt@kms_flip@flip-vs-expired-vblank:
- shard-glk: [PASS][25] -> [FAIL][26] ([fdo#105363]) +1 similar issue
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6838/shard-glk7/igt@kms_flip@flip-vs-expired-vblank.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14282/shard-glk9/igt@kms_flip@flip-vs-expired-vblank.html
* igt@kms_flip@flip-vs-suspend-interruptible:
- shard-apl: [PASS][27] -> [FAIL][28] ([fdo#103375]) +2 similar issues
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6838/shard-apl1/igt@kms_flip@flip-vs-suspend-interruptible.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14282/shard-apl8/igt@kms_flip@flip-vs-suspend-interruptible.html
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-mmap-gtt:
- shard-skl: [PASS][29] -> [FAIL][30] ([fdo#103167])
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6838/shard-skl2/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-mmap-gtt.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14282/shard-skl10/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-mmap-gtt.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-render:
- shard-iclb: [PASS][31] -> [FAIL][32] ([fdo#103167]) +2 similar issues
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6838/shard-iclb1/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-render.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14282/shard-iclb8/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-render.html
* igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes:
- shard-skl: [PASS][33] -> [FAIL][34] ([fdo#103166])
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6838/shard-skl9/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14282/shard-skl3/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html
* igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes:
- shard-skl: [PASS][35] -> [INCOMPLETE][36] ([fdo#104108])
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6838/shard-skl6/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14282/shard-skl5/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html
* igt@kms_psr@psr2_primary_mmap_cpu:
- shard-iclb: [PASS][37] -> [SKIP][38] ([fdo#109441]) +1 similar issue
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6838/shard-iclb2/igt@kms_psr@psr2_primary_mmap_cpu.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14282/shard-iclb5/igt@kms_psr@psr2_primary_mmap_cpu.html
* igt@kms_setmode@basic:
- shard-hsw: [PASS][39] -> [FAIL][40] ([fdo#99912])
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6838/shard-hsw7/igt@kms_setmode@basic.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14282/shard-hsw7/igt@kms_setmode@basic.html
* igt@perf_pmu@init-wait-rcs0:
- shard-apl: [PASS][41] -> [FAIL][42] ([fdo#111545]) +7 similar issues
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6838/shard-apl1/igt@perf_pmu@init-wait-rcs0.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14282/shard-apl8/igt@perf_pmu@init-wait-rcs0.html
* igt@prime_busy@hang-vebox:
- shard-hsw: [PASS][43] -> [INCOMPLETE][44] ([fdo#103540])
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6838/shard-hsw2/igt@prime_busy@hang-vebox.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14282/shard-hsw6/igt@prime_busy@hang-vebox.html
#### Possible fixes ####
* igt@gem_ctx_shared@exec-single-timeline-bsd:
- shard-iclb: [SKIP][45] ([fdo#110841]) -> [PASS][46]
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6838/shard-iclb1/igt@gem_ctx_shared@exec-single-timeline-bsd.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14282/shard-iclb8/igt@gem_ctx_shared@exec-single-timeline-bsd.html
* igt@gem_exec_reloc@basic-gtt-active:
- shard-skl: [DMESG-WARN][47] ([fdo#106107]) -> [PASS][48]
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6838/shard-skl5/igt@gem_exec_reloc@basic-gtt-active.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14282/shard-skl2/igt@gem_exec_reloc@basic-gtt-active.html
* igt@gem_exec_schedule@preempt-other-chain-bsd:
- shard-iclb: [SKIP][49] ([fdo#111325]) -> [PASS][50] +2 similar issues
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6838/shard-iclb2/igt@gem_exec_schedule@preempt-other-chain-bsd.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14282/shard-iclb5/igt@gem_exec_schedule@preempt-other-chain-bsd.html
* igt@gem_exec_schedule@preempt-queue-bsd1:
- shard-iclb: [SKIP][51] ([fdo#109276]) -> [PASS][52] +18 similar issues
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6838/shard-iclb6/igt@gem_exec_schedule@preempt-queue-bsd1.html
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14282/shard-iclb4/igt@gem_exec_schedule@preempt-queue-bsd1.html
* igt@gem_request_retire@retire-vma-not-inactive:
- shard-apl: [INCOMPLETE][53] ([fdo#103927]) -> [PASS][54] +1 similar issue
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6838/shard-apl6/igt@gem_request_retire@retire-vma-not-inactive.html
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14282/shard-apl3/igt@gem_request_retire@retire-vma-not-inactive.html
* igt@gem_softpin@noreloc-s3:
- shard-skl: [INCOMPLETE][55] ([fdo#104108] / [fdo#107773]) -> [PASS][56]
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6838/shard-skl1/igt@gem_softpin@noreloc-s3.html
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14282/shard-skl10/igt@gem_softpin@noreloc-s3.html
* igt@i915_pm_rc6_residency@rc6-accuracy:
- shard-snb: [SKIP][57] ([fdo#109271]) -> [PASS][58]
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6838/shard-snb4/igt@i915_pm_rc6_residency@rc6-accuracy.html
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14282/shard-snb1/igt@i915_pm_rc6_residency@rc6-accuracy.html
* igt@i915_pm_rpm@system-suspend:
- shard-hsw: [FAIL][59] ([fdo#111548]) -> [PASS][60] +4 similar issues
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6838/shard-hsw2/igt@i915_pm_rpm@system-suspend.html
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14282/shard-hsw4/igt@i915_pm_rpm@system-suspend.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible:
- shard-skl: [FAIL][61] ([fdo#105363]) -> [PASS][62]
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6838/shard-skl5/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14282/shard-skl10/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
* igt@kms_frontbuffer_tracking@fbc-suspend:
- shard-apl: [DMESG-WARN][63] ([fdo#108566]) -> [PASS][64] +1 similar issue
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6838/shard-apl5/igt@kms_frontbuffer_tracking@fbc-suspend.html
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14282/shard-apl2/igt@kms_frontbuffer_tracking@fbc-suspend.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-pwrite:
- shard-iclb: [FAIL][65] ([fdo#103167]) -> [PASS][66] +5 similar issues
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6838/shard-iclb7/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-pwrite.html
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14282/shard-iclb1/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-pwrite.html
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
- shard-snb: [FAIL][67] ([fdo#103375]) -> [PASS][68] +2 similar issues
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6838/shard-snb7/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14282/shard-snb7/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html
* igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes:
- shard-kbl: [INCOMPLETE][69] ([fdo#103665]) -> [PASS][70]
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6838/shard-kbl3/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14282/shard-kbl7/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html
* igt@kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes:
- shard-hsw: [FAIL][71] ([fdo#103375]) -> [PASS][72] +6 similar issues
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6838/shard-hsw2/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes.html
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14282/shard-hsw7/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes.html
* igt@kms_plane_cursor@pipe-c-viewport-size-256:
- shard-iclb: [INCOMPLETE][73] ([fdo#107713]) -> [PASS][74] +1 similar issue
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6838/shard-iclb1/igt@kms_plane_cursor@pipe-c-viewport-size-256.html
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14282/shard-iclb8/igt@kms_plane_cursor@pipe-c-viewport-size-256.html
* igt@kms_psr2_su@frontbuffer:
- shard-iclb: [SKIP][75] ([fdo#109642] / [fdo#111068]) -> [PASS][76]
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6838/shard-iclb5/igt@kms_psr2_su@frontbuffer.html
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14282/shard-iclb2/igt@kms_psr2_su@frontbuffer.html
* igt@kms_psr@psr2_sprite_plane_move:
- shard-iclb: [SKIP][77] ([fdo#109441]) -> [PASS][78] +2 similar issues
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6838/shard-iclb5/igt@kms_psr@psr2_sprite_plane_move.html
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14282/shard-iclb2/igt@kms_psr@psr2_sprite_plane_move.html
* igt@kms_setmode@basic:
- shard-apl: [FAIL][79] ([fdo#99912]) -> [PASS][80]
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6838/shard-apl8/igt@kms_setmode@basic.html
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14282/shard-apl5/igt@kms_setmode@basic.html
* igt@perf@blocking:
- shard-skl: [FAIL][81] ([fdo#110728]) -> [PASS][82]
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6838/shard-skl7/igt@perf@blocking.html
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14282/shard-skl9/igt@perf@blocking.html
#### Warnings ####
* igt@gem_mocs_settings@mocs-settings-bsd2:
- shard-iclb: [SKIP][83] ([fdo#109276]) -> [FAIL][84] ([fdo#111330]) +1 similar issue
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6838/shard-iclb6/igt@gem_mocs_settings@mocs-settings-bsd2.html
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14282/shard-iclb2/igt@gem_mocs_settings@mocs-settings-bsd2.html
[fdo#103060]: https://bugs.freedesktop.org/show_bug.cgi?id=103060
[fdo#103166]: https://bugs.freedesktop.org/show_bug.cgi?id=103166
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#103375]: https://bugs.freedesktop.org/show_bug.cgi?id=103375
[fdo#103540]: https://bugs.freedesktop.org/show_bug.cgi?id=103540
[fdo#103665]: https://bugs.freedesktop.org/show_bug.cgi?id=103665
[fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
[fdo#104108]: https://bugs.freedesktop.org/show_bug.cgi?id=104108
[fdo#105363]: https://bugs.freedesktop.org/show_bug.cgi?id=105363
[fdo#106107]: https://bugs.freedesktop.org/show_bug.cgi?id=106107
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107773]: https://bugs.freedesktop.org/show_bug.cgi?id=107773
[fdo#108566]: https://bugs.freedesktop.org/show_bug.cgi?id=108566
[fdo#108686]: https://bugs.freedesktop.org/show_bug.cgi?id=108686
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642
[fdo#110728]: https://bugs.freedesktop.org/show_bug.cgi?id=110728
[fdo#110841]: https://bugs.freedesktop.org/show_bug.cgi?id=110841
[fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
[fdo#111325]: https://bugs.freedesktop.org/show_bug.cgi?id=111325
[fdo#111330]: https://bugs.freedesktop.org/show_bug.cgi?id=111330
[fdo#111545]: https://bugs.freedesktop.org/show_bug.cgi?id=111545
[fdo#111547]: https://bugs.freedesktop.org/show_bug.cgi?id=111547
[fdo#111548]: https://bugs.freedesktop.org/show_bug.cgi?id=111548
[fdo#111550]: https://bugs.freedesktop.org/show_bug.cgi?id=111550
[fdo#99912]: https://bugs.freedesktop.org/show_bug.cgi?id=99912
Participating hosts (10 -> 9)
------------------------------
Missing (1): pig-hsw-4770r
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_6838 -> Patchwork_14282
CI-20190529: 20190529
CI_DRM_6838: 8e907b7591b620dba402c7ada493a31ca0320c99 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5171: 1911564805fe454919e8a5846534a0c1ef376a33 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_14282: 665f407f9346de4c06d766ea641a1643e3470174 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14282/
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