From mboxrd@z Thu Jan 1 00:00:00 1970 From: Rasmus Villemoes Date: Thu, 12 Sep 2019 09:17:11 +0000 Subject: [U-Boot] [PATCH 3/4] arm: mxs: be more careful when enabling gpmi_clk In-Reply-To: <20190912091656.14301-1-rasmus.villemoes@prevas.dk> References: <20190912091656.14301-1-rasmus.villemoes@prevas.dk> Message-ID: <20190912091656.14301-4-rasmus.villemoes@prevas.dk> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de The data sheet says that the DIV field cannot change while the CLKGATE bit is set or modified. So do it a little more carefully, by first clearing the bit, waiting for that to appear, then setting the DIV field. Signed-off-by: Rasmus Villemoes --- arch/arm/cpu/arm926ejs/mxs/mxs.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/arch/arm/cpu/arm926ejs/mxs/mxs.c b/arch/arm/cpu/arm926ejs/mxs/mxs.c index 585c53baf6..183aa40b6d 100644 --- a/arch/arm/cpu/arm926ejs/mxs/mxs.c +++ b/arch/arm/cpu/arm926ejs/mxs/mxs.c @@ -103,8 +103,11 @@ int arch_cpu_init(void) &clkctrl_regs->hw_clkctrl_clkseq_set); /* Set GPMI clock to ref_xtal / 1 */ + clrbits_le32(&clkctrl_regs->hw_clkctrl_gpmi, CLKCTRL_GPMI_CLKGATE); + while (readl(&clkctrl_regs->hw_clkctrl_gpmi) & CLKCTRL_GPMI_CLKGATE) + ; clrsetbits_le32(&clkctrl_regs->hw_clkctrl_gpmi, - CLKCTRL_GPMI_CLKGATE | CLKCTRL_GPMI_DIV_MASK, 1); + CLKCTRL_GPMI_DIV_MASK, 1); udelay(1000); -- 2.20.1