Re: [PATCH] clk: qcom: gcc: Add missing clocks in SM8150

[Stephen Boyd <sboyd@kernel.org>]

Quoting Vinod Koul (2019-09-17 02:16:23)
> The initial upstreaming of SM8150 GCC driver missed few clock so add
> them up now.
> 
> Signed-off-by: Vinod Koul <vkoul@kernel.org>
> ---

Should have some sort of fixes tag?

>  drivers/clk/qcom/gcc-sm8150.c | 172 ++++++++++++++++++++++++++++++++++
>  1 file changed, 172 insertions(+)
> 
> diff --git a/drivers/clk/qcom/gcc-sm8150.c b/drivers/clk/qcom/gcc-sm8150.c
> index 12ca2d14797f..13d4d14a5744 100644
> --- a/drivers/clk/qcom/gcc-sm8150.c
> +++ b/drivers/clk/qcom/gcc-sm8150.c
> @@ -1616,6 +1616,38 @@ static struct clk_branch gcc_gpu_cfg_ahb_clk = {
>         },
>  };
>  
> +static struct clk_branch gcc_gpu_gpll0_clk_src = {
> +       .halt_check = BRANCH_HALT_SKIP,

Why skip?

> +       .clkr = {
> +               .enable_reg = 0x52004,
> +               .enable_mask = BIT(15),
> +               .hw.init = &(struct clk_init_data){
> +                       .name = "gcc_gpu_gpll0_clk_src",
> +                       .parent_hws = (const struct clk_hw *[]){
> +                               &gpll0.clkr.hw },
> +                       .num_parents = 1,
> +                       .flags = CLK_SET_RATE_PARENT,
> +                       .ops = &clk_branch2_ops,
> +               },
> +       },
> +};
> +
> +static struct clk_branch gcc_gpu_gpll0_div_clk_src = {
> +       .halt_check = BRANCH_HALT_SKIP,

Why skip?

> +       .clkr = {
> +               .enable_reg = 0x52004,
> +               .enable_mask = BIT(16),
> +               .hw.init = &(struct clk_init_data){
> +                       .name = "gcc_gpu_gpll0_div_clk_src",
> +                       .parent_hws = (const struct clk_hw *[]){
> +                               &gcc_gpu_gpll0_clk_src.clkr.hw },
> +                       .num_parents = 1,
> +                       .flags = CLK_SET_RATE_PARENT,
> +                       .ops = &clk_branch2_ops,
> +               },
> +       },
> +};
> +
>  static struct clk_branch gcc_gpu_iref_clk = {
>         .halt_reg = 0x8c010,
>         .halt_check = BRANCH_HALT,
> @@ -1698,6 +1730,38 @@ static struct clk_branch gcc_npu_cfg_ahb_clk = {
>         },
>  };
>  
> +static struct clk_branch gcc_npu_gpll0_clk_src = {
> +       .halt_check = BRANCH_HALT_SKIP,
> +       .clkr = {
> +               .enable_reg = 0x52004,
> +               .enable_mask = BIT(18),
> +               .hw.init = &(struct clk_init_data){
> +                       .name = "gcc_npu_gpll0_clk_src",
> +                       .parent_hws = (const struct clk_hw *[]){
> +                               &gpll0.clkr.hw },
> +                       .num_parents = 1,
> +                       .flags = CLK_SET_RATE_PARENT,
> +                       .ops = &clk_branch2_ops,
> +               },
> +       },
> +};
> +
> +static struct clk_branch gcc_npu_gpll0_div_clk_src = {
> +       .halt_check = BRANCH_HALT_SKIP,
> +       .clkr = {
> +               .enable_reg = 0x52004,
> +               .enable_mask = BIT(19),
> +               .hw.init = &(struct clk_init_data){
> +                       .name = "gcc_npu_gpll0_div_clk_src",
> +                       .parent_hws = (const struct clk_hw *[]){
> +                               &gcc_npu_gpll0_clk_src.clkr.hw },
> +                       .num_parents = 1,
> +                       .flags = CLK_SET_RATE_PARENT,
> +                       .ops = &clk_branch2_ops,
> +               },
> +       },
> +};
> +
>  static struct clk_branch gcc_npu_trig_clk = {
>         .halt_reg = 0x4d00c,
>         .halt_check = BRANCH_VOTED,
> @@ -2812,6 +2876,42 @@ static struct clk_branch gcc_ufs_card_phy_aux_hw_ctl_clk = {
>         },
>  };
>  
> +static struct clk_branch gcc_ufs_card_rx_symbol_0_clk = {
> +       .halt_check = BRANCH_HALT_SKIP,

Can't we fix the UFS driver to not require this anymore? This is the
fourth or fifth time I've asked for this.

> +       .clkr = {
> +               .enable_reg = 0x7501c,
> +               .enable_mask = BIT(0),
> +               .hw.init = &(struct clk_init_data){
> +                       .name = "gcc_ufs_card_rx_symbol_0_clk",
> +                       .ops = &clk_branch2_ops,
> +               },
> +       },
> +};
> +
> +static struct clk_branch gcc_ufs_card_rx_symbol_1_clk = {
> +       .halt_check = BRANCH_HALT_SKIP,
> +       .clkr = {
> +               .enable_reg = 0x750ac,
> +               .enable_mask = BIT(0),
> +               .hw.init = &(struct clk_init_data){
> +                       .name = "gcc_ufs_card_rx_symbol_1_clk",
> +                       .ops = &clk_branch2_ops,
> +               },
> +       },
> +};
> +
> +static struct clk_branch gcc_ufs_card_tx_symbol_0_clk = {
> +       .halt_check = BRANCH_HALT_SKIP,
> +       .clkr = {
> +               .enable_reg = 0x75018,
> +               .enable_mask = BIT(0),
> +               .hw.init = &(struct clk_init_data){
> +                       .name = "gcc_ufs_card_tx_symbol_0_clk",
> +                       .ops = &clk_branch2_ops,
> +               },
> +       },
> +};
> +
>  static struct clk_branch gcc_ufs_card_unipro_core_clk = {
>         .halt_reg = 0x75058,
>         .halt_check = BRANCH_HALT,