From: Jitao Shi <jitao.shi@mediatek.com>
To: CK Hu <ck.hu@mediatek.com>, David Airlie <airlied@linux.ie>,
Daniel Vetter <daniel@ffwll.ch>,
dri-devel@lists.freedesktop.org
Cc: Jitao Shi <jitao.shi@mediatek.com>,
srv_heupstream@mediatek.com, stonea168@163.com,
cawa.cheng@mediatek.com, sj.huang@mediatek.com,
linux-mediatek@lists.infradead.org,
Matthias Brugger <matthias.bgg@gmail.com>,
yingjoe.chen@mediatek.com, eddie.huang@mediatek.com
Subject: [PATCH v7 9/9] drm/mediatek: add dphy reset after setting lanes number
Date: Thu, 19 Sep 2019 14:58:06 +0800 [thread overview]
Message-ID: <20190919065806.111016-10-jitao.shi@mediatek.com> (raw)
In-Reply-To: <20190919065806.111016-1-jitao.shi@mediatek.com>
Add dphy reset after setting lanes number to avoid dphy fifo effor.
Signed-off-by: Jitao Shi <jitao.shi@mediatek.com>
---
drivers/gpu/drm/mediatek/mtk_dsi.c | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c b/drivers/gpu/drm/mediatek/mtk_dsi.c
index b02373b04848..8c2620ea18d0 100644
--- a/drivers/gpu/drm/mediatek/mtk_dsi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dsi.c
@@ -37,6 +37,7 @@
#define DSI_CON_CTRL 0x10
#define DSI_RESET BIT(0)
#define DSI_EN BIT(1)
+#define DPHY_RESET BIT(2)
#define DSI_MODE_CTRL 0x14
#define MODE (3)
@@ -280,6 +281,12 @@ static void mtk_dsi_reset_engine(struct mtk_dsi *dsi)
mtk_dsi_mask(dsi, DSI_CON_CTRL, DSI_RESET, 0);
}
+static void mtk_dsi_reset_dphy(struct mtk_dsi *dsi)
+{
+ mtk_dsi_mask(dsi, DSI_CON_CTRL, DPHY_RESET, DPHY_RESET);
+ mtk_dsi_mask(dsi, DSI_CON_CTRL, DPHY_RESET, 0);
+}
+
static void mtk_dsi_clk_ulp_mode_enter(struct mtk_dsi *dsi)
{
mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_HS_TX_EN, 0);
@@ -650,6 +657,8 @@ static int mtk_dsi_poweron(struct mtk_dsi *dsi)
mtk_dsi_phy_timconfig(dsi);
mtk_dsi_rxtx_control(dsi);
+ usleep_range(30, 100);
+ mtk_dsi_reset_dphy(dsi);
mtk_dsi_ps_control_vact(dsi);
mtk_dsi_set_vm_cmd(dsi);
mtk_dsi_config_vdo_timing(dsi);
--
2.21.0
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next prev parent reply other threads:[~2019-09-19 6:58 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-09-19 6:57 [PATCH v7 0/9] Support dsi for mt8183 Jitao Shi
2019-09-19 6:57 ` [PATCH v7 1/9] drm/mediatek: move mipi_dsi_host_register to probe Jitao Shi
2019-09-19 6:57 ` [PATCH v7 2/9] drm/mediatek: fixes CMDQ reg address of mt8173 is different with mt2701 Jitao Shi
2019-09-26 8:50 ` CK Hu
2019-09-19 6:58 ` [PATCH v7 3/9] drm/mediatek: replace writeb() with mtk_dsi_mask() Jitao Shi
2019-09-26 8:50 ` CK Hu
2019-09-19 6:58 ` [PATCH v7 4/9] drm/mediatek: add dsi reg commit disable control Jitao Shi
2019-09-19 6:58 ` [PATCH v7 5/9] drm/mediatek: add frame size control Jitao Shi
2019-09-19 6:58 ` [PATCH v7 6/9] drm/mediatek: add mt8183 dsi driver support Jitao Shi
2019-09-19 6:58 ` [PATCH v7 7/9] drm/mediatek: change the dsi phytiming calculate method Jitao Shi
2019-09-26 8:51 ` CK Hu
2019-12-12 13:53 ` Enric Balletbo Serra
2019-12-12 13:53 ` Enric Balletbo Serra
2019-12-12 22:47 ` Ryan Case
2019-12-12 22:47 ` Ryan Case
2019-12-13 2:45 ` CK Hu
2019-12-13 2:45 ` CK Hu
2019-09-19 6:58 ` [PATCH v7 8/9] drm: mediatek: adjust dsi and mipi_tx probe sequence Jitao Shi
2019-09-19 6:58 ` Jitao Shi [this message]
2019-09-26 8:52 ` [PATCH v7 9/9] drm/mediatek: add dphy reset after setting lanes number CK Hu
2019-09-27 1:35 ` [PATCH v7 0/9] Support dsi for mt8183 CK Hu
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