All of lore.kernel.org
 help / color / mirror / Atom feed
From: James Ausmus <james.ausmus@intel.com>
To: "Summers, Stuart" <stuart.summers@intel.com>
Cc: "intel-gfx@lists.freedesktop.org" <intel-gfx@lists.freedesktop.org>
Subject: Re: [PATCH v2] drm/i915/tgl: Add memory type decoding for bandwidth checking
Date: Wed, 25 Sep 2019 15:39:35 -0700	[thread overview]
Message-ID: <20190925223935.GB25514@jausmus-gentoo-dev6.jf.intel.com> (raw)
In-Reply-To: <ea5a9907e73060039733f2002bb1cad1d5016b41.camel@intel.com>

On Wed, Sep 25, 2019 at 03:35:28PM -0700, Summers, Stuart wrote:
> On Wed, 2019-09-25 at 08:35 -0700, James Ausmus wrote:
> > On Wed, Sep 25, 2019 at 07:33:38AM -0700, Summers, Stuart wrote:
> > > On Tue, 2019-09-24 at 15:28 -0700, James Ausmus wrote:
> > > > The memory type values have changed in TGL, so we need to
> > > > translate
> > > > them
> > > > differently than ICL. While we're moving it, fix up the ICL
> > > > translation
> > > > for LPDDR4.
> > > > 
> > > > BSpec: 53998
> > > > 
> > > > v2: Fix up ICL LPDDR4 entry (Ville); Drop unused values from TGL
> > > > (Ville)
> > > > 
> > > > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > > Cc: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> > > > Signed-off-by: James Ausmus <james.ausmus@intel.com>
> > > > Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > > ---
> > > >  drivers/gpu/drm/i915/display/intel_bw.c | 55 ++++++++++++++++++-
> > > > ----
> > > > --
> > > >  1 file changed, 39 insertions(+), 16 deletions(-)
> > > > 
> > > > diff --git a/drivers/gpu/drm/i915/display/intel_bw.c
> > > > b/drivers/gpu/drm/i915/display/intel_bw.c
> > > > index cd58e47ab7b2..22e83f857de8 100644
> > > > --- a/drivers/gpu/drm/i915/display/intel_bw.c
> > > > +++ b/drivers/gpu/drm/i915/display/intel_bw.c
> > > > @@ -35,22 +35,45 @@ static int
> > > > icl_pcode_read_mem_global_info(struct
> > > > drm_i915_private *dev_priv,
> > > >  	if (ret)
> > > >  		return ret;
> > > >  
> > > > -	switch (val & 0xf) {
> > > > -	case 0:
> > > > -		qi->dram_type = INTEL_DRAM_DDR4;
> > > > -		break;
> > > > -	case 1:
> > > > -		qi->dram_type = INTEL_DRAM_DDR3;
> > > > -		break;
> > > > -	case 2:
> > > > -		qi->dram_type = INTEL_DRAM_LPDDR3;
> > > > -		break;
> > > > -	case 3:
> > > > -		qi->dram_type = INTEL_DRAM_LPDDR3;
> > > > -		break;
> > > > -	default:
> > > > -		MISSING_CASE(val & 0xf);
> > > > -		break;
> > > > +	if (IS_GEN(dev_priv, 12)) {
> > > > +		switch (val & 0xf) {
> > > > +		case 0:
> > > > +			qi->dram_type = INTEL_DRAM_DDR4;
> > > > +			break;
> > > > +		case 3:
> > > > +			qi->dram_type = INTEL_DRAM_LPDDR4;
> > > > +			break;
> > > > +		case 4:
> > > > +			qi->dram_type = INTEL_DRAM_DDR3;
> > > > +			break;
> > > > +		case 5:
> > > > +			qi->dram_type = INTEL_DRAM_LPDDR3;
> > > > +			break;
> > > > +		default:
> > > > +			MISSING_CASE(val & 0xf);
> > > > +			break;
> > > > +		}
> > > > +	} else if (IS_GEN(dev_priv, 11)) {
> > > > +		switch (val & 0xf) {
> > > > +		case 0:
> > > > +			qi->dram_type = INTEL_DRAM_DDR4;
> > > > +			break;
> > > > +		case 1:
> > > > +			qi->dram_type = INTEL_DRAM_DDR3;
> > > > +			break;
> > > > +		case 2:
> > > > +			qi->dram_type = INTEL_DRAM_LPDDR3;
> > > > +			break;
> > > > +		case 3:
> > > > +			qi->dram_type = INTEL_DRAM_LPDDR4;
> > > > +			break;
> > > > +		default:
> > > > +			MISSING_CASE(val & 0xf);
> > > > +			break;
> > > 
> > > James, is there a reason we can't just combine these two conditions
> > > into one switch statement? At initial glance it looks like the
> > > cases
> > > are the same for the common ones and the only real difference is
> > > the
> > > supported bits.
> > 
> > The info I got from the HW guys indicates that the same values are
> > very
> > likely to have different meanings for different gens, and likely to
> > even
> > have different values for variants of a single gen, so as more
> > platforms
> > are added in the future, a single switch would get very messy. Even
> > now,
> > I think it would be fairly ugly, as it would look something like:
> > 
> > switch (val) {
> > 	case 0:
> > 		DDR4;
> > 	case 1:
> > 		if (GEN == 11)
> > 			DDR3;
> > 		else
> > 			MISSING_CASE(val);
> > 	case 2:
> > 		if (GEN == 11)
> > 			LPDDR3;
> > 		else
> > 			MISSING_CASE(val);
> > 	case 3:
> > 		LPDDR4;
> > 	case 4:
> > 		if (GEN == 12)
> > 			DDR3;
> > 		else
> > 			MISSING_CASE(val);
> > 	case 5:
> > 		if (GEN == 12)
> > 			LPDDR3;
> > 		else
> > 			MISSING_CASE(val);
> > }
> > 
> > And then start adding special cases for variants within a gen, as
> > well
> > as additional gen checks, and I think it starts looking fairly
> > spaghetti. :)
> 
> I understand and thanks for the explanation. Your reasoning makes sense
> to me.
> 
> I checked bspec and confirmed the TGL entries look right. We also spoke
> in IRC and I agree with the changes you're making for ICL. With that:
> 
> Reviewed-by: Stuart Summers <stuart.summers@intel.com>

Thanks for the review!

-James

> 
> > 
> > -James
> > 
> > > 
> > > Thanks,
> > > Stuart
> > > 
> > > > +		}
> > > > +	} else {
> > > > +		MISSING_CASE(INTEL_GEN(dev_priv));
> > > > +		qi->dram_type = INTEL_DRAM_LPDDR3; /* Conservative
> > > > default */
> > > >  	}
> > > >  
> > > >  	qi->num_channels = (val & 0xf0) >> 4;
> > 
> > 


_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

  reply	other threads:[~2019-09-25 22:38 UTC|newest]

Thread overview: 7+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-09-24 22:28 [PATCH v2] drm/i915/tgl: Add memory type decoding for bandwidth checking James Ausmus
2019-09-24 23:25 ` ✓ Fi.CI.BAT: success for " Patchwork
2019-09-25 14:33 ` [PATCH v2] " Summers, Stuart
2019-09-25 15:35   ` James Ausmus
2019-09-25 22:35     ` Summers, Stuart
2019-09-25 22:39       ` James Ausmus [this message]
2019-09-25 18:54 ` ✓ Fi.CI.IGT: success for " Patchwork

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20190925223935.GB25514@jausmus-gentoo-dev6.jf.intel.com \
    --to=james.ausmus@intel.com \
    --cc=intel-gfx@lists.freedesktop.org \
    --cc=stuart.summers@intel.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.