From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.6 required=3.0 tests=DKIM_INVALID,DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 573A5C4360C for ; Fri, 27 Sep 2019 06:23:22 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 212B8206B7 for ; Fri, 27 Sep 2019 06:23:22 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=gibson.dropbear.id.au header.i=@gibson.dropbear.id.au header.b="MO+8iuLf" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 212B8206B7 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=gibson.dropbear.id.au Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Received: from localhost ([::1]:46848 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iDjey-0006ik-ND for qemu-devel@archiver.kernel.org; Fri, 27 Sep 2019 02:23:20 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:47990) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iDj9u-0007Ww-L4 for qemu-devel@nongnu.org; Fri, 27 Sep 2019 01:51:16 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iDj9s-0005hS-F3 for qemu-devel@nongnu.org; Fri, 27 Sep 2019 01:51:14 -0400 Received: from ozlabs.org ([2401:3900:2:1::2]:41935) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1iDj9r-00058Y-UD; Fri, 27 Sep 2019 01:51:12 -0400 Received: by ozlabs.org (Postfix, from userid 1007) id 46fgrH0MK6z9sRd; Fri, 27 Sep 2019 15:50:38 +1000 (AEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1569563439; bh=JmUXPhsV8ShVtITBG1Xm7PwhWkcDYo0Kq/AlPDVCEk4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=MO+8iuLfiJIy1FXRghcSpUavdUJ5Y0/mP0AbeJUnAFeUTJb7741h0ghfRlAT1Au7E hWcJo+JPo+VX+WCtOpPI1h7+b/ybaTYMEEO3yZNGDB0QBdUb9pkvCmoR+PEfg2bhbj Ytzr5l/wGhorKQxd1Sbk8CQf1Ft8NYcaQciSgeSw= From: David Gibson To: qemu-devel@nongnu.org, clg@kaod.org, qemu-ppc@nongnu.org Subject: [PATCH v2 29/33] spapr, xics, xive: Move SpaprIrq::reset hook logic into activate/deactivate Date: Fri, 27 Sep 2019 15:50:24 +1000 Message-Id: <20190927055028.11493-30-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190927055028.11493-1-david@gibson.dropbear.id.au> References: <20190927055028.11493-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2401:3900:2:1::2 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jason Wang , Riku Voipio , groug@kaod.org, Laurent Vivier , Paolo Bonzini , =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , philmd@redhat.com, David Gibson Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" It turns out that all the logic in the SpaprIrq::reset hooks (and some in the SpaprIrq::post_load hooks) isn't really related to resetting the irq backend (that's handled by the backends' own reset routines). Rather its about getting the backend ready to be the active interrupt controller or stopping being the active interrupt controller - reset (and post_load) is just the only time that changes at present. To make this flow clearer, move the logic into the explicit backend activate and deactivate hooks. Signed-off-by: David Gibson --- hw/intc/spapr_xive.c | 35 ++++++++++++++++++++ hw/intc/xics_spapr.c | 16 +++++++++ hw/ppc/spapr_irq.c | 67 ++------------------------------------ include/hw/ppc/spapr_irq.h | 4 ++- 4 files changed, 57 insertions(+), 65 deletions(-) diff --git a/hw/intc/spapr_xive.c b/hw/intc/spapr_xive.c index 37ffb74ca5..e8b946982c 100644 --- a/hw/intc/spapr_xive.c +++ b/hw/intc/spapr_xive.c @@ -640,6 +640,39 @@ static void spapr_xive_dt(SpaprInterruptController *= intc, uint32_t nr_servers, plat_res_int_priorities, sizeof(plat_res_int_priori= ties))); } =20 +static void spapr_xive_activate(SpaprInterruptController *intc, Error **= errp) +{ + SpaprXive *xive =3D SPAPR_XIVE(intc); + CPUState *cs; + + CPU_FOREACH(cs) { + PowerPCCPU *cpu =3D POWERPC_CPU(cs); + + /* (TCG) Set the OS CAM line of the thread interrupt context. */ + spapr_xive_set_tctx_os_cam(spapr_cpu_state(cpu)->tctx); + } + + if (kvm_enabled()) { + if (spapr_irq_init_kvm(kvmppc_xive_connect, intc, errp) < 0) { + return; + } + } + + /* Activate the XIVE MMIOs */ + spapr_xive_mmio_set_enabled(xive, true); +} + +static void spapr_xive_deactivate(SpaprInterruptController *intc) +{ + SpaprXive *xive =3D SPAPR_XIVE(intc); + + spapr_xive_mmio_set_enabled(xive, false); + + if (kvm_irqchip_in_kernel()) { + kvmppc_xive_disconnect(intc); + } +} + static void spapr_xive_class_init(ObjectClass *klass, void *data) { DeviceClass *dc =3D DEVICE_CLASS(klass); @@ -658,6 +691,8 @@ static void spapr_xive_class_init(ObjectClass *klass,= void *data) xrc->write_nvt =3D spapr_xive_write_nvt; xrc->get_tctx =3D spapr_xive_get_tctx; =20 + sicc->activate =3D spapr_xive_activate; + sicc->deactivate =3D spapr_xive_deactivate; sicc->cpu_intc_create =3D spapr_xive_cpu_intc_create; sicc->claim_irq =3D spapr_xive_claim_irq; sicc->free_irq =3D spapr_xive_free_irq; diff --git a/hw/intc/xics_spapr.c b/hw/intc/xics_spapr.c index 4eabafc7e1..8abbc799ba 100644 --- a/hw/intc/xics_spapr.c +++ b/hw/intc/xics_spapr.c @@ -395,6 +395,20 @@ static void xics_spapr_print_info(SpaprInterruptCont= roller *intc, Monitor *mon) ics_pic_print_info(ics, mon); } =20 +static void xics_spapr_activate(SpaprInterruptController *intc, Error **= errp) +{ + if (kvm_enabled()) { + spapr_irq_init_kvm(xics_kvm_connect, intc, errp); + } +} + +static void xics_spapr_deactivate(SpaprInterruptController *intc) +{ + if (kvm_irqchip_in_kernel()) { + xics_kvm_disconnect(intc); + } +} + static void ics_spapr_class_init(ObjectClass *klass, void *data) { DeviceClass *dc =3D DEVICE_CLASS(klass); @@ -403,6 +417,8 @@ static void ics_spapr_class_init(ObjectClass *klass, = void *data) =20 device_class_set_parent_realize(dc, ics_spapr_realize, &isc->parent_realize); + sicc->activate =3D xics_spapr_activate; + sicc->deactivate =3D xics_spapr_deactivate; sicc->cpu_intc_create =3D xics_spapr_cpu_intc_create; sicc->claim_irq =3D xics_spapr_claim_irq; sicc->free_irq =3D xics_spapr_free_irq; diff --git a/hw/ppc/spapr_irq.c b/hw/ppc/spapr_irq.c index c6abebc4ef..2fd9dd0ec2 100644 --- a/hw/ppc/spapr_irq.c +++ b/hw/ppc/spapr_irq.c @@ -65,9 +65,9 @@ void spapr_irq_msi_free(SpaprMachineState *spapr, int i= rq, uint32_t num) bitmap_clear(spapr->irq_map, irq - SPAPR_IRQ_MSI, num); } =20 -static int spapr_irq_init_kvm(int (*fn)(SpaprInterruptController *, Erro= r **), - SpaprInterruptController *intc, - Error **errp) +int spapr_irq_init_kvm(int (*fn)(SpaprInterruptController *, Error **), + SpaprInterruptController *intc, + Error **errp) { MachineState *machine =3D MACHINE(qdev_get_machine()); Error *local_err =3D NULL; @@ -112,11 +112,6 @@ static int spapr_irq_post_load_xics(SpaprMachineStat= e *spapr, int version_id) return 0; } =20 -static void spapr_irq_reset_xics(SpaprMachineState *spapr, Error **errp) -{ - spapr_irq_init_kvm(xics_kvm_connect, SPAPR_INTC(spapr->ics), errp); -} - SpaprIrq spapr_irq_xics =3D { .nr_xirqs =3D SPAPR_NR_XIRQS, .nr_msis =3D SPAPR_NR_MSIS, @@ -124,7 +119,6 @@ SpaprIrq spapr_irq_xics =3D { .xive =3D false, =20 .post_load =3D spapr_irq_post_load_xics, - .reset =3D spapr_irq_reset_xics, }; =20 /* @@ -136,26 +130,6 @@ static int spapr_irq_post_load_xive(SpaprMachineStat= e *spapr, int version_id) return spapr_xive_post_load(spapr->xive, version_id); } =20 -static void spapr_irq_reset_xive(SpaprMachineState *spapr, Error **errp) -{ - CPUState *cs; - - CPU_FOREACH(cs) { - PowerPCCPU *cpu =3D POWERPC_CPU(cs); - - /* (TCG) Set the OS CAM line of the thread interrupt context. */ - spapr_xive_set_tctx_os_cam(spapr_cpu_state(cpu)->tctx); - } - - if (spapr_irq_init_kvm(kvmppc_xive_connect, - SPAPR_INTC(spapr->xive), errp) < 0) { - return; - } - - /* Activate the XIVE MMIOs */ - spapr_xive_mmio_set_enabled(spapr->xive, true); -} - SpaprIrq spapr_irq_xive =3D { .nr_xirqs =3D SPAPR_NR_XIRQS, .nr_msis =3D SPAPR_NR_MSIS, @@ -163,7 +137,6 @@ SpaprIrq spapr_irq_xive =3D { .xive =3D true, =20 .post_load =3D spapr_irq_post_load_xive, - .reset =3D spapr_irq_reset_xive, }; =20 /* @@ -187,37 +160,9 @@ static SpaprIrq *spapr_irq_current(SpaprMachineState= *spapr) =20 static int spapr_irq_post_load_dual(SpaprMachineState *spapr, int versio= n_id) { - /* - * Force a reset of the XIVE backend after migration. The machine - * defaults to XICS at startup. - */ - if (spapr_ovec_test(spapr->ov5_cas, OV5_XIVE_EXPLOIT)) { - if (kvm_irqchip_in_kernel()) { - xics_kvm_disconnect(SPAPR_INTC(spapr->ics)); - } - spapr_irq_xive.reset(spapr, &error_fatal); - } - return spapr_irq_current(spapr)->post_load(spapr, version_id); } =20 -static void spapr_irq_reset_dual(SpaprMachineState *spapr, Error **errp) -{ - /* - * Deactivate the XIVE MMIOs. The XIVE backend will reenable them - * if selected. - */ - spapr_xive_mmio_set_enabled(spapr->xive, false); - - /* Destroy all KVM devices */ - if (kvm_irqchip_in_kernel()) { - xics_kvm_disconnect(SPAPR_INTC(spapr->ics)); - kvmppc_xive_disconnect(SPAPR_INTC(spapr->xive)); - } - - spapr_irq_current(spapr)->reset(spapr, errp); -} - /* * Define values in sync with the XIVE and XICS backend */ @@ -228,7 +173,6 @@ SpaprIrq spapr_irq_dual =3D { .xive =3D true, =20 .post_load =3D spapr_irq_post_load_dual, - .reset =3D spapr_irq_reset_dual, }; =20 =20 @@ -519,10 +463,6 @@ void spapr_irq_reset(SpaprMachineState *spapr, Error= **errp) assert(!spapr->irq_map || bitmap_empty(spapr->irq_map, spapr->irq_ma= p_nr)); =20 spapr_irq_update_active_intc(spapr); - - if (spapr->irq->reset) { - spapr->irq->reset(spapr, errp); - } } =20 int spapr_irq_get_phandle(SpaprMachineState *spapr, void *fdt, Error **e= rrp) @@ -658,7 +598,6 @@ SpaprIrq spapr_irq_xics_legacy =3D { .xive =3D false, =20 .post_load =3D spapr_irq_post_load_xics, - .reset =3D spapr_irq_reset_xics, }; =20 static void spapr_irq_register_types(void) diff --git a/include/hw/ppc/spapr_irq.h b/include/hw/ppc/spapr_irq.h index c947f40571..28044d7479 100644 --- a/include/hw/ppc/spapr_irq.h +++ b/include/hw/ppc/spapr_irq.h @@ -84,7 +84,6 @@ typedef struct SpaprIrq { bool xive; =20 int (*post_load)(SpaprMachineState *spapr, int version_id); - void (*reset)(SpaprMachineState *spapr, Error **errp); } SpaprIrq; =20 extern SpaprIrq spapr_irq_xics; @@ -99,6 +98,9 @@ qemu_irq spapr_qirq(SpaprMachineState *spapr, int irq); int spapr_irq_post_load(SpaprMachineState *spapr, int version_id); void spapr_irq_reset(SpaprMachineState *spapr, Error **errp); int spapr_irq_get_phandle(SpaprMachineState *spapr, void *fdt, Error **e= rrp); +int spapr_irq_init_kvm(int (*fn)(SpaprInterruptController *, Error **), + SpaprInterruptController *intc, + Error **errp); =20 /* * XICS legacy routines --=20 2.21.0