From mboxrd@z Thu Jan 1 00:00:00 1970 From: Jagan Teki Date: Sun, 29 Sep 2019 13:12:35 +0530 Subject: [U-Boot] [PATCH 1/5] riscv: dts: Add hifive-unleashed-a00 dts from Linux In-Reply-To: <20190929074239.11575-1-jagan@amarulasolutions.com> References: <20190929074239.11575-1-jagan@amarulasolutions.com> Message-ID: <20190929074239.11575-2-jagan@amarulasolutions.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable To: u-boot@lists.denx.de Sync the hifive-unleashed-a00 dts from Linux with below commit details: commit 11ae2d892139a1086f257188d457ddcb71ab5257 Author: Paul Walmsley Date: Thu Jul 25 13:41:31 2019 -0700 riscv: dts: fu540-c000: drop "timebase-frequency" Idea is to periodically sync the dts from Linux instead of tweeking internal changes one after another, so better not add any intermediate changes in between.=C2=A0This would help to maintain the dts files easy and meaningful since we are reusing devicetree files from Linux. Signed-off-by: Jagan Teki --- arch/riscv/dts/Makefile | 1 + arch/riscv/dts/fu540-c000.dtsi | 235 ++++++++++++++++++++++++ arch/riscv/dts/hifive-unleashed-a00.dts | 88 +++++++++ 3 files changed, 324 insertions(+) create mode 100644 arch/riscv/dts/fu540-c000.dtsi create mode 100644 arch/riscv/dts/hifive-unleashed-a00.dts diff --git a/arch/riscv/dts/Makefile b/arch/riscv/dts/Makefile index f9cd606a9a..4f30e6936f 100644 --- a/arch/riscv/dts/Makefile +++ b/arch/riscv/dts/Makefile @@ -1,6 +1,7 @@ # SPDX-License-Identifier: GPL-2.0+ =20 dtb-$(CONFIG_TARGET_AX25_AE350) +=3D ae350_32.dtb ae350_64.dtb +dtb-$(CONFIG_TARGET_SIFIVE_FU540) +=3D hifive-unleashed-a00.dtb =20 targets +=3D $(dtb-y) =20 diff --git a/arch/riscv/dts/fu540-c000.dtsi b/arch/riscv/dts/fu540-c000.dtsi new file mode 100644 index 0000000000..42b5ec2231 --- /dev/null +++ b/arch/riscv/dts/fu540-c000.dtsi @@ -0,0 +1,235 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* Copyright (c) 2018-2019 SiFive, Inc */ + +/dts-v1/; + +#include + +/ { + #address-cells =3D <2>; + #size-cells =3D <2>; + compatible =3D "sifive,fu540-c000", "sifive,fu540"; + + aliases { + serial0 =3D &uart0; + serial1 =3D &uart1; + }; + + chosen { + }; + + cpus { + #address-cells =3D <1>; + #size-cells =3D <0>; + cpu0: cpu at 0 { + compatible =3D "sifive,e51", "sifive,rocket0", "riscv"; + device_type =3D "cpu"; + i-cache-block-size =3D <64>; + i-cache-sets =3D <128>; + i-cache-size =3D <16384>; + reg =3D <0>; + riscv,isa =3D "rv64imac"; + status =3D "disabled"; + cpu0_intc: interrupt-controller { + #interrupt-cells =3D <1>; + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + }; + }; + cpu1: cpu at 1 { + compatible =3D "sifive,u54-mc", "sifive,rocket0", "riscv"; + d-cache-block-size =3D <64>; + d-cache-sets =3D <64>; + d-cache-size =3D <32768>; + d-tlb-sets =3D <1>; + d-tlb-size =3D <32>; + device_type =3D "cpu"; + i-cache-block-size =3D <64>; + i-cache-sets =3D <64>; + i-cache-size =3D <32768>; + i-tlb-sets =3D <1>; + i-tlb-size =3D <32>; + mmu-type =3D "riscv,sv39"; + reg =3D <1>; + riscv,isa =3D "rv64imafdc"; + tlb-split; + cpu1_intc: interrupt-controller { + #interrupt-cells =3D <1>; + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + }; + }; + cpu2: cpu at 2 { + clock-frequency =3D <0>; + compatible =3D "sifive,u54-mc", "sifive,rocket0", "riscv"; + d-cache-block-size =3D <64>; + d-cache-sets =3D <64>; + d-cache-size =3D <32768>; + d-tlb-sets =3D <1>; + d-tlb-size =3D <32>; + device_type =3D "cpu"; + i-cache-block-size =3D <64>; + i-cache-sets =3D <64>; + i-cache-size =3D <32768>; + i-tlb-sets =3D <1>; + i-tlb-size =3D <32>; + mmu-type =3D "riscv,sv39"; + reg =3D <2>; + riscv,isa =3D "rv64imafdc"; + tlb-split; + cpu2_intc: interrupt-controller { + #interrupt-cells =3D <1>; + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + }; + }; + cpu3: cpu at 3 { + clock-frequency =3D <0>; + compatible =3D "sifive,u54-mc", "sifive,rocket0", "riscv"; + d-cache-block-size =3D <64>; + d-cache-sets =3D <64>; + d-cache-size =3D <32768>; + d-tlb-sets =3D <1>; + d-tlb-size =3D <32>; + device_type =3D "cpu"; + i-cache-block-size =3D <64>; + i-cache-sets =3D <64>; + i-cache-size =3D <32768>; + i-tlb-sets =3D <1>; + i-tlb-size =3D <32>; + mmu-type =3D "riscv,sv39"; + reg =3D <3>; + riscv,isa =3D "rv64imafdc"; + tlb-split; + cpu3_intc: interrupt-controller { + #interrupt-cells =3D <1>; + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + }; + }; + cpu4: cpu at 4 { + clock-frequency =3D <0>; + compatible =3D "sifive,u54-mc", "sifive,rocket0", "riscv"; + d-cache-block-size =3D <64>; + d-cache-sets =3D <64>; + d-cache-size =3D <32768>; + d-tlb-sets =3D <1>; + d-tlb-size =3D <32>; + device_type =3D "cpu"; + i-cache-block-size =3D <64>; + i-cache-sets =3D <64>; + i-cache-size =3D <32768>; + i-tlb-sets =3D <1>; + i-tlb-size =3D <32>; + mmu-type =3D "riscv,sv39"; + reg =3D <4>; + riscv,isa =3D "rv64imafdc"; + tlb-split; + cpu4_intc: interrupt-controller { + #interrupt-cells =3D <1>; + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + }; + }; + }; + soc { + #address-cells =3D <2>; + #size-cells =3D <2>; + compatible =3D "sifive,fu540-c000", "sifive,fu540", "simple-bus"; + ranges; + plic0: interrupt-controller at c000000 { + #interrupt-cells =3D <1>; + compatible =3D "sifive,plic-1.0.0"; + reg =3D <0x0 0xc000000 0x0 0x4000000>; + riscv,ndev =3D <53>; + interrupt-controller; + interrupts-extended =3D < + &cpu0_intc 0xffffffff + &cpu1_intc 0xffffffff &cpu1_intc 9 + &cpu2_intc 0xffffffff &cpu2_intc 9 + &cpu3_intc 0xffffffff &cpu3_intc 9 + &cpu4_intc 0xffffffff &cpu4_intc 9>; + }; + prci: clock-controller at 10000000 { + compatible =3D "sifive,fu540-c000-prci"; + reg =3D <0x0 0x10000000 0x0 0x1000>; + clocks =3D <&hfclk>, <&rtcclk>; + #clock-cells =3D <1>; + }; + uart0: serial at 10010000 { + compatible =3D "sifive,fu540-c000-uart", "sifive,uart0"; + reg =3D <0x0 0x10010000 0x0 0x1000>; + interrupt-parent =3D <&plic0>; + interrupts =3D <4>; + clocks =3D <&prci PRCI_CLK_TLCLK>; + status =3D "disabled"; + }; + uart1: serial at 10011000 { + compatible =3D "sifive,fu540-c000-uart", "sifive,uart0"; + reg =3D <0x0 0x10011000 0x0 0x1000>; + interrupt-parent =3D <&plic0>; + interrupts =3D <5>; + clocks =3D <&prci PRCI_CLK_TLCLK>; + status =3D "disabled"; + }; + i2c0: i2c at 10030000 { + compatible =3D "sifive,fu540-c000-i2c", "sifive,i2c0"; + reg =3D <0x0 0x10030000 0x0 0x1000>; + interrupt-parent =3D <&plic0>; + interrupts =3D <50>; + clocks =3D <&prci PRCI_CLK_TLCLK>; + reg-shift =3D <2>; + reg-io-width =3D <1>; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + qspi0: spi at 10040000 { + compatible =3D "sifive,fu540-c000-spi", "sifive,spi0"; + reg =3D <0x0 0x10040000 0x0 0x1000 + 0x0 0x20000000 0x0 0x10000000>; + interrupt-parent =3D <&plic0>; + interrupts =3D <51>; + clocks =3D <&prci PRCI_CLK_TLCLK>; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + qspi1: spi at 10041000 { + compatible =3D "sifive,fu540-c000-spi", "sifive,spi0"; + reg =3D <0x0 0x10041000 0x0 0x1000 + 0x0 0x30000000 0x0 0x10000000>; + interrupt-parent =3D <&plic0>; + interrupts =3D <52>; + clocks =3D <&prci PRCI_CLK_TLCLK>; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + qspi2: spi at 10050000 { + compatible =3D "sifive,fu540-c000-spi", "sifive,spi0"; + reg =3D <0x0 0x10050000 0x0 0x1000>; + interrupt-parent =3D <&plic0>; + interrupts =3D <6>; + clocks =3D <&prci PRCI_CLK_TLCLK>; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + eth0: ethernet at 10090000 { + compatible =3D "sifive,fu540-c000-gem"; + interrupt-parent =3D <&plic0>; + interrupts =3D <53>; + reg =3D <0x0 0x10090000 0x0 0x2000 + 0x0 0x100a0000 0x0 0x1000>; + local-mac-address =3D [00 00 00 00 00 00]; + clock-names =3D "pclk", "hclk"; + clocks =3D <&prci PRCI_CLK_GEMGXLPLL>, + <&prci PRCI_CLK_GEMGXLPLL>; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + + }; +}; diff --git a/arch/riscv/dts/hifive-unleashed-a00.dts b/arch/riscv/dts/hifiv= e-unleashed-a00.dts new file mode 100644 index 0000000000..7397b740b4 --- /dev/null +++ b/arch/riscv/dts/hifive-unleashed-a00.dts @@ -0,0 +1,88 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* Copyright (c) 2018-2019 SiFive, Inc */ + +#include "fu540-c000.dtsi" + +/* Clock frequency (in Hz) of the PCB crystal for rtcclk */ +#define RTCCLK_FREQ 1000000 + +/ { + #address-cells =3D <2>; + #size-cells =3D <2>; + model =3D "SiFive HiFive Unleashed A00"; + compatible =3D "sifive,hifive-unleashed-a00", "sifive,fu540-c000"; + + chosen { + stdout-path =3D "/soc/serial at 10010000:115200"; + }; + + cpus { + timebase-frequency =3D ; + }; + + memory at 80000000 { + device_type =3D "memory"; + reg =3D <0x0 0x80000000 0x2 0x00000000>; + }; + + soc { + }; + + hfclk: hfclk { + #clock-cells =3D <0>; + compatible =3D "fixed-clock"; + clock-frequency =3D <33333333>; + clock-output-names =3D "hfclk"; + }; + + rtcclk: rtcclk { + #clock-cells =3D <0>; + compatible =3D "fixed-clock"; + clock-frequency =3D ; + clock-output-names =3D "rtcclk"; + }; +}; + +&uart0 { + status =3D "okay"; +}; + +&uart1 { + status =3D "okay"; +}; + +&i2c0 { + status =3D "okay"; +}; + +&qspi0 { + status =3D "okay"; + flash at 0 { + compatible =3D "issi,is25wp256", "jedec,spi-nor"; + reg =3D <0>; + spi-max-frequency =3D <50000000>; + m25p,fast-read; + spi-tx-bus-width =3D <4>; + spi-rx-bus-width =3D <4>; + }; +}; + +&qspi2 { + status =3D "okay"; + mmc at 0 { + compatible =3D "mmc-spi-slot"; + reg =3D <0>; + spi-max-frequency =3D <20000000>; + voltage-ranges =3D <3300 3300>; + disable-wp; + }; +}; + +ð0 { + status =3D "okay"; + phy-mode =3D "gmii"; + phy-handle =3D <&phy0>; + phy0: ethernet-phy at 0 { + reg =3D <0>; + }; +}; --=20 2.18.0.321.gffc6fa0e3