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Fri, 4 Oct 2019 08:01:58 +0000 (UTC) Date: Fri, 4 Oct 2019 10:01:57 +0200 From: Igor Mammedov To: Tao Xu Subject: Re: [PATCH v12 10/11] hmat acpi: Build Memory Side Cache Information Structure(s) Message-ID: <20191004100157.7e3ce374@redhat.com> In-Reply-To: <20190920074349.2616-11-tao3.xu@intel.com> References: <20190920074349.2616-1-tao3.xu@intel.com> <20190920074349.2616-11-tao3.xu@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 2.79 on 10.5.11.12 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.28]); Fri, 04 Oct 2019 08:02:00 +0000 (UTC) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.132.183.28 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: ehabkost@redhat.com, jingqi.liu@intel.com, fan.du@intel.com, qemu-devel@nongnu.org, Daniel Black , Jonathan Cameron , dan.j.williams@intel.com Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On Fri, 20 Sep 2019 15:43:48 +0800 Tao Xu wrote: > From: Liu Jingqi >=20 > This structure describes memory side cache information for memory > proximity domains if the memory side cache is present and the > physical device forms the memory side cache. > The software could use this information to effectively place > the data in memory to maximize the performance of the system > memory that use the memory side cache. >=20 > Reviewed-by: Daniel Black > Reviewed-by: Jonathan Cameron > Signed-off-by: Liu Jingqi > Signed-off-by: Tao Xu > --- >=20 > No changes in v12. >=20 > Changes in v11: > - Move numa option patches forward. > --- > hw/acpi/hmat.c | 64 +++++++++++++++++++++++++++++++++++++++++++++++++- > 1 file changed, 63 insertions(+), 1 deletion(-) >=20 > diff --git a/hw/acpi/hmat.c b/hw/acpi/hmat.c > index e7be849581..6b260eeef5 100644 > --- a/hw/acpi/hmat.c > +++ b/hw/acpi/hmat.c > @@ -160,13 +160,62 @@ static void build_hmat_lb(GArray *table_data, HMAT_= LB_Info *hmat_lb, > } > } > =20 > +/* ACPI 6.3: 5.2.27.5 Memory Side Cache Information Structure: Table 5-1= 47 */ > +static void build_hmat_cache(GArray *table_data, HMAT_Cache_Info *hmat_c= ache) > +{ > + /* > + * Cache Attributes: Bits [3:0] =E2=80=93 Total Cache Levels > + * for this Memory Proximity Domain > + */ > + uint32_t cache_attr =3D hmat_cache->total_levels & 0xF; > + > + /* Bits [7:4] : Cache Level described in this structure */ > + cache_attr |=3D (hmat_cache->level & 0xF) << 4; > + /* Bits [11:8] - Cache Associativity */ > + cache_attr |=3D (hmat_cache->associativity & 0xF) << 8; > + > + /* Bits [15:12] - Write Policy */ > + cache_attr |=3D (hmat_cache->write_policy & 0xF) << 12; s/0xF/0x7/ for Cache Associativity / Write Policy > + > + /* Bits [31:16] - Cache Line size in bytes */ > + cache_attr |=3D (hmat_cache->line_size & 0xFFFF) << 16; > + > + cache_attr =3D cpu_to_le32(cache_attr); > + > + /* Type */ > + build_append_int_noprefix(table_data, 2, 2); > + /* Reserved */ > + build_append_int_noprefix(table_data, 0, 2); > + /* Length */ > + build_append_int_noprefix(table_data, 32, 4); > + /* Proximity Domain for the Memory */ > + build_append_int_noprefix(table_data, hmat_cache->mem_proximity, 4); > + /* Reserved */ > + build_append_int_noprefix(table_data, 0, 4); > + /* Memory Side Cache Size */ > + build_append_int_noprefix(table_data, hmat_cache->size, 8); > + /* Cache Attributes */ > + build_append_int_noprefix(table_data, cache_attr, 4); > + /* Reserved */ > + build_append_int_noprefix(table_data, 0, 2); > + /* > + * Number of SMBIOS handles (n) > + * Linux kernel uses Memory Side Cache Information Structure > + * without SMBIOS entries for now, so set Number of SMBIOS handles > + * as 0. > + */ > + build_append_int_noprefix(table_data, 0, 2); > +} > + > /* Build HMAT sub table structures */ > static void hmat_build_table_structs(GArray *table_data, NumaState *nsta= t) > { > uint16_t flags; > uint32_t *initiator_list =3D NULL; > - int i, j, hrchy, type; > + int i, j, hrchy, type, level; s/level/cache_level/ > HMAT_LB_Info *numa_hmat_lb; > + HMAT_Cache_Info *numa_hmat_cache; > =20 > for (i =3D 0; i < nstat->num_nodes; i++) { > flags =3D 0; > @@ -205,6 +254,19 @@ static void hmat_build_table_structs(GArray *table_d= ata, NumaState *nstat) > } > } > =20 > + /* > + * ACPI 6.3: 5.2.27.5 Memory Side Cache Information Structure: > + * Table 5-147 > + */ > + for (i =3D 0; i < nstat->num_nodes; i++) { > + for (level =3D 0; level <=3D MAX_HMAT_CACHE_LEVEL; level++) { > + numa_hmat_cache =3D nstat->hmat_cache[i][level]; > + if (numa_hmat_cache) { > + build_hmat_cache(table_data, numa_hmat_cache); > + } > + } > + } > + > g_free(initiator_list); > } > =20