From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail.linutronix.de (193.142.43.55:993) by crypto-ml.lab.linutronix.de with IMAP4-SSL for ; 07 Oct 2019 17:56:20 -0000 Received: from mga06.intel.com ([134.134.136.31]) by Galois.linutronix.de with esmtps (TLS1.2:DHE_RSA_AES_256_CBC_SHA256:256) (Exim 4.80) (envelope-from ) id 1iHXF4-0001i8-Sm for speck@linutronix.de; Mon, 07 Oct 2019 19:56:19 +0200 Date: Mon, 7 Oct 2019 10:50:32 -0700 From: Pawan Gupta Subject: [MODERATED] Re: [PATCH v5 03/11] TAAv5 3 Message-ID: <20191007175032.GB5154@guptapadev.amr> References: <5d98396a.1c69fb81.6c7a8.23b1SMTPIN_ADDED_BROKEN@mx.google.com> MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit To: speck@linutronix.de List-ID: > > +void tsx_init(struct cpuinfo_x86 *c) > > +{ > > + if (!tsx_ctrl_is_supported()) > > + return; > > + > > + /* > > + * Default to TSX_CTRL_DISABLE. This is because on certain processors > > + * TSX may be used as part of a speculative side channel attack. > > + */ > > + tsx_ctrl_state = TSX_CTRL_DISABLE; > > + > > + tsx_disable(); > > + /* > > + * tsx_disable() will change the state of the > > + * RTM CPUID bit. Clear it here since it is now > > + * expected to be not set. > > + */ > > + clear_cpu_cap(c, X86_FEATURE_RTM); > > + setup_clear_cpu_cap(X86_FEATURE_RTM); > > You shouldn't be doing both clear_cpu_cap *and* setup_clear_cpu_cap(). > > Also, please fold patch 4 into this patch or at least make the contents > of tsx_init() in this patch make some sense. I will fold patch 4 into this. Thanks, Pawan