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[90.63.244.31]) by smtp.gmail.com with ESMTPSA id s10sm8373770wmf.48.2019.10.10.02.25.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 10 Oct 2019 02:25:34 -0700 (PDT) From: Neil Armstrong To: dri-devel@lists.freedesktop.org Subject: [PATCH 7/7] drm/meson: crtc: add OSD1 plane AFBC commit Date: Thu, 10 Oct 2019 11:25:26 +0200 Message-Id: <20191010092526.10419-8-narmstrong@baylibre.com> X-Mailer: git-send-email 2.22.0 In-Reply-To: <20191010092526.10419-1-narmstrong@baylibre.com> References: <20191010092526.10419-1-narmstrong@baylibre.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20191010_022537_019036_E1AD89FE X-CRM114-Status: GOOD ( 15.02 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: khilman@baylibre.com, linux-amlogic@lists.infradead.org, ayan.halder@arm.com, linux-arm-kernel@lists.infradead.org, Neil Armstrong Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org Finally, setup the VIU registers and start the AFBC decoder at each vsync IRQ to support displaying AFBC encoded buffers on Amlogic GXM and G12A SoCs. Since the DRM core will stop the vsync IRQ after a few interrupts, we need to keep the IRQ enabled while using the AFBC decoder. Signed-off-by: Neil Armstrong --- drivers/gpu/drm/meson/meson_crtc.c | 79 ++++++++++++++++++++++++++++-- 1 file changed, 74 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/meson/meson_crtc.c b/drivers/gpu/drm/meson/meson_crtc.c index d478fa232951..d28efd0dbf11 100644 --- a/drivers/gpu/drm/meson/meson_crtc.c +++ b/drivers/gpu/drm/meson/meson_crtc.c @@ -24,6 +24,7 @@ #include "meson_venc.h" #include "meson_viu.h" #include "meson_vpp.h" +#include "meson_osd_afbcd.h" #define MESON_G12A_VIU_OFFSET 0x5ec0 @@ -35,7 +36,11 @@ struct meson_crtc { struct meson_drm *priv; void (*enable_osd1)(struct meson_drm *priv); void (*enable_vd1)(struct meson_drm *priv); + void (*enable_osd1_afbc)(struct meson_drm *priv); + void (*disable_osd1_afbc)(struct meson_drm *priv); unsigned int viu_offset; + bool vsync_forced; + bool vsync_disabled; }; #define to_meson_crtc(x) container_of(x, struct meson_crtc, base) @@ -46,6 +51,7 @@ static int meson_crtc_enable_vblank(struct drm_crtc *crtc) struct meson_crtc *meson_crtc = to_meson_crtc(crtc); struct meson_drm *priv = meson_crtc->priv; + meson_crtc->vsync_disabled = false; meson_venc_enable_vsync(priv); return 0; @@ -56,7 +62,10 @@ static void meson_crtc_disable_vblank(struct drm_crtc *crtc) struct meson_crtc *meson_crtc = to_meson_crtc(crtc); struct meson_drm *priv = meson_crtc->priv; - meson_venc_disable_vsync(priv); + if (!meson_crtc->vsync_forced) { + meson_crtc->vsync_disabled = true; + meson_venc_disable_vsync(priv); + } } static const struct drm_crtc_funcs meson_crtc_funcs = { @@ -236,6 +245,26 @@ static void meson_crtc_enable_osd1(struct meson_drm *priv) priv->io_base + _REG(VPP_MISC)); } +static void meson_crtc_g12a_enable_osd1_afbc(struct meson_drm *priv) +{ + writel_relaxed(priv->viu.osd1_blk2_cfg4, + priv->io_base + _REG(VIU_OSD1_BLK2_CFG_W4)); + + writel_bits_relaxed(OSD_MEM_LINEAR_ADDR, OSD_MEM_LINEAR_ADDR, + priv->io_base + _REG(VIU_OSD1_CTRL_STAT)); + + writel_relaxed(priv->viu.osd1_blk1_cfg4, + priv->io_base + _REG(VIU_OSD1_BLK1_CFG_W4)); + + meson_viu_g12a_enable_osd1_afbc(priv); + + writel_bits_relaxed(OSD_MEM_LINEAR_ADDR, OSD_MEM_LINEAR_ADDR, + priv->io_base + _REG(VIU_OSD1_CTRL_STAT)); + + writel_bits_relaxed(OSD_MALI_SRC_EN, OSD_MALI_SRC_EN, + priv->io_base + _REG(VIU_OSD1_BLK0_CFG_W0)); +} + static void meson_g12a_crtc_enable_osd1(struct meson_drm *priv) { writel_relaxed(priv->viu.osd_blend_din0_scope_h, @@ -293,6 +322,19 @@ void meson_crtc_irq(struct meson_drm *priv) priv->io_base + _REG(VIU_OSD1_BLK0_CFG_W3)); writel_relaxed(priv->viu.osd1_blk0_cfg[4], priv->io_base + _REG(VIU_OSD1_BLK0_CFG_W4)); + + if (priv->viu.osd1_afbcd) { + if (meson_crtc->enable_osd1_afbc) + meson_crtc->enable_osd1_afbc(priv); + } else { + if (meson_crtc->disable_osd1_afbc) + meson_crtc->disable_osd1_afbc(priv); + if (priv->afbcd.ops) { + priv->afbcd.ops->reset(priv); + priv->afbcd.ops->disable(priv); + } + } + writel_relaxed(priv->viu.osd_sc_ctrl0, priv->io_base + _REG(VPP_OSD_SC_CTRL0)); writel_relaxed(priv->viu.osd_sc_i_wh_m1, @@ -314,15 +356,23 @@ void meson_crtc_irq(struct meson_drm *priv) writel_relaxed(priv->viu.osd_sc_v_ctrl0, priv->io_base + _REG(VPP_OSD_VSC_CTRL0)); - meson_canvas_config(priv->canvas, priv->canvas_id_osd1, - priv->viu.osd1_addr, priv->viu.osd1_stride, - priv->viu.osd1_height, MESON_CANVAS_WRAP_NONE, - MESON_CANVAS_BLKMODE_LINEAR, 0); + if (!priv->viu.osd1_afbcd) + meson_canvas_config(priv->canvas, priv->canvas_id_osd1, + priv->viu.osd1_addr, + priv->viu.osd1_stride, + priv->viu.osd1_height, + MESON_CANVAS_WRAP_NONE, + MESON_CANVAS_BLKMODE_LINEAR, 0); /* Enable OSD1 */ if (meson_crtc->enable_osd1) meson_crtc->enable_osd1(priv); + if (priv->viu.osd1_afbcd) + meson_crtc->vsync_forced = true; + else + meson_crtc->vsync_forced = false; + priv->viu.osd1_commit = false; } @@ -545,6 +595,15 @@ void meson_crtc_irq(struct meson_drm *priv) priv->viu.vd1_commit = false; } + if (meson_crtc->vsync_forced && priv->viu.osd1_afbcd) { + priv->afbcd.ops->reset(priv); + priv->afbcd.ops->setup(priv); + priv->afbcd.ops->enable(priv); + } + + if (meson_crtc->vsync_disabled) + return; + drm_crtc_handle_vblank(priv->crtc); spin_lock_irqsave(&priv->drm->event_lock, flags); @@ -581,10 +640,20 @@ int meson_crtc_create(struct meson_drm *priv) meson_crtc->enable_osd1 = meson_g12a_crtc_enable_osd1; meson_crtc->enable_vd1 = meson_g12a_crtc_enable_vd1; meson_crtc->viu_offset = MESON_G12A_VIU_OFFSET; + meson_crtc->enable_osd1_afbc = + meson_crtc_g12a_enable_osd1_afbc; + meson_crtc->disable_osd1_afbc = + meson_viu_g12a_disable_osd1_afbc; drm_crtc_helper_add(crtc, &meson_g12a_crtc_helper_funcs); } else { meson_crtc->enable_osd1 = meson_crtc_enable_osd1; meson_crtc->enable_vd1 = meson_crtc_enable_vd1; + if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXM)) { + meson_crtc->enable_osd1_afbc = + meson_viu_gxm_enable_osd1_afbc; + meson_crtc->disable_osd1_afbc = + meson_viu_gxm_disable_osd1_afbc; + } drm_crtc_helper_add(crtc, &meson_crtc_helper_funcs); } -- 2.22.0 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel From mboxrd@z Thu Jan 1 00:00:00 1970 From: Neil Armstrong Subject: [PATCH 7/7] drm/meson: crtc: add OSD1 plane AFBC commit Date: Thu, 10 Oct 2019 11:25:26 +0200 Message-ID: <20191010092526.10419-8-narmstrong@baylibre.com> References: <20191010092526.10419-1-narmstrong@baylibre.com> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: Received: from mail-wm1-x341.google.com (mail-wm1-x341.google.com [IPv6:2a00:1450:4864:20::341]) by gabe.freedesktop.org (Postfix) with ESMTPS id 279036EAD4 for ; Thu, 10 Oct 2019 09:25:37 +0000 (UTC) Received: by mail-wm1-x341.google.com with SMTP id p7so6122961wmp.4 for ; Thu, 10 Oct 2019 02:25:37 -0700 (PDT) In-Reply-To: <20191010092526.10419-1-narmstrong@baylibre.com> List-Unsubscribe: , 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[90.63.244.31]) by smtp.gmail.com with ESMTPSA id s10sm8373770wmf.48.2019.10.10.02.25.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 10 Oct 2019 02:25:34 -0700 (PDT) From: Neil Armstrong To: dri-devel@lists.freedesktop.org Subject: [PATCH 7/7] drm/meson: crtc: add OSD1 plane AFBC commit Date: Thu, 10 Oct 2019 11:25:26 +0200 Message-Id: <20191010092526.10419-8-narmstrong@baylibre.com> X-Mailer: git-send-email 2.22.0 In-Reply-To: <20191010092526.10419-1-narmstrong@baylibre.com> References: <20191010092526.10419-1-narmstrong@baylibre.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20191010_022536_855821_15310A1A X-CRM114-Status: GOOD ( 13.45 ) X-BeenThere: linux-amlogic@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: khilman@baylibre.com, linux-amlogic@lists.infradead.org, ayan.halder@arm.com, linux-arm-kernel@lists.infradead.org, Neil Armstrong Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-amlogic" Errors-To: linux-amlogic-bounces+linux-amlogic=archiver.kernel.org@lists.infradead.org Finally, setup the VIU registers and start the AFBC decoder at each vsync IRQ to support displaying AFBC encoded buffers on Amlogic GXM and G12A SoCs. Since the DRM core will stop the vsync IRQ after a few interrupts, we need to keep the IRQ enabled while using the AFBC decoder. Signed-off-by: Neil Armstrong --- drivers/gpu/drm/meson/meson_crtc.c | 79 ++++++++++++++++++++++++++++-- 1 file changed, 74 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/meson/meson_crtc.c b/drivers/gpu/drm/meson/meson_crtc.c index d478fa232951..d28efd0dbf11 100644 --- a/drivers/gpu/drm/meson/meson_crtc.c +++ b/drivers/gpu/drm/meson/meson_crtc.c @@ -24,6 +24,7 @@ #include "meson_venc.h" #include "meson_viu.h" #include "meson_vpp.h" +#include "meson_osd_afbcd.h" #define MESON_G12A_VIU_OFFSET 0x5ec0 @@ -35,7 +36,11 @@ struct meson_crtc { struct meson_drm *priv; void (*enable_osd1)(struct meson_drm *priv); void (*enable_vd1)(struct meson_drm *priv); + void (*enable_osd1_afbc)(struct meson_drm *priv); + void (*disable_osd1_afbc)(struct meson_drm *priv); unsigned int viu_offset; + bool vsync_forced; + bool vsync_disabled; }; #define to_meson_crtc(x) container_of(x, struct meson_crtc, base) @@ -46,6 +51,7 @@ static int meson_crtc_enable_vblank(struct drm_crtc *crtc) struct meson_crtc *meson_crtc = to_meson_crtc(crtc); struct meson_drm *priv = meson_crtc->priv; + meson_crtc->vsync_disabled = false; meson_venc_enable_vsync(priv); return 0; @@ -56,7 +62,10 @@ static void meson_crtc_disable_vblank(struct drm_crtc *crtc) struct meson_crtc *meson_crtc = to_meson_crtc(crtc); struct meson_drm *priv = meson_crtc->priv; - meson_venc_disable_vsync(priv); + if (!meson_crtc->vsync_forced) { + meson_crtc->vsync_disabled = true; + meson_venc_disable_vsync(priv); + } } static const struct drm_crtc_funcs meson_crtc_funcs = { @@ -236,6 +245,26 @@ static void meson_crtc_enable_osd1(struct meson_drm *priv) priv->io_base + _REG(VPP_MISC)); } +static void meson_crtc_g12a_enable_osd1_afbc(struct meson_drm *priv) +{ + writel_relaxed(priv->viu.osd1_blk2_cfg4, + priv->io_base + _REG(VIU_OSD1_BLK2_CFG_W4)); + + writel_bits_relaxed(OSD_MEM_LINEAR_ADDR, OSD_MEM_LINEAR_ADDR, + priv->io_base + _REG(VIU_OSD1_CTRL_STAT)); + + writel_relaxed(priv->viu.osd1_blk1_cfg4, + priv->io_base + _REG(VIU_OSD1_BLK1_CFG_W4)); + + meson_viu_g12a_enable_osd1_afbc(priv); + + writel_bits_relaxed(OSD_MEM_LINEAR_ADDR, OSD_MEM_LINEAR_ADDR, + priv->io_base + _REG(VIU_OSD1_CTRL_STAT)); + + writel_bits_relaxed(OSD_MALI_SRC_EN, OSD_MALI_SRC_EN, + priv->io_base + _REG(VIU_OSD1_BLK0_CFG_W0)); +} + static void meson_g12a_crtc_enable_osd1(struct meson_drm *priv) { writel_relaxed(priv->viu.osd_blend_din0_scope_h, @@ -293,6 +322,19 @@ void meson_crtc_irq(struct meson_drm *priv) priv->io_base + _REG(VIU_OSD1_BLK0_CFG_W3)); writel_relaxed(priv->viu.osd1_blk0_cfg[4], priv->io_base + _REG(VIU_OSD1_BLK0_CFG_W4)); + + if (priv->viu.osd1_afbcd) { + if (meson_crtc->enable_osd1_afbc) + meson_crtc->enable_osd1_afbc(priv); + } else { + if (meson_crtc->disable_osd1_afbc) + meson_crtc->disable_osd1_afbc(priv); + if (priv->afbcd.ops) { + priv->afbcd.ops->reset(priv); + priv->afbcd.ops->disable(priv); + } + } + writel_relaxed(priv->viu.osd_sc_ctrl0, priv->io_base + _REG(VPP_OSD_SC_CTRL0)); writel_relaxed(priv->viu.osd_sc_i_wh_m1, @@ -314,15 +356,23 @@ void meson_crtc_irq(struct meson_drm *priv) writel_relaxed(priv->viu.osd_sc_v_ctrl0, priv->io_base + _REG(VPP_OSD_VSC_CTRL0)); - meson_canvas_config(priv->canvas, priv->canvas_id_osd1, - priv->viu.osd1_addr, priv->viu.osd1_stride, - priv->viu.osd1_height, MESON_CANVAS_WRAP_NONE, - MESON_CANVAS_BLKMODE_LINEAR, 0); + if (!priv->viu.osd1_afbcd) + meson_canvas_config(priv->canvas, priv->canvas_id_osd1, + priv->viu.osd1_addr, + priv->viu.osd1_stride, + priv->viu.osd1_height, + MESON_CANVAS_WRAP_NONE, + MESON_CANVAS_BLKMODE_LINEAR, 0); /* Enable OSD1 */ if (meson_crtc->enable_osd1) meson_crtc->enable_osd1(priv); + if (priv->viu.osd1_afbcd) + meson_crtc->vsync_forced = true; + else + meson_crtc->vsync_forced = false; + priv->viu.osd1_commit = false; } @@ -545,6 +595,15 @@ void meson_crtc_irq(struct meson_drm *priv) priv->viu.vd1_commit = false; } + if (meson_crtc->vsync_forced && priv->viu.osd1_afbcd) { + priv->afbcd.ops->reset(priv); + priv->afbcd.ops->setup(priv); + priv->afbcd.ops->enable(priv); + } + + if (meson_crtc->vsync_disabled) + return; + drm_crtc_handle_vblank(priv->crtc); spin_lock_irqsave(&priv->drm->event_lock, flags); @@ -581,10 +640,20 @@ int meson_crtc_create(struct meson_drm *priv) meson_crtc->enable_osd1 = meson_g12a_crtc_enable_osd1; meson_crtc->enable_vd1 = meson_g12a_crtc_enable_vd1; meson_crtc->viu_offset = MESON_G12A_VIU_OFFSET; + meson_crtc->enable_osd1_afbc = + meson_crtc_g12a_enable_osd1_afbc; + meson_crtc->disable_osd1_afbc = + meson_viu_g12a_disable_osd1_afbc; drm_crtc_helper_add(crtc, &meson_g12a_crtc_helper_funcs); } else { meson_crtc->enable_osd1 = meson_crtc_enable_osd1; meson_crtc->enable_vd1 = meson_crtc_enable_vd1; + if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXM)) { + meson_crtc->enable_osd1_afbc = + meson_viu_gxm_enable_osd1_afbc; + meson_crtc->disable_osd1_afbc = + meson_viu_gxm_disable_osd1_afbc; + } drm_crtc_helper_add(crtc, &meson_crtc_helper_funcs); } -- 2.22.0 _______________________________________________ linux-amlogic mailing list linux-amlogic@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-amlogic