From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.2 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED,USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 752F9ECE58C for ; Fri, 11 Oct 2019 14:22:06 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 5818D206A1 for ; Fri, 11 Oct 2019 14:22:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728570AbfJKOWF (ORCPT ); Fri, 11 Oct 2019 10:22:05 -0400 Received: from foss.arm.com ([217.140.110.172]:33928 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728068AbfJKOWE (ORCPT ); Fri, 11 Oct 2019 10:22:04 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 3816F142F; Fri, 11 Oct 2019 07:22:03 -0700 (PDT) Received: from lakrids.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.121.207.14]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 51D463F68E; Fri, 11 Oct 2019 07:22:00 -0700 (PDT) Date: Fri, 11 Oct 2019 15:21:58 +0100 From: Mark Rutland To: Dave Martin Cc: linux-kernel@vger.kernel.org, Andrew Jones , Arnd Bergmann , Catalin Marinas , Eugene Syromiatnikov , Florian Weimer , "H.J. Lu" , Jann Horn , Kees Cook , Kristina =?utf-8?Q?Mart=C5=A1enko?= , Mark Brown , Paul Elliott , Peter Zijlstra , Richard Henderson , Sudakshina Das , Szabolcs Nagy , Thomas Gleixner , Will Deacon , Yu-cheng Yu , Amit Kachhap , Vincenzo Frascino , linux-arch@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: Re: [PATCH v2 11/12] arm64: BTI: Reset BTYPE when skipping emulated instructions Message-ID: <20191011142157.GC33537@lakrids.cambridge.arm.com> References: <1570733080-21015-1-git-send-email-Dave.Martin@arm.com> <1570733080-21015-12-git-send-email-Dave.Martin@arm.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1570733080-21015-12-git-send-email-Dave.Martin@arm.com> User-Agent: Mutt/1.11.1+11 (2f07cb52) (2018-12-01) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, Oct 10, 2019 at 07:44:39PM +0100, Dave Martin wrote: > Since normal execution of any non-branch instruction resets the > PSTATE BTYPE field to 0, so do the same thing when emulating a > trapped instruction. > > Branches don't trap directly, so we should never need to assign a > non-zero value to BTYPE here. > > Signed-off-by: Dave Martin > --- > arch/arm64/kernel/traps.c | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/arch/arm64/kernel/traps.c b/arch/arm64/kernel/traps.c > index 3af2768..4d8ce50 100644 > --- a/arch/arm64/kernel/traps.c > +++ b/arch/arm64/kernel/traps.c > @@ -331,6 +331,8 @@ void arm64_skip_faulting_instruction(struct pt_regs *regs, unsigned long size) > > if (regs->pstate & PSR_MODE32_BIT) > advance_itstate(regs); > + else > + regs->pstate &= ~(u64)PSR_BTYPE_MASK; This looks good to me, with one nit below. We don't (currently) need the u64 cast here, and it's inconsistent with what we do elsewhere. If the upper 32-bit of pstate get allocated, we'll need to fix up all the other masking we do: [mark@lakrids:~/src/linux]% git grep 'pstate &= ~' arch/arm64/kernel/armv8_deprecated.c: regs->pstate &= ~PSR_AA32_E_BIT; arch/arm64/kernel/cpufeature.c: regs->pstate &= ~PSR_SSBS_BIT; arch/arm64/kernel/debug-monitors.c: regs->pstate &= ~DBG_SPSR_SS; arch/arm64/kernel/insn.c: pstate &= ~(pstate >> 1); /* PSR_C_BIT &= ~PSR_Z_BIT */ arch/arm64/kernel/insn.c: pstate &= ~(pstate >> 1); /* PSR_C_BIT &= ~PSR_Z_BIT */ arch/arm64/kernel/probes/kprobes.c: regs->pstate &= ~PSR_D_BIT; arch/arm64/kernel/probes/kprobes.c: regs->pstate &= ~DAIF_MASK; arch/arm64/kernel/ptrace.c: regs->pstate &= ~SPSR_EL1_AARCH32_RES0_BITS; arch/arm64/kernel/ptrace.c: regs->pstate &= ~PSR_AA32_E_BIT; arch/arm64/kernel/ptrace.c: regs->pstate &= ~SPSR_EL1_AARCH64_RES0_BITS; arch/arm64/kernel/ptrace.c: regs->pstate &= ~DBG_SPSR_SS; arch/arm64/kernel/ssbd.c: task_pt_regs(task)->pstate &= ~val; arch/arm64/kernel/traps.c: regs->pstate &= ~PSR_AA32_IT_MASK; ... and at that point I'd suggest we should just ensure the bit definitions are all defined as unsigned long in the first place since adding casts to each use is error-prone. Thanks, Mark. From mboxrd@z Thu Jan 1 00:00:00 1970 From: Mark Rutland Subject: Re: [PATCH v2 11/12] arm64: BTI: Reset BTYPE when skipping emulated instructions Date: Fri, 11 Oct 2019 15:21:58 +0100 Message-ID: <20191011142157.GC33537@lakrids.cambridge.arm.com> References: <1570733080-21015-1-git-send-email-Dave.Martin@arm.com> <1570733080-21015-12-git-send-email-Dave.Martin@arm.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Return-path: Content-Disposition: inline In-Reply-To: <1570733080-21015-12-git-send-email-Dave.Martin@arm.com> Sender: linux-kernel-owner@vger.kernel.org To: Dave Martin Cc: linux-kernel@vger.kernel.org, Andrew Jones , Arnd Bergmann , Catalin Marinas , Eugene Syromiatnikov , Florian Weimer , "H.J. Lu" , Jann Horn , Kees Cook , Kristina =?utf-8?Q?Mart=C5=A1enko?= , Mark Brown , Paul Elliott , Peter Zijlstra , Richard Henderson , Sudakshina Das , Szabolcs Nagy , Thomas Gleixner , Will Deacon , Yu-cheng Yu , Amit Kachhap List-Id: linux-arch.vger.kernel.org On Thu, Oct 10, 2019 at 07:44:39PM +0100, Dave Martin wrote: > Since normal execution of any non-branch instruction resets the > PSTATE BTYPE field to 0, so do the same thing when emulating a > trapped instruction. > > Branches don't trap directly, so we should never need to assign a > non-zero value to BTYPE here. > > Signed-off-by: Dave Martin > --- > arch/arm64/kernel/traps.c | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/arch/arm64/kernel/traps.c b/arch/arm64/kernel/traps.c > index 3af2768..4d8ce50 100644 > --- a/arch/arm64/kernel/traps.c > +++ b/arch/arm64/kernel/traps.c > @@ -331,6 +331,8 @@ void arm64_skip_faulting_instruction(struct pt_regs *regs, unsigned long size) > > if (regs->pstate & PSR_MODE32_BIT) > advance_itstate(regs); > + else > + regs->pstate &= ~(u64)PSR_BTYPE_MASK; This looks good to me, with one nit below. We don't (currently) need the u64 cast here, and it's inconsistent with what we do elsewhere. If the upper 32-bit of pstate get allocated, we'll need to fix up all the other masking we do: [mark@lakrids:~/src/linux]% git grep 'pstate &= ~' arch/arm64/kernel/armv8_deprecated.c: regs->pstate &= ~PSR_AA32_E_BIT; arch/arm64/kernel/cpufeature.c: regs->pstate &= ~PSR_SSBS_BIT; arch/arm64/kernel/debug-monitors.c: regs->pstate &= ~DBG_SPSR_SS; arch/arm64/kernel/insn.c: pstate &= ~(pstate >> 1); /* PSR_C_BIT &= ~PSR_Z_BIT */ arch/arm64/kernel/insn.c: pstate &= ~(pstate >> 1); /* PSR_C_BIT &= ~PSR_Z_BIT */ arch/arm64/kernel/probes/kprobes.c: regs->pstate &= ~PSR_D_BIT; arch/arm64/kernel/probes/kprobes.c: regs->pstate &= ~DAIF_MASK; arch/arm64/kernel/ptrace.c: regs->pstate &= ~SPSR_EL1_AARCH32_RES0_BITS; arch/arm64/kernel/ptrace.c: regs->pstate &= ~PSR_AA32_E_BIT; arch/arm64/kernel/ptrace.c: regs->pstate &= ~SPSR_EL1_AARCH64_RES0_BITS; arch/arm64/kernel/ptrace.c: regs->pstate &= ~DBG_SPSR_SS; arch/arm64/kernel/ssbd.c: task_pt_regs(task)->pstate &= ~val; arch/arm64/kernel/traps.c: regs->pstate &= ~PSR_AA32_IT_MASK; ... and at that point I'd suggest we should just ensure the bit definitions are all defined as unsigned long in the first place since adding casts to each use is error-prone. Thanks, Mark. From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.3 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_SANE_1 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3BE4BC47404 for ; Fri, 11 Oct 2019 14:22:11 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 08CE8206A1 for ; Fri, 11 Oct 2019 14:22:11 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="tIh7sPPn" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 08CE8206A1 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=6tWtiRP2CXtwTz0NaknC5OsYrq+rvwKYfgBkHPbJyZA=; b=tIh7sPPnxhr/Ve zsfgfDdPuabfXlZuiMQw568roTAs+bHYPIgfWMIhm9VTK5cAEOoPjPY/ucZBummyhqZV8bv1WKdtJ Ic2xvaV4urRPwaG7eUFtgUfoJ3MfaTZ40+nieR/z/dVTHqq2KAWClkEFBbPbNVmgpDB+p868yll4E /x/g5BahSmuTf8YSOGEtU5O+3OoglDbspHPPNd2HGFGIBF6GuB5jlR2giASk7ehBic1y/nfbUkBwX nj9/PIpdS7Fyo2zTsg0Au3dcfowFBC9rFOXAjEKhlw/cnAbxZPIeDk1SCaea+/AYaN5+1fhHGYwW+ QdvaSddZ5eTFqdAcpjQQ==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1iIvny-000546-8s; Fri, 11 Oct 2019 14:22:06 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1iIvnv-00053N-PZ for linux-arm-kernel@lists.infradead.org; Fri, 11 Oct 2019 14:22:05 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 3816F142F; Fri, 11 Oct 2019 07:22:03 -0700 (PDT) Received: from lakrids.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.121.207.14]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 51D463F68E; Fri, 11 Oct 2019 07:22:00 -0700 (PDT) Date: Fri, 11 Oct 2019 15:21:58 +0100 From: Mark Rutland To: Dave Martin Subject: Re: [PATCH v2 11/12] arm64: BTI: Reset BTYPE when skipping emulated instructions Message-ID: <20191011142157.GC33537@lakrids.cambridge.arm.com> References: <1570733080-21015-1-git-send-email-Dave.Martin@arm.com> <1570733080-21015-12-git-send-email-Dave.Martin@arm.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <1570733080-21015-12-git-send-email-Dave.Martin@arm.com> User-Agent: Mutt/1.11.1+11 (2f07cb52) (2018-12-01) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20191011_072203_913650_0591E166 X-CRM114-Status: GOOD ( 15.88 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Paul Elliott , Peter Zijlstra , Catalin Marinas , Will Deacon , Yu-cheng Yu , Amit Kachhap , Vincenzo Frascino , linux-arch@vger.kernel.org, Eugene Syromiatnikov , Szabolcs Nagy , "H.J. Lu" , Andrew Jones , Kees Cook , Arnd Bergmann , Jann Horn , Richard Henderson , Kristina =?utf-8?Q?Mart=C5=A1enko?= , Mark Brown , Thomas Gleixner , linux-arm-kernel@lists.infradead.org, Florian Weimer , linux-kernel@vger.kernel.org, Sudakshina Das Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Thu, Oct 10, 2019 at 07:44:39PM +0100, Dave Martin wrote: > Since normal execution of any non-branch instruction resets the > PSTATE BTYPE field to 0, so do the same thing when emulating a > trapped instruction. > > Branches don't trap directly, so we should never need to assign a > non-zero value to BTYPE here. > > Signed-off-by: Dave Martin > --- > arch/arm64/kernel/traps.c | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/arch/arm64/kernel/traps.c b/arch/arm64/kernel/traps.c > index 3af2768..4d8ce50 100644 > --- a/arch/arm64/kernel/traps.c > +++ b/arch/arm64/kernel/traps.c > @@ -331,6 +331,8 @@ void arm64_skip_faulting_instruction(struct pt_regs *regs, unsigned long size) > > if (regs->pstate & PSR_MODE32_BIT) > advance_itstate(regs); > + else > + regs->pstate &= ~(u64)PSR_BTYPE_MASK; This looks good to me, with one nit below. We don't (currently) need the u64 cast here, and it's inconsistent with what we do elsewhere. If the upper 32-bit of pstate get allocated, we'll need to fix up all the other masking we do: [mark@lakrids:~/src/linux]% git grep 'pstate &= ~' arch/arm64/kernel/armv8_deprecated.c: regs->pstate &= ~PSR_AA32_E_BIT; arch/arm64/kernel/cpufeature.c: regs->pstate &= ~PSR_SSBS_BIT; arch/arm64/kernel/debug-monitors.c: regs->pstate &= ~DBG_SPSR_SS; arch/arm64/kernel/insn.c: pstate &= ~(pstate >> 1); /* PSR_C_BIT &= ~PSR_Z_BIT */ arch/arm64/kernel/insn.c: pstate &= ~(pstate >> 1); /* PSR_C_BIT &= ~PSR_Z_BIT */ arch/arm64/kernel/probes/kprobes.c: regs->pstate &= ~PSR_D_BIT; arch/arm64/kernel/probes/kprobes.c: regs->pstate &= ~DAIF_MASK; arch/arm64/kernel/ptrace.c: regs->pstate &= ~SPSR_EL1_AARCH32_RES0_BITS; arch/arm64/kernel/ptrace.c: regs->pstate &= ~PSR_AA32_E_BIT; arch/arm64/kernel/ptrace.c: regs->pstate &= ~SPSR_EL1_AARCH64_RES0_BITS; arch/arm64/kernel/ptrace.c: regs->pstate &= ~DBG_SPSR_SS; arch/arm64/kernel/ssbd.c: task_pt_regs(task)->pstate &= ~val; arch/arm64/kernel/traps.c: regs->pstate &= ~PSR_AA32_IT_MASK; ... and at that point I'd suggest we should just ensure the bit definitions are all defined as unsigned long in the first place since adding casts to each use is error-prone. Thanks, Mark. _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel