From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.2 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED,USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1B575ECE58C for ; Fri, 11 Oct 2019 14:51:57 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id EEC0D2089F for ; Fri, 11 Oct 2019 14:51:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727554AbfJKOvz (ORCPT ); Fri, 11 Oct 2019 10:51:55 -0400 Received: from foss.arm.com ([217.140.110.172]:34842 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726174AbfJKOvz (ORCPT ); Fri, 11 Oct 2019 10:51:55 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 614DB142F; Fri, 11 Oct 2019 07:51:54 -0700 (PDT) Received: from arm.com (usa-sjc-imap-foss1.foss.arm.com [10.121.207.14]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 607CF3F68E; Fri, 11 Oct 2019 07:51:51 -0700 (PDT) Date: Fri, 11 Oct 2019 15:51:49 +0100 From: Dave Martin To: Alex =?iso-8859-1?Q?Benn=E9e?= Cc: Paul Elliott , Peter Zijlstra , Catalin Marinas , Will Deacon , Yu-cheng Yu , Amit Kachhap , Vincenzo Frascino , linux-arch@vger.kernel.org, Eugene Syromiatnikov , Szabolcs Nagy , "H.J. Lu" , Andrew Jones , Kees Cook , Arnd Bergmann , Jann Horn , Richard Henderson , Kristina =?utf-8?Q?Mart=C5=A1enko?= , Mark Brown , Thomas Gleixner , linux-arm-kernel@lists.infradead.org, Florian Weimer , linux-kernel@vger.kernel.org, Sudakshina Das , Suzuki Poulose Subject: Re: [PATCH v2 04/12] arm64: docs: cpu-feature-registers: Document ID_AA64PFR1_EL1 Message-ID: <20191011145148.GK27757@arm.com> References: <1570733080-21015-1-git-send-email-Dave.Martin@arm.com> <1570733080-21015-5-git-send-email-Dave.Martin@arm.com> <87zhi7l8qz.fsf@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <87zhi7l8qz.fsf@linaro.org> User-Agent: Mutt/1.5.23 (2014-03-12) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri, Oct 11, 2019 at 02:19:48PM +0100, Alex Bennée wrote: > > Dave Martin writes: > > > Commit d71be2b6c0e1 ("arm64: cpufeature: Detect SSBS and advertise > > to userspace") exposes ID_AA64PFR1_EL1 to userspace, but didn't > > update the documentation to match. > > > > Add it. > > > > Signed-off-by: Dave Martin > > > > --- > > > > Note to maintainers: > > > > * This patch has been racing with various other attempts to fix > > the same documentation in the meantime. > > > > Since this patch only fixes the documenting for pre-existing > > features, it can safely be dropped if appropriate. > > > > The _new_ documentation relating to BTI feature reporting > > is in a subsequent patch, and needs to be retained. > > --- > > Documentation/arm64/cpu-feature-registers.rst | 15 +++++++++++---- > > 1 file changed, 11 insertions(+), 4 deletions(-) > > > > diff --git a/Documentation/arm64/cpu-feature-registers.rst b/Documentation/arm64/cpu-feature-registers.rst > > index 2955287..b86828f 100644 > > --- a/Documentation/arm64/cpu-feature-registers.rst > > +++ b/Documentation/arm64/cpu-feature-registers.rst > > @@ -168,8 +168,15 @@ infrastructure: > > +------------------------------+---------+---------+ > > > > > > - 3) MIDR_EL1 - Main ID Register > > + 3) ID_AA64PFR1_EL1 - Processor Feature Register 1 > > + +------------------------------+---------+---------+ > > + | Name | bits | visible | > > + +------------------------------+---------+---------+ > > + | SSBS | [7-4] | y | > > + +------------------------------+---------+---------+ > > + > > > > + 4) MIDR_EL1 - Main ID Register > > +------------------------------+---------+---------+ > > | Name | bits | visible | > > +------------------------------+---------+---------+ > > @@ -188,7 +195,7 @@ infrastructure: > > as available on the CPU where it is fetched and is not a system > > wide safe value. > > > > - 4) ID_AA64ISAR1_EL1 - Instruction set attribute register 1 > > + 5) ID_AA64ISAR1_EL1 - Instruction set attribute register 1 > > If I'm not mistaken .rst has support for auto-enumeration if the # > character is used. That might reduce the pain of re-numbering in future. Ack, though it would be good to go one better and generate this document from the cpufeature.c tables (or from some common source). The numbers are relatively easy to maintain -- remembering to update the document at all seems the bigger maintenance headache right now. I think this particular patch is superseded by similar fixes from other people, just not in torvalds/master yet. [...] Cheers ---Dave From mboxrd@z Thu Jan 1 00:00:00 1970 From: Dave Martin Subject: Re: [PATCH v2 04/12] arm64: docs: cpu-feature-registers: Document ID_AA64PFR1_EL1 Date: Fri, 11 Oct 2019 15:51:49 +0100 Message-ID: <20191011145148.GK27757@arm.com> References: <1570733080-21015-1-git-send-email-Dave.Martin@arm.com> <1570733080-21015-5-git-send-email-Dave.Martin@arm.com> <87zhi7l8qz.fsf@linaro.org> Mime-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Transfer-Encoding: 8bit Return-path: Content-Disposition: inline In-Reply-To: <87zhi7l8qz.fsf@linaro.org> Sender: linux-kernel-owner@vger.kernel.org To: Alex =?iso-8859-1?Q?Benn=E9e?= Cc: Paul Elliott , Peter Zijlstra , Catalin Marinas , Will Deacon , Yu-cheng Yu , Amit Kachhap , Vincenzo Frascino , linux-arch@vger.kernel.org, Eugene Syromiatnikov , Szabolcs Nagy , "H.J. Lu" , Andrew Jones , Kees Cook , Arnd Bergmann , Jann Horn , Richard Henderson , Kristina =?utf-8?Q?Mart=C5=A1enko?= , Mark Brown , Thomas Gleixner , linux-arm-kernel@lists.infradead.or List-Id: linux-arch.vger.kernel.org On Fri, Oct 11, 2019 at 02:19:48PM +0100, Alex Bennée wrote: > > Dave Martin writes: > > > Commit d71be2b6c0e1 ("arm64: cpufeature: Detect SSBS and advertise > > to userspace") exposes ID_AA64PFR1_EL1 to userspace, but didn't > > update the documentation to match. > > > > Add it. > > > > Signed-off-by: Dave Martin > > > > --- > > > > Note to maintainers: > > > > * This patch has been racing with various other attempts to fix > > the same documentation in the meantime. > > > > Since this patch only fixes the documenting for pre-existing > > features, it can safely be dropped if appropriate. > > > > The _new_ documentation relating to BTI feature reporting > > is in a subsequent patch, and needs to be retained. > > --- > > Documentation/arm64/cpu-feature-registers.rst | 15 +++++++++++---- > > 1 file changed, 11 insertions(+), 4 deletions(-) > > > > diff --git a/Documentation/arm64/cpu-feature-registers.rst b/Documentation/arm64/cpu-feature-registers.rst > > index 2955287..b86828f 100644 > > --- a/Documentation/arm64/cpu-feature-registers.rst > > +++ b/Documentation/arm64/cpu-feature-registers.rst > > @@ -168,8 +168,15 @@ infrastructure: > > +------------------------------+---------+---------+ > > > > > > - 3) MIDR_EL1 - Main ID Register > > + 3) ID_AA64PFR1_EL1 - Processor Feature Register 1 > > + +------------------------------+---------+---------+ > > + | Name | bits | visible | > > + +------------------------------+---------+---------+ > > + | SSBS | [7-4] | y | > > + +------------------------------+---------+---------+ > > + > > > > + 4) MIDR_EL1 - Main ID Register > > +------------------------------+---------+---------+ > > | Name | bits | visible | > > +------------------------------+---------+---------+ > > @@ -188,7 +195,7 @@ infrastructure: > > as available on the CPU where it is fetched and is not a system > > wide safe value. > > > > - 4) ID_AA64ISAR1_EL1 - Instruction set attribute register 1 > > + 5) ID_AA64ISAR1_EL1 - Instruction set attribute register 1 > > If I'm not mistaken .rst has support for auto-enumeration if the # > character is used. That might reduce the pain of re-numbering in future. Ack, though it would be good to go one better and generate this document from the cpufeature.c tables (or from some common source). The numbers are relatively easy to maintain -- remembering to update the document at all seems the bigger maintenance headache right now. I think this particular patch is superseded by similar fixes from other people, just not in torvalds/master yet. [...] Cheers ---Dave From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.3 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A934CC47404 for ; Fri, 11 Oct 2019 14:52:03 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 7C9F8214E0 for ; Fri, 11 Oct 2019 14:52:03 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="DUHs8ZUk" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 7C9F8214E0 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=V6lTJXB/vALJE86WNGMviFxRg0Thi8lj51yqbPttrwM=; b=DUHs8ZUkJdITya mdmY4Ng/a6QKUWGrS6tvmkeut1sPlJPR6xC5cpDlvT5/GYVSQLyHP2/acL6nv4PDpdTobf4Nr0M+7 +/El8sBgcQHQC5mboifKOu+H3hHlXadPnYQeBG1bLuz5KugJ/pd8l+KH8OaU2vhDX8juNQhojlWy1 CY3kwJhgha0CTDKnp31OHDNPJnC9TD7ggl4mW3Zr43/PHpwbp433Ad0an0IdAOULev4SpavXtTxKE 15dJEiAh+IYM3dB7wSwFf7YhCKVhtj9MevXZhX/xSCWTGn1pyj4JyzkAUtIhkG9cmXYp+ZrhLSs0t 7708RcX45upny7sovUIw==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1iIwGs-0003Dt-Fe; Fri, 11 Oct 2019 14:51:58 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1iIwGq-0003Cq-2W for linux-arm-kernel@lists.infradead.org; Fri, 11 Oct 2019 14:51:57 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 614DB142F; Fri, 11 Oct 2019 07:51:54 -0700 (PDT) Received: from arm.com (usa-sjc-imap-foss1.foss.arm.com [10.121.207.14]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 607CF3F68E; Fri, 11 Oct 2019 07:51:51 -0700 (PDT) Date: Fri, 11 Oct 2019 15:51:49 +0100 From: Dave Martin To: Alex =?iso-8859-1?Q?Benn=E9e?= Subject: Re: [PATCH v2 04/12] arm64: docs: cpu-feature-registers: Document ID_AA64PFR1_EL1 Message-ID: <20191011145148.GK27757@arm.com> References: <1570733080-21015-1-git-send-email-Dave.Martin@arm.com> <1570733080-21015-5-git-send-email-Dave.Martin@arm.com> <87zhi7l8qz.fsf@linaro.org> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <87zhi7l8qz.fsf@linaro.org> User-Agent: Mutt/1.5.23 (2014-03-12) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20191011_075156_204780_45C5ADBE X-CRM114-Status: GOOD ( 22.93 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Paul Elliott , Peter Zijlstra , Catalin Marinas , Will Deacon , Andrew Jones , Amit Kachhap , Vincenzo Frascino , linux-arch@vger.kernel.org, Suzuki Poulose , Eugene Syromiatnikov , Szabolcs Nagy , "H.J. Lu" , Yu-cheng Yu , Kees Cook , Arnd Bergmann , Jann Horn , Richard Henderson , Kristina =?utf-8?Q?Mart=C5=A1enko?= , Mark Brown , Thomas Gleixner , linux-arm-kernel@lists.infradead.org, Florian Weimer , linux-kernel@vger.kernel.org, Sudakshina Das Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Fri, Oct 11, 2019 at 02:19:48PM +0100, Alex Benn=E9e wrote: > = > Dave Martin writes: > = > > Commit d71be2b6c0e1 ("arm64: cpufeature: Detect SSBS and advertise > > to userspace") exposes ID_AA64PFR1_EL1 to userspace, but didn't > > update the documentation to match. > > > > Add it. > > > > Signed-off-by: Dave Martin > > > > --- > > > > Note to maintainers: > > > > * This patch has been racing with various other attempts to fix > > the same documentation in the meantime. > > > > Since this patch only fixes the documenting for pre-existing > > features, it can safely be dropped if appropriate. > > > > The _new_ documentation relating to BTI feature reporting > > is in a subsequent patch, and needs to be retained. > > --- > > Documentation/arm64/cpu-feature-registers.rst | 15 +++++++++++---- > > 1 file changed, 11 insertions(+), 4 deletions(-) > > > > diff --git a/Documentation/arm64/cpu-feature-registers.rst b/Documentat= ion/arm64/cpu-feature-registers.rst > > index 2955287..b86828f 100644 > > --- a/Documentation/arm64/cpu-feature-registers.rst > > +++ b/Documentation/arm64/cpu-feature-registers.rst > > @@ -168,8 +168,15 @@ infrastructure: > > +------------------------------+---------+---------+ > > > > > > - 3) MIDR_EL1 - Main ID Register > > + 3) ID_AA64PFR1_EL1 - Processor Feature Register 1 > > + +------------------------------+---------+---------+ > > + | Name | bits | visible | > > + +------------------------------+---------+---------+ > > + | SSBS | [7-4] | y | > > + +------------------------------+---------+---------+ > > + > > > > + 4) MIDR_EL1 - Main ID Register > > +------------------------------+---------+---------+ > > | Name | bits | visible | > > +------------------------------+---------+---------+ > > @@ -188,7 +195,7 @@ infrastructure: > > as available on the CPU where it is fetched and is not a system > > wide safe value. > > > > - 4) ID_AA64ISAR1_EL1 - Instruction set attribute register 1 > > + 5) ID_AA64ISAR1_EL1 - Instruction set attribute register 1 > = > If I'm not mistaken .rst has support for auto-enumeration if the # > character is used. That might reduce the pain of re-numbering in future. Ack, though it would be good to go one better and generate this document from the cpufeature.c tables (or from some common source). The numbers are relatively easy to maintain -- remembering to update the document at all seems the bigger maintenance headache right now. I think this particular patch is superseded by similar fixes from other people, just not in torvalds/master yet. [...] Cheers ---Dave _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel