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[67.216.151.25]) by smtp.gmail.com with ESMTPSA id d17sm2473139ywb.95.2019.10.11.08.55.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 11 Oct 2019 08:55:47 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v6 00/20] target/arm: Reduce overhead of cpu_get_tb_cpu_state Date: Fri, 11 Oct 2019 11:55:26 -0400 Message-Id: <20191011155546.14342-1-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::c41 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: laurent.desnogues@gmail.com, peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Changes since v5: * Fix the debug assertion ifdef in the final patch. * Add more calls to arm_rebuild_hflags: CPSR and M-profile These become two new patches, 18 & 19. * Update some comments per review. (Alex) Changes since v4: * Split patch 1 into 15 smaller patches. * Cache the new DEBUG_TARGET_EL field. * Split out m-profile hflags separately from a-profile 32-bit. * Move around non-cached tb flags as well, avoiding repetitive checks for m-profile or other mutually exclusive conditions. I haven't officially re-run the performance test quoted in the last patch, but I have eyeballed "perf top", and have dug into the compiled code a bit, which resulted in a few of the new cleanup patches (e.g. cs_base, arm_mmu_idx_el, and arm_cpu_data_is_big_endian). Changes since v3: * Rebase. * Do not cache XSCALE_CPAR now that it overlaps VECSTRIDE. * Leave the new v7m bits as uncached. I haven't figured out all of the ways fpccr is modified. Changes since v2: * Do not cache VECLEN, VECSTRIDE, VFPEN. These variables come from VFP_FPSCR and VFP_FPEXC, not from system control registers. * Move HANDLER and STACKCHECK to rebuild_hflags_a32, instead of building them in rebuild_hflags_common. Changes since v1: * Apparently I had started a last-minute API change, and failed to covert all of the users, and also failed to re-test afterward. * Retain assertions for --enable-debug-tcg. Richard Henderson (20): target/arm: Split out rebuild_hflags_common target/arm: Split out rebuild_hflags_a64 target/arm: Split out rebuild_hflags_common_32 target/arm: Split arm_cpu_data_is_big_endian target/arm: Split out rebuild_hflags_m32 target/arm: Reduce tests vs M-profile in cpu_get_tb_cpu_state target/arm: Split out rebuild_hflags_a32 target/arm: Split out rebuild_hflags_aprofile target/arm: Hoist XSCALE_CPAR, VECLEN, VECSTRIDE in cpu_get_tb_cpu_state target/arm: Simplify set of PSTATE_SS in cpu_get_tb_cpu_state target/arm: Hoist computation of TBFLAG_A32.VFPEN target/arm: Add arm_rebuild_hflags target/arm: Split out arm_mmu_idx_el target/arm: Hoist store to cs_base in cpu_get_tb_cpu_state target/arm: Add HELPER(rebuild_hflags_{a32,a64,m32}) target/arm: Rebuild hflags at EL changes target/arm: Rebuild hflags at MSR writes target/arm: Rebuild hflags at CPSR writes target/arm: Rebuild hflags for M-profile. target/arm: Rely on hflags correct in cpu_get_tb_cpu_state target/arm/cpu.h | 84 +++++--- target/arm/helper.h | 4 + target/arm/internals.h | 9 + linux-user/syscall.c | 1 + target/arm/cpu.c | 1 + target/arm/helper-a64.c | 3 + target/arm/helper.c | 383 ++++++++++++++++++++++++------------- target/arm/m_helper.c | 6 + target/arm/machine.c | 1 + target/arm/op_helper.c | 4 + target/arm/translate-a64.c | 13 +- target/arm/translate.c | 28 ++- 12 files changed, 363 insertions(+), 174 deletions(-) -- 2.17.1