From mboxrd@z Thu Jan 1 00:00:00 1970 From: Laurentiu Tudor Date: Thu, 17 Oct 2019 09:22:00 +0000 Subject: [U-Boot] [PATCH 4/6] armv8: fsl-layerscape: add missing SATA3 and SATA4 base addresses In-Reply-To: <20191017092144.19525-1-laurentiu.tudor@nxp.com> References: <20191017092144.19525-1-laurentiu.tudor@nxp.com> Message-ID: <20191017092144.19525-4-laurentiu.tudor@nxp.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de From: Laurentiu Tudor There are chips that have 4 sata controllers. Add missing base addresses for SATA3 and SATA4. Signed-off-by: Laurentiu Tudor --- arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h index 4f050470dd..0e4bf331fd 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h @@ -87,6 +87,8 @@ /* SATA */ #define AHCI_BASE_ADDR1 (CONFIG_SYS_IMMR + 0x02200000) #define AHCI_BASE_ADDR2 (CONFIG_SYS_IMMR + 0x02210000) +#define AHCI_BASE_ADDR3 (CONFIG_SYS_IMMR + 0x02220000) +#define AHCI_BASE_ADDR4 (CONFIG_SYS_IMMR + 0x02230000) /* QDMA */ #define QDMA_BASE_ADDR (CONFIG_SYS_IMMR + 0x07380000) -- 2.17.1