From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.7 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D3362ECE58E for ; Thu, 17 Oct 2019 15:29:57 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id A2C4620872 for ; Thu, 17 Oct 2019 15:29:57 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org A2C4620872 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=kaod.org Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Received: from localhost ([::1]:51046 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iL7it-0004Bb-Q0 for qemu-devel@archiver.kernel.org; Thu, 17 Oct 2019 11:29:55 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:49768) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iL6zL-0004Fh-O5 for qemu-devel@nongnu.org; Thu, 17 Oct 2019 10:42:53 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iL6zK-00069G-3v for qemu-devel@nongnu.org; Thu, 17 Oct 2019 10:42:51 -0400 Received: from mx0b-001b2d01.pphosted.com ([148.163.158.5]:9208 helo=mx0a-001b2d01.pphosted.com) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1iL6zJ-00068i-V9 for qemu-devel@nongnu.org; Thu, 17 Oct 2019 10:42:50 -0400 Received: from pps.filterd (m0098421.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id x9HEgVS4074805 for ; Thu, 17 Oct 2019 10:42:48 -0400 Received: from e06smtp05.uk.ibm.com (e06smtp05.uk.ibm.com [195.75.94.101]) by mx0a-001b2d01.pphosted.com with ESMTP id 2vpsrk1tcg-1 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=NOT) for ; Thu, 17 Oct 2019 10:42:47 -0400 Received: from localhost by e06smtp05.uk.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; (version=TLSv1/SSLv3 cipher=AES256-GCM-SHA384 bits=256/256) Thu, 17 Oct 2019 15:42:44 +0100 Received: from d06av24.portsmouth.uk.ibm.com (mk.ibm.com [9.149.105.60]) by b06cxnps4075.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id x9HEghX955181476 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Thu, 17 Oct 2019 14:42:43 GMT Received: from d06av24.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 7A2014204C; Thu, 17 Oct 2019 14:42:43 +0000 (GMT) Received: from d06av24.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 5B11F42042; Thu, 17 Oct 2019 14:42:43 +0000 (GMT) Received: from smtp.tls.ibm.com (unknown [9.101.4.1]) by d06av24.portsmouth.uk.ibm.com (Postfix) with ESMTP; Thu, 17 Oct 2019 14:42:43 +0000 (GMT) Received: from yukon.tls.ibm.com (yukon.tls.ibm.com [9.101.4.25]) by smtp.tls.ibm.com (Postfix) with ESMTP id 19A792201F3; Thu, 17 Oct 2019 16:42:43 +0200 (CEST) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: David Gibson Subject: [PATCH 2/2] spapr/xive: Set the OS CAM line at reset Date: Thu, 17 Oct 2019 16:42:41 +0200 X-Mailer: git-send-email 2.21.0 In-Reply-To: <20191017144241.12522-1-clg@kaod.org> References: <20191017144241.12522-1-clg@kaod.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 X-TM-AS-GCONF: 00 x-cbid: 19101714-0020-0000-0000-00000379FCA1 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 19101714-0021-0000-0000-000021D02759 Message-Id: <20191017144241.12522-3-clg@kaod.org> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2019-10-17_05:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=0 phishscore=0 bulkscore=0 spamscore=0 clxscore=1034 lowpriorityscore=0 mlxscore=0 impostorscore=0 mlxlogscore=999 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1908290000 definitions=main-1910170133 Content-Transfer-Encoding: quoted-printable X-MIME-Autoconverted: from 8bit to quoted-printable by mx0a-001b2d01.pphosted.com id x9HEgVS4074805 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [generic] [fuzzy] X-Received-From: 148.163.158.5 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , qemu-ppc@nongnu.org, qemu-devel@nongnu.org, Greg Kurz Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" When a Virtual Processor is scheduled to run on a HW thread, the hypervisor pushes its identifier in the OS CAM line. When running in TCG or kernel_irqchip=3Doff, QEMU needs to emulate the same behavior. Introduce a 'os-cam' property which will be used to set the OS CAM line at reset and remove the spapr_xive_set_tctx_os_cam() calls which are done when the XIVE interrupt controller are activated. This change also has the benefit to remove the use of CPU_FOREACH() which can be unsafe. Signed-off-by: C=C3=A9dric Le Goater --- include/hw/ppc/spapr_xive.h | 1 - include/hw/ppc/xive.h | 4 +++- hw/intc/spapr_xive.c | 31 +++++-------------------------- hw/intc/xive.c | 22 +++++++++++++++++++++- hw/ppc/pnv.c | 3 ++- 5 files changed, 31 insertions(+), 30 deletions(-) diff --git a/include/hw/ppc/spapr_xive.h b/include/hw/ppc/spapr_xive.h index d84bd5c229f0..742b7e834f2a 100644 --- a/include/hw/ppc/spapr_xive.h +++ b/include/hw/ppc/spapr_xive.h @@ -57,7 +57,6 @@ typedef struct SpaprXive { void spapr_xive_pic_print_info(SpaprXive *xive, Monitor *mon); =20 void spapr_xive_hcall_init(SpaprMachineState *spapr); -void spapr_xive_set_tctx_os_cam(XiveTCTX *tctx); void spapr_xive_mmio_set_enabled(SpaprXive *xive, bool enable); void spapr_xive_map_mmio(SpaprXive *xive); =20 diff --git a/include/hw/ppc/xive.h b/include/hw/ppc/xive.h index 99381639f50c..e273069c25a9 100644 --- a/include/hw/ppc/xive.h +++ b/include/hw/ppc/xive.h @@ -319,6 +319,7 @@ typedef struct XiveTCTX { qemu_irq os_output; =20 uint8_t regs[XIVE_TM_RING_COUNT * XIVE_TM_RING_SIZE]; + uint32_t os_cam; } XiveTCTX; =20 /* @@ -414,7 +415,8 @@ void xive_tctx_tm_write(XiveTCTX *tctx, hwaddr offset= , uint64_t value, uint64_t xive_tctx_tm_read(XiveTCTX *tctx, hwaddr offset, unsigned size)= ; =20 void xive_tctx_pic_print_info(XiveTCTX *tctx, Monitor *mon); -Object *xive_tctx_create(Object *cpu, XiveRouter *xrtr, Error **errp); +Object *xive_tctx_create(Object *cpu, XiveRouter *xrtr, uint32_t os_cam, + Error **errp); void xive_tctx_reset(XiveTCTX *tctx); =20 static inline uint32_t xive_nvt_cam_line(uint8_t nvt_blk, uint32_t nvt_i= dx) diff --git a/hw/intc/spapr_xive.c b/hw/intc/spapr_xive.c index 0c3acf1a4192..71f138512a1c 100644 --- a/hw/intc/spapr_xive.c +++ b/hw/intc/spapr_xive.c @@ -205,21 +205,13 @@ void spapr_xive_mmio_set_enabled(SpaprXive *xive, b= ool enable) memory_region_set_enabled(&xive->end_source.esb_mmio, false); } =20 -/* - * When a Virtual Processor is scheduled to run on a HW thread, the - * hypervisor pushes its identifier in the OS CAM line. Emulate the - * same behavior under QEMU. - */ -void spapr_xive_set_tctx_os_cam(XiveTCTX *tctx) +static uint32_t spapr_xive_get_os_cam(PowerPCCPU *cpu) { uint8_t nvt_blk; uint32_t nvt_idx; - uint32_t nvt_cam; - - spapr_xive_cpu_to_nvt(POWERPC_CPU(tctx->cs), &nvt_blk, &nvt_idx); =20 - nvt_cam =3D cpu_to_be32(TM_QW1W2_VO | xive_nvt_cam_line(nvt_blk, nvt= _idx)); - memcpy(&tctx->regs[TM_QW1_OS + TM_WORD2], &nvt_cam, 4); + spapr_xive_cpu_to_nvt(cpu, &nvt_blk, &nvt_idx); + return xive_nvt_cam_line(nvt_blk, nvt_idx); } =20 static void spapr_xive_end_reset(XiveEND *end) @@ -537,19 +529,14 @@ static int spapr_xive_cpu_intc_create(SpaprInterrup= tController *intc, SpaprXive *xive =3D SPAPR_XIVE(intc); Object *obj; SpaprCpuState *spapr_cpu =3D spapr_cpu_state(cpu); + uint32_t os_cam =3D spapr_xive_get_os_cam(cpu); =20 - obj =3D xive_tctx_create(OBJECT(cpu), XIVE_ROUTER(xive), errp); + obj =3D xive_tctx_create(OBJECT(cpu), XIVE_ROUTER(xive), os_cam, err= p); if (!obj) { return -1; } =20 spapr_cpu->tctx =3D XIVE_TCTX(obj); - - /* - * (TCG) Early setting the OS CAM line for hotplugged CPUs as they - * don't beneficiate from the reset of the XIVE IRQ backend - */ - spapr_xive_set_tctx_os_cam(spapr_cpu->tctx); return 0; } =20 @@ -650,14 +637,6 @@ static void spapr_xive_dt(SpaprInterruptController *= intc, uint32_t nr_servers, static int spapr_xive_activate(SpaprInterruptController *intc, Error **e= rrp) { SpaprXive *xive =3D SPAPR_XIVE(intc); - CPUState *cs; - - CPU_FOREACH(cs) { - PowerPCCPU *cpu =3D POWERPC_CPU(cs); - - /* (TCG) Set the OS CAM line of the thread interrupt context. */ - spapr_xive_set_tctx_os_cam(spapr_cpu_state(cpu)->tctx); - } =20 if (kvm_enabled()) { int rc =3D spapr_irq_init_kvm(kvmppc_xive_connect, intc, errp); diff --git a/hw/intc/xive.c b/hw/intc/xive.c index 0ae3f9b1efe4..be4f2c974178 100644 --- a/hw/intc/xive.c +++ b/hw/intc/xive.c @@ -566,6 +566,18 @@ static void xive_tctx_reset_handler(void *dev) ipb_to_pipr(tctx->regs[TM_QW1_OS + TM_IPB]); tctx->regs[TM_QW3_HV_PHYS + TM_PIPR] =3D ipb_to_pipr(tctx->regs[TM_QW3_HV_PHYS + TM_IPB]); + + /* + * (TCG) Set the OS CAM line of the thread interrupt context. + * + * When a Virtual Processor is scheduled to run on a HW thread, + * the hypervisor pushes its identifier in the OS CAM line. + * Emulate the same behavior under QEMU. + */ + if (tctx->os_cam) { + uint32_t qw1w2 =3D cpu_to_be32(TM_QW1W2_VO | tctx->os_cam); + memcpy(&tctx->regs[TM_QW1_OS + TM_WORD2], &qw1w2, 4); + } } =20 void xive_tctx_reset(XiveTCTX *tctx) @@ -667,11 +679,17 @@ static const VMStateDescription vmstate_xive_tctx =3D= { }, }; =20 +static Property xive_tctx_properties[] =3D { + DEFINE_PROP_UINT32("os-cam", XiveTCTX, os_cam, 0), + DEFINE_PROP_END_OF_LIST(), +}; + static void xive_tctx_class_init(ObjectClass *klass, void *data) { DeviceClass *dc =3D DEVICE_CLASS(klass); =20 dc->desc =3D "XIVE Interrupt Thread Context"; + dc->props =3D xive_tctx_properties; dc->realize =3D xive_tctx_realize; dc->unrealize =3D xive_tctx_unrealize; dc->vmsd =3D &vmstate_xive_tctx; @@ -689,7 +707,8 @@ static const TypeInfo xive_tctx_info =3D { .class_init =3D xive_tctx_class_init, }; =20 -Object *xive_tctx_create(Object *cpu, XiveRouter *xrtr, Error **errp) +Object *xive_tctx_create(Object *cpu, XiveRouter *xrtr, uint32_t os_cam, + Error **errp) { Error *local_err =3D NULL; Object *obj; @@ -698,6 +717,7 @@ Object *xive_tctx_create(Object *cpu, XiveRouter *xrt= r, Error **errp) object_property_add_child(cpu, TYPE_XIVE_TCTX, obj, &error_abort); object_unref(obj); object_property_add_const_link(obj, "cpu", cpu, &error_abort); + object_property_set_int(obj, os_cam, "os-cam", &local_err); object_property_set_bool(obj, true, "realized", &local_err); if (local_err) { goto error; diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index 7cf64b6d2533..99c06842573e 100644 --- a/hw/ppc/pnv.c +++ b/hw/ppc/pnv.c @@ -806,7 +806,8 @@ static void pnv_chip_power9_intc_create(PnvChip *chip= , PowerPCCPU *cpu, * controller object is initialized afterwards. Hopefully, it's * only used at runtime. */ - obj =3D xive_tctx_create(OBJECT(cpu), XIVE_ROUTER(&chip9->xive), &lo= cal_err); + obj =3D xive_tctx_create(OBJECT(cpu), XIVE_ROUTER(&chip9->xive), 0, + &local_err); if (local_err) { error_propagate(errp, local_err); return; --=20 2.21.0