From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail.linutronix.de (193.142.43.55:993) by crypto-ml.lab.linutronix.de with IMAP4-SSL for ; 18 Oct 2019 00:20:15 -0000 Received: from mga06.intel.com ([134.134.136.31]) by Galois.linutronix.de with esmtps (TLS1.2:DHE_RSA_AES_256_CBC_SHA256:256) (Exim 4.80) (envelope-from ) id 1iLG05-0000bV-GX for speck@linutronix.de; Fri, 18 Oct 2019 02:20:15 +0200 Date: Thu, 17 Oct 2019 17:14:07 -0700 From: Pawan Gupta Subject: [MODERATED] Re: [PATCH v5 08/11] TAAv5 8 Message-ID: <20191018001407.GA28905@guptapadev.amr> References: <20191014210458.GF4957@zn.tnic> <20191015103454.GW317@dhcp22.suse.cz> <20191016075434.GL317@dhcp22.suse.cz> <20191016092333.GQ317@dhcp22.suse.cz> MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit To: speck@linutronix.de List-ID: On Wed, Oct 16, 2019 at 02:15:08PM +0200, speck for Thomas Gleixner wrote: > On Wed, 16 Oct 2019, speck for Michal Hocko wrote: > > Is tsx=auto going to lead to any different state than tsx=on? In other > > words does auto mode make any sense at all? > > Is it only my vacation induced spark of mental sanity or is this whole TAA > thing a complete trainwreck again? > > We're at version 5 and more than 3 month since the first RFC got posted and > we are still debating which CPUs are affected and which migitations are > going to be deployed depending on the CPU advertized misfeatures and the > eventually surfacing microcode? > > Can we please stop this complete waste of time right now and start over > with clarifying the situation? I.e. someone at Intel needs to sit down and > write up a matrix: > > TAA-Affected | MDS_NO | VERW works | TSX_MSR | Resulting action > -------------|--------|------------|---------|----------------- > No | X | X | Y | ? > No | X | X | N | None > Yes | 0 | 0 | 0 | SNAFU > ... | | | | > > You surely can fill in the rest on your own, right? > > And exactly that information wants to be in the admin documentation or in a > separate Documentation/x86/taa.rst as well. Below is the matrix for the impact of tsx= cmdline options on state of TAA mitigation, VERW behavior and TSX feature for various combinations of MSR_IA32_ARCH_CAPABILITIES bits. 1. tsx=auto +----------+----------+----------------+---------------+--------------+-------------------+ | MSR_IA32_ARCH_CAPABILITIES bits | Result with cmdline tsx=auto | +----------+----------+----------------+---------------+--------------+-------------------+ | TAA_NO | MDS_NO | TSX_CTRL_MSR | VERW clears | TSX state | TAA mitigation | | | | | CPU buffers | after bootup | | +==========+==========+================+===============+==============+===================+ | 0 | 0 | 0 | Yes | HW default | Same as MDS | +----------+----------+----------------+---------------+--------------+-------------------+ | 0 | 0 | 1 | Invalid case | Invalid case | Invalid case | +----------+----------+----------------+---------------+--------------+-------------------+ | 0 | 1 | 0 | No | HW default | Need ucode update | +----------+----------+----------------+---------------+--------------+-------------------+ | 0 | 1 | 1 | Yes | TSX disabled | TSX disabled | +----------+----------+----------------+---------------+--------------+-------------------+ | 1 | X | 1 | X | TSX enabled | None needed | +----------+----------+----------------+---------------+--------------+-------------------+ 2. tsx=on +----------+----------+----------------+---------------+--------------+-------------------+ | MSR_IA32_ARCH_CAPABILITIES bits | Result with cmdline tsx=on | +----------+----------+----------------+---------------+--------------+-------------------+ | TAA_NO | MDS_NO | TSX_CTRL_MSR | VERW clears | TSX state | TAA mitigation | | | | | CPU buffers | after bootup | | +==========+==========+================+===============+==============+===================+ | 0 | 0 | 0 | Yes | HW default | Same as MDS | +----------+----------+----------------+---------------+--------------+-------------------+ | 0 | 0 | 1 | Invalid case | Invalid case | Invalid case | +----------+----------+----------------+---------------+--------------+-------------------+ | 0 | 1 | 0 | No | HW default | Need ucode update | +----------+----------+----------------+---------------+--------------+-------------------+ | 0 | 1 | 1 | Yes | TSX enabled | Same as MDS | +----------+----------+----------------+---------------+--------------+-------------------+ | 1 | X | 1 | X | TSX enabled | None needed | +----------+----------+----------------+---------------+--------------+-------------------+ 3. tsx=off +----------+----------+----------------+---------------+--------------+-------------------+ | MSR_IA32_ARCH_CAPABILITIES bits | Result with cmdline tsx=off | +----------+----------+----------------+---------------+--------------+-------------------+ | TAA_NO | MDS_NO | TSX_CTRL_MSR | VERW clears | TSX state | TAA mitigation | | | | | CPU buffers | after bootup | | +==========+==========+================+===============+==============+===================+ | 0 | 0 | 0 | Yes | HW default | Same as MDS | +----------+----------+----------------+---------------+--------------+-------------------+ | 0 | 0 | 1 | Invalid case | Invalid case | Invalid case | +----------+----------+----------------+---------------+--------------+-------------------+ | 0 | 1 | 0 | No | HW default | Need ucode update | +----------+----------+----------------+---------------+--------------+-------------------+ | 0 | 1 | 1 | Yes | TSX disabled | TSX disabled | +----------+----------+----------------+---------------+--------------+-------------------+ | 1 | X | 1 | X | TSX disabled | None needed | +----------+----------+----------------+---------------+--------------+-------------------+ Let me know if there are any questions. Thanks, Pawan