From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail.linutronix.de (193.142.43.55:993) by crypto-ml.lab.linutronix.de with IMAP4-SSL for ; 21 Oct 2019 20:34:48 -0000 Received: from us-smtp-delivery-1.mimecast.com ([207.211.31.120] helo=us-smtp-1.mimecast.com) by Galois.linutronix.de with esmtps (TLS1.2:DHE_RSA_AES_256_CBC_SHA256:256) (Exim 4.80) (envelope-from ) id 1iMeO7-0001P3-1j for speck@linutronix.de; Mon, 21 Oct 2019 22:34:47 +0200 Received: from smtp.corp.redhat.com (int-mx03.intmail.prod.int.phx2.redhat.com [10.5.11.13]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 93D4A47B for ; Mon, 21 Oct 2019 20:34:42 +0000 (UTC) Received: from treble (ovpn-124-143.rdu2.redhat.com [10.10.124.143]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 2BB0C608A5 for ; Mon, 21 Oct 2019 20:34:42 +0000 (UTC) Date: Mon, 21 Oct 2019 15:34:40 -0500 From: Josh Poimboeuf Subject: [MODERATED] Re: [PATCH v5 08/11] TAAv5 8 Message-ID: <20191021203440.73dl2q5lucu5eiaq@treble> References: <20191015103454.GW317@dhcp22.suse.cz> <20191016075434.GL317@dhcp22.suse.cz> <20191016092333.GQ317@dhcp22.suse.cz> <20191018001407.GA28905@guptapadev.amr> <20191021125429.GP9379@dhcp22.suse.cz> <20191021200139.GA23497@guptapadev.amr> <20191021203338.uhkjj2ixa36ysdvm@treble> MIME-Version: 1.0 In-Reply-To: <20191021203338.uhkjj2ixa36ysdvm@treble> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Content-Disposition: inline To: speck@linutronix.de List-ID: On Mon, Oct 21, 2019 at 03:33:38PM -0500, Josh Poimboeuf wrote: > On Mon, Oct 21, 2019 at 01:01:39PM -0700, speck for Pawan Gupta wrote: > > On Mon, Oct 21, 2019 at 02:54:29PM +0200, speck for Michal Hocko wrote: > > > On Thu 17-10-19 17:14:07, speck for Pawan Gupta wrote: > > > [...] > > > > Let me know if there are any questions. > > >=20 > > > is there any list of CPUs that would benefit from tsx=3Dauto compared= to > > > tsx=3Don? In other words do we really need both? > >=20 > > Below is the list of TAA affected CPUs that will get TSX_CTRL MSR. > >=20 > > +----------------------------+------------------+------------+ > > | Name | Family / model | Stepping | > > +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D+=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D+=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D+ > > | Whiskey Lake (ULT refresh) | 06_8E | 0xC | > > +----------------------------+------------------+------------+ > > | 2nd gen Cascade Lake | 06_55 | 6, 7 | > > +----------------------------+------------------+------------+ > > | Coffee Lake R | 06_9E | 0xD | > > +----------------------------+------------------+------------+ > >=20 > > tsx=3Dauto on these CPUs will disable TSX. > > tsx=3Don will keep TSX enabled. [ Please ignore my previous email, it had a glaring typo ] Just to clarify, is this list identical to the list of CPUs which are vulnerable to TAA and have MDS_NO=3D1? --=20 Josh