From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail.linutronix.de (193.142.43.55:993) by crypto-ml.lab.linutronix.de with IMAP4-SSL for ; 22 Oct 2019 17:25:20 -0000 Received: from us-smtp-1.mimecast.com ([207.211.31.81] helo=us-smtp-delivery-1.mimecast.com) by Galois.linutronix.de with esmtps (TLS1.2:DHE_RSA_AES_256_CBC_SHA256:256) (Exim 4.80) (envelope-from ) id 1iMxuJ-0003Nq-AT for speck@linutronix.de; Tue, 22 Oct 2019 19:25:19 +0200 Received: from smtp.corp.redhat.com (int-mx07.intmail.prod.int.phx2.redhat.com [10.5.11.22]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 6CB701800D6A for ; Tue, 22 Oct 2019 17:25:10 +0000 (UTC) Received: from treble (ovpn-124-213.rdu2.redhat.com [10.10.124.213]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 1AD3F1001925 for ; Tue, 22 Oct 2019 17:25:10 +0000 (UTC) Date: Tue, 22 Oct 2019 12:25:08 -0500 From: Josh Poimboeuf Subject: [MODERATED] Re: [PATCH v7 01/10] TAAv7 1 Message-ID: <20191022172508.7h7d523puvepfjap@treble> References: =?utf-8?q?=3Cfc886d6e7492f33d2747d0f13cf4da97cec9a680=2E1571688957=2Egi?= =?utf-8?q?t=2Epawan=2Ekumar=2Egupta=40linux=2Eintel=2Ecom=3E?= MIME-Version: 1.0 In-Reply-To: =?utf-8?q?=3Cfc886d6e7492f33d2747d0f13cf4da97cec9a680=2E15716?= =?utf-8?q?88957=2Egit=2Epawan=2Ekumar=2Egupta=40linux=2Eintel=2Ecom=3E?= Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit To: speck@linutronix.de List-ID: On Mon, Oct 21, 2019 at 01:23:02PM -0700, speck for Pawan Gupta wrote: > From: Pawan Gupta > Subject: [PATCH v7 01/10] x86/tsx: Add enumeration support for IA32_TSX_CTRL > MSR > > Transactional Synchronization Extensions (TSX) may be used on certain > processors as part of a speculative side channel attack. A microcode > update for existing processors that are vulnerable to this attack will > add a new MSR, IA32_TSX_CTRL to allow the system administrator the > option to disable TSX as one of the possible mitigations. [Note that > future processors that are not vulnerable will also support the > IA32_TSX_CTRL MSR]. Add defines for the new IA32_TSX_CTRL MSR and its > bits. > > TSX has two sub-features: > > 1. Restricted Transactional Memory (RTM) is an explicitly-used feature > where new instructions begin and end TSX transactions. > 2. Hardware Lock Elision (HLE) is implicitly used when certain kinds of > "old" style locks are used by software. > > Bit 7 of the IA32_ARCH_CAPABILITIES indicates the presence of the > IA32_TSX_CTRL MSR. > > There are two control bits in IA32_TSX_CTRL MSR: > > Bit 0: When set it disables the Restricted Transactional Memory (RTM) > sub-feature of TSX (will force all transactions to abort on the > XBEGIN instruction). > > Bit 1: When set it disables the enumeration of the RTM and HLE feature > (i.e. it will make CPUID(EAX=7).EBX{bit4} and > CPUID(EAX=7).EBX{bit11} read as 0). > > The other TSX sub-feature, Hardware Lock Elision (HLE), is unconditionally > disabled How is HLE unconditionally disabled? Is it done by the above mentioned microcode? Is there a way to enable it? > but still enumerated as present by CPUID(EAX=7).EBX{bit4}. ... unless disabled via bit 1 of IA32_TSX_CTRL_MSR? [ Also please add the above clarifications to the patch description. ] -- Josh